phy/marvell/phy-pxa-usb.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
0004  * Copyright (C) 2018 Lubomir Rintel <lkundrak@v3.sk>
0005  */
0006
0007 #include <dt-bindings/phy/phy.h>
0008 #include <linux/clk.h>
0009 #include <linux/delay.h>
0010 #include <linux/io.h>
0011 #include <linux/module.h>
0012 #include <linux/of_address.h>
0013 #include <linux/phy/phy.h>
0014 #include <linux/platform_device.h>
0015
0016 /* phy regs */
0017 #define UTMI_REVISION       0x0
0018 #define UTMI_CTRL       0x4
0019 #define UTMI_PLL        0x8
0020 #define UTMI_TX         0xc
0021 #define UTMI_RX         0x10
0022 #define UTMI_IVREF      0x14
0023 #define UTMI_T0         0x18
0024 #define UTMI_T1         0x1c
0025 #define UTMI_T2         0x20
0026 #define UTMI_T3         0x24
0027 #define UTMI_T4         0x28
0028 #define UTMI_T5         0x2c
0029 #define UTMI_RESERVE        0x30
0030 #define UTMI_USB_INT        0x34
0031 #define UTMI_DBG_CTL        0x38
0032 #define UTMI_OTG_ADDON      0x3c
0033
0034 /* For UTMICTRL Register */
0035 #define UTMI_CTRL_USB_CLK_EN                    (1 << 31)
0036 /* pxa168 */
0037 #define UTMI_CTRL_SUSPEND_SET1                  (1 << 30)
0038 #define UTMI_CTRL_SUSPEND_SET2                  (1 << 29)
0039 #define UTMI_CTRL_RXBUF_PDWN                    (1 << 24)
0040 #define UTMI_CTRL_TXBUF_PDWN                    (1 << 11)
0041
0042 #define UTMI_CTRL_INPKT_DELAY_SHIFT             30
0043 #define UTMI_CTRL_INPKT_DELAY_SOF_SHIFT     28
0044 #define UTMI_CTRL_PU_REF_SHIFT          20
0045 #define UTMI_CTRL_ARC_PULLDN_SHIFT              12
0046 #define UTMI_CTRL_PLL_PWR_UP_SHIFT              1
0047 #define UTMI_CTRL_PWR_UP_SHIFT                  0
0048
0049 /* For UTMI_PLL Register */
0050 #define UTMI_PLL_PLLCALI12_SHIFT        29
0051 #define UTMI_PLL_PLLCALI12_MASK         (0x3 << 29)
0052
0053 #define UTMI_PLL_PLLVDD18_SHIFT         27
0054 #define UTMI_PLL_PLLVDD18_MASK          (0x3 << 27)
0055
0056 #define UTMI_PLL_PLLVDD12_SHIFT         25
0057 #define UTMI_PLL_PLLVDD12_MASK          (0x3 << 25)
0058
0059 #define UTMI_PLL_CLK_BLK_EN_SHIFT               24
0060 #define CLK_BLK_EN                              (0x1 << 24)
0061 #define PLL_READY                               (0x1 << 23)
0062 #define KVCO_EXT                                (0x1 << 22)
0063 #define VCOCAL_START                            (0x1 << 21)
0064
0065 #define UTMI_PLL_KVCO_SHIFT         15
0066 #define UTMI_PLL_KVCO_MASK                      (0x7 << 15)
0067
0068 #define UTMI_PLL_ICP_SHIFT          12
0069 #define UTMI_PLL_ICP_MASK                       (0x7 << 12)
0070
0071 #define UTMI_PLL_FBDIV_SHIFT                    4
0072 #define UTMI_PLL_FBDIV_MASK                     (0xFF << 4)
0073
0074 #define UTMI_PLL_REFDIV_SHIFT                   0
0075 #define UTMI_PLL_REFDIV_MASK                    (0xF << 0)
0076
0077 /* For UTMI_TX Register */
0078 #define UTMI_TX_REG_EXT_FS_RCAL_SHIFT       27
0079 #define UTMI_TX_REG_EXT_FS_RCAL_MASK        (0xf << 27)
0080
0081 #define UTMI_TX_REG_EXT_FS_RCAL_EN_SHIFT    26
0082 #define UTMI_TX_REG_EXT_FS_RCAL_EN_MASK     (0x1 << 26)
0083
0084 #define UTMI_TX_TXVDD12_SHIFT                   22
0085 #define UTMI_TX_TXVDD12_MASK                    (0x3 << 22)
0086
0087 #define UTMI_TX_CK60_PHSEL_SHIFT                17
0088 #define UTMI_TX_CK60_PHSEL_MASK                 (0xf << 17)
0089
0090 #define UTMI_TX_IMPCAL_VTH_SHIFT                14
0091 #define UTMI_TX_IMPCAL_VTH_MASK                 (0x7 << 14)
0092
0093 #define REG_RCAL_START                          (0x1 << 12)
0094
0095 #define UTMI_TX_LOW_VDD_EN_SHIFT                11
0096
0097 #define UTMI_TX_AMP_SHIFT           0
0098 #define UTMI_TX_AMP_MASK            (0x7 << 0)
0099
0100 /* For UTMI_RX Register */
0101 #define UTMI_REG_SQ_LENGTH_SHIFT                15
0102 #define UTMI_REG_SQ_LENGTH_MASK                 (0x3 << 15)
0103
0104 #define UTMI_RX_SQ_THRESH_SHIFT                 4
0105 #define UTMI_RX_SQ_THRESH_MASK                  (0xf << 4)
0106
0107 #define UTMI_OTG_ADDON_OTG_ON           (1 << 0)
0108
0109 enum pxa_usb_phy_version {
0110     PXA_USB_PHY_MMP2,
0111     PXA_USB_PHY_PXA910,
0112     PXA_USB_PHY_PXA168,
0113 };
0114
0115 struct pxa_usb_phy {
0116     struct phy *phy;
0117     void __iomem *base;
0118     enum pxa_usb_phy_version version;
0119 };
0120
0121 /*****************************************************************************
0122  * The registers read/write routines
0123  *****************************************************************************/
0124
0125 static unsigned int u2o_get(void __iomem *base, unsigned int offset)
0126 {
0127     return readl_relaxed(base + offset);
0128 }
0129
0130 static void u2o_set(void __iomem *base, unsigned int offset,
0131         unsigned int value)
0132 {
0133     u32 reg;
0134
0135     reg = readl_relaxed(base + offset);
0136     reg |= value;
0137     writel_relaxed(reg, base + offset);
0138     readl_relaxed(base + offset);
0139 }
0140
0141 static void u2o_clear(void __iomem *base, unsigned int offset,
0142         unsigned int value)
0143 {
0144     u32 reg;
0145
0146     reg = readl_relaxed(base + offset);
0147     reg &= ~value;
0148     writel_relaxed(reg, base + offset);
0149     readl_relaxed(base + offset);
0150 }
0151
0152 static void u2o_write(void __iomem *base, unsigned int offset,
0153         unsigned int value)
0154 {
0155     writel_relaxed(value, base + offset);
0156     readl_relaxed(base + offset);
0157 }
0158
0159 static int pxa_usb_phy_init(struct phy *phy)
0160 {
0161     struct pxa_usb_phy *pxa_usb_phy = phy_get_drvdata(phy);
0162     void __iomem *base = pxa_usb_phy->base;
0163     int loops;
0164
0165     dev_info(&phy->dev, "initializing Marvell PXA USB PHY");
0166
0167     /* Initialize the USB PHY power */
0168     if (pxa_usb_phy->version == PXA_USB_PHY_PXA910) {
0169         u2o_set(base, UTMI_CTRL, (1<<UTMI_CTRL_INPKT_DELAY_SOF_SHIFT)
0170             | (1<<UTMI_CTRL_PU_REF_SHIFT));
0171     }
0172
0173     u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT);
0174     u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT);
0175
0176     /* UTMI_PLL settings */
0177     u2o_clear(base, UTMI_PLL, UTMI_PLL_PLLVDD18_MASK
0178         | UTMI_PLL_PLLVDD12_MASK | UTMI_PLL_PLLCALI12_MASK
0179         | UTMI_PLL_FBDIV_MASK | UTMI_PLL_REFDIV_MASK
0180         | UTMI_PLL_ICP_MASK | UTMI_PLL_KVCO_MASK);
0181
0182     u2o_set(base, UTMI_PLL, 0xee<<UTMI_PLL_FBDIV_SHIFT
0183         | 0xb<<UTMI_PLL_REFDIV_SHIFT | 3<<UTMI_PLL_PLLVDD18_SHIFT
0184         | 3<<UTMI_PLL_PLLVDD12_SHIFT | 3<<UTMI_PLL_PLLCALI12_SHIFT
0185         | 1<<UTMI_PLL_ICP_SHIFT | 3<<UTMI_PLL_KVCO_SHIFT);
0186
0187     /* UTMI_TX */
0188     u2o_clear(base, UTMI_TX, UTMI_TX_REG_EXT_FS_RCAL_EN_MASK
0189         | UTMI_TX_TXVDD12_MASK | UTMI_TX_CK60_PHSEL_MASK
0190         | UTMI_TX_IMPCAL_VTH_MASK | UTMI_TX_REG_EXT_FS_RCAL_MASK
0191         | UTMI_TX_AMP_MASK);
0192     u2o_set(base, UTMI_TX, 3<<UTMI_TX_TXVDD12_SHIFT
0193         | 4<<UTMI_TX_CK60_PHSEL_SHIFT | 4<<UTMI_TX_IMPCAL_VTH_SHIFT
0194         | 8<<UTMI_TX_REG_EXT_FS_RCAL_SHIFT | 3<<UTMI_TX_AMP_SHIFT);
0195
0196     /* UTMI_RX */
0197     u2o_clear(base, UTMI_RX, UTMI_RX_SQ_THRESH_MASK
0198         | UTMI_REG_SQ_LENGTH_MASK);
0199     u2o_set(base, UTMI_RX, 7<<UTMI_RX_SQ_THRESH_SHIFT
0200         | 2<<UTMI_REG_SQ_LENGTH_SHIFT);
0201
0202     /* UTMI_IVREF */
0203     if (pxa_usb_phy->version == PXA_USB_PHY_PXA168) {
0204         /*
0205          * fixing Microsoft Altair board interface with NEC hub issue -
0206          * Set UTMI_IVREF from 0x4a3 to 0x4bf
0207          */
0208         u2o_write(base, UTMI_IVREF, 0x4bf);
0209     }
0210
0211     /* toggle VCOCAL_START bit of UTMI_PLL */
0212     udelay(200);
0213     u2o_set(base, UTMI_PLL, VCOCAL_START);
0214     udelay(40);
0215     u2o_clear(base, UTMI_PLL, VCOCAL_START);
0216
0217     /* toggle REG_RCAL_START bit of UTMI_TX */
0218     udelay(400);
0219     u2o_set(base, UTMI_TX, REG_RCAL_START);
0220     udelay(40);
0221     u2o_clear(base, UTMI_TX, REG_RCAL_START);
0222     udelay(400);
0223
0224     /* Make sure PHY PLL is ready */
0225     loops = 0;
0226     while ((u2o_get(base, UTMI_PLL) & PLL_READY) == 0) {
0227         mdelay(1);
0228         loops++;
0229         if (loops > 100) {
0230             dev_warn(&phy->dev, "calibrate timeout, UTMI_PLL %x\n",
0231                         u2o_get(base, UTMI_PLL));
0232             break;
0233         }
0234     }
0235
0236     if (pxa_usb_phy->version == PXA_USB_PHY_PXA168) {
0237         u2o_set(base, UTMI_RESERVE, 1 << 5);
0238         /* Turn on UTMI PHY OTG extension */
0239         u2o_write(base, UTMI_OTG_ADDON, 1);
0240     }
0241
0242     return 0;
0243
0244 }
0245
0246 static int pxa_usb_phy_exit(struct phy *phy)
0247 {
0248     struct pxa_usb_phy *pxa_usb_phy = phy_get_drvdata(phy);
0249     void __iomem *base = pxa_usb_phy->base;
0250
0251     dev_info(&phy->dev, "deinitializing Marvell PXA USB PHY");
0252
0253     if (pxa_usb_phy->version == PXA_USB_PHY_PXA168)
0254         u2o_clear(base, UTMI_OTG_ADDON, UTMI_OTG_ADDON_OTG_ON);
0255
0256     u2o_clear(base, UTMI_CTRL, UTMI_CTRL_RXBUF_PDWN);
0257     u2o_clear(base, UTMI_CTRL, UTMI_CTRL_TXBUF_PDWN);
0258     u2o_clear(base, UTMI_CTRL, UTMI_CTRL_USB_CLK_EN);
0259     u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT);
0260     u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT);
0261
0262     return 0;
0263 }
0264
0265 static const struct phy_ops pxa_usb_phy_ops = {
0266     .init   = pxa_usb_phy_init,
0267     .exit   = pxa_usb_phy_exit,
0268     .owner  = THIS_MODULE,
0269 };
0270
0271 static const struct of_device_id pxa_usb_phy_of_match[] = {
0272     {
0273         .compatible = "marvell,mmp2-usb-phy",
0274         .data = (void *)PXA_USB_PHY_MMP2,
0275     }, {
0276         .compatible = "marvell,pxa910-usb-phy",
0277         .data = (void *)PXA_USB_PHY_PXA910,
0278     }, {
0279         .compatible = "marvell,pxa168-usb-phy",
0280         .data = (void *)PXA_USB_PHY_PXA168,
0281     },
0282     { },
0283 };
0284 MODULE_DEVICE_TABLE(of, pxa_usb_phy_of_match);
0285
0286 static int pxa_usb_phy_probe(struct platform_device *pdev)
0287 {
0288     struct device *dev = &pdev->dev;
0289     struct pxa_usb_phy *pxa_usb_phy;
0290     struct phy_provider *provider;
0291     const struct of_device_id *of_id;
0292
0293     pxa_usb_phy = devm_kzalloc(dev, sizeof(struct pxa_usb_phy), GFP_KERNEL);
0294     if (!pxa_usb_phy)
0295         return -ENOMEM;
0296
0297     of_id = of_match_node(pxa_usb_phy_of_match, dev->of_node);
0298     if (of_id)
0299         pxa_usb_phy->version = (enum pxa_usb_phy_version)of_id->data;
0300     else
0301         pxa_usb_phy->version = PXA_USB_PHY_MMP2;
0302
0303     pxa_usb_phy->base = devm_platform_ioremap_resource(pdev, 0);
0304     if (IS_ERR(pxa_usb_phy->base)) {
0305         dev_err(dev, "failed to remap PHY regs\n");
0306         return PTR_ERR(pxa_usb_phy->base);
0307     }
0308
0309     pxa_usb_phy->phy = devm_phy_create(dev, NULL, &pxa_usb_phy_ops);
0310     if (IS_ERR(pxa_usb_phy->phy)) {
0311         dev_err(dev, "failed to create PHY\n");
0312         return PTR_ERR(pxa_usb_phy->phy);
0313     }
0314
0315     phy_set_drvdata(pxa_usb_phy->phy, pxa_usb_phy);
0316     provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0317     if (IS_ERR(provider)) {
0318         dev_err(dev, "failed to register PHY provider\n");
0319         return PTR_ERR(provider);
0320     }
0321
0322     if (!dev->of_node) {
0323         phy_create_lookup(pxa_usb_phy->phy, "usb", "mv-udc");
0324         phy_create_lookup(pxa_usb_phy->phy, "usb", "pxa-u2oehci");
0325         phy_create_lookup(pxa_usb_phy->phy, "usb", "mv-otg");
0326     }
0327
0328     dev_info(dev, "Marvell PXA USB PHY");
0329     return 0;
0330 }
0331
0332 static struct platform_driver pxa_usb_phy_driver = {
0333     .probe      = pxa_usb_phy_probe,
0334     .driver     = {
0335         .name   = "pxa-usb-phy",
0336         .of_match_table = pxa_usb_phy_of_match,
0337     },
0338 };
0339 module_platform_driver(pxa_usb_phy_driver);
0340
0341 MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>");
0342 MODULE_DESCRIPTION("Marvell PXA USB PHY Driver");
0343 MODULE_LICENSE("GPL v2");