phy/marvell/phy-pxa-28nm-usb2.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2015 Linaro, Ltd.
0004  * Rob Herring <robh@kernel.org>
0005  *
0006  * Based on vendor driver:
0007  * Copyright (C) 2013 Marvell Inc.
0008  * Author: Chao Xie <xiechao.mail@gmail.com>
0009  */
0010
0011 #include <linux/delay.h>
0012 #include <linux/slab.h>
0013 #include <linux/of.h>
0014 #include <linux/of_device.h>
0015 #include <linux/io.h>
0016 #include <linux/iopoll.h>
0017 #include <linux/err.h>
0018 #include <linux/clk.h>
0019 #include <linux/module.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/phy/phy.h>
0022
0023 /* USB PXA1928 PHY mapping */
0024 #define PHY_28NM_PLL_REG0           0x0
0025 #define PHY_28NM_PLL_REG1           0x4
0026 #define PHY_28NM_CAL_REG            0x8
0027 #define PHY_28NM_TX_REG0            0x0c
0028 #define PHY_28NM_TX_REG1            0x10
0029 #define PHY_28NM_RX_REG0            0x14
0030 #define PHY_28NM_RX_REG1            0x18
0031 #define PHY_28NM_DIG_REG0           0x1c
0032 #define PHY_28NM_DIG_REG1           0x20
0033 #define PHY_28NM_TEST_REG0          0x24
0034 #define PHY_28NM_TEST_REG1          0x28
0035 #define PHY_28NM_MOC_REG            0x2c
0036 #define PHY_28NM_PHY_RESERVE            0x30
0037 #define PHY_28NM_OTG_REG            0x34
0038 #define PHY_28NM_CHRG_DET           0x38
0039 #define PHY_28NM_CTRL_REG0          0xc4
0040 #define PHY_28NM_CTRL_REG1          0xc8
0041 #define PHY_28NM_CTRL_REG2          0xd4
0042 #define PHY_28NM_CTRL_REG3          0xdc
0043
0044 /* PHY_28NM_PLL_REG0 */
0045 #define PHY_28NM_PLL_READY          BIT(31)
0046
0047 #define PHY_28NM_PLL_SELLPFR_SHIFT      28
0048 #define PHY_28NM_PLL_SELLPFR_MASK       (0x3 << 28)
0049
0050 #define PHY_28NM_PLL_FBDIV_SHIFT        16
0051 #define PHY_28NM_PLL_FBDIV_MASK         (0x1ff << 16)
0052
0053 #define PHY_28NM_PLL_ICP_SHIFT          8
0054 #define PHY_28NM_PLL_ICP_MASK           (0x7 << 8)
0055
0056 #define PHY_28NM_PLL_REFDIV_SHIFT       0
0057 #define PHY_28NM_PLL_REFDIV_MASK        0x7f
0058
0059 /* PHY_28NM_PLL_REG1 */
0060 #define PHY_28NM_PLL_PU_BY_REG          BIT(1)
0061
0062 #define PHY_28NM_PLL_PU_PLL         BIT(0)
0063
0064 /* PHY_28NM_CAL_REG */
0065 #define PHY_28NM_PLL_PLLCAL_DONE        BIT(31)
0066
0067 #define PHY_28NM_PLL_IMPCAL_DONE        BIT(23)
0068
0069 #define PHY_28NM_PLL_KVCO_SHIFT         16
0070 #define PHY_28NM_PLL_KVCO_MASK          (0x7 << 16)
0071
0072 #define PHY_28NM_PLL_CAL12_SHIFT        20
0073 #define PHY_28NM_PLL_CAL12_MASK         (0x3 << 20)
0074
0075 #define PHY_28NM_IMPCAL_VTH_SHIFT       8
0076 #define PHY_28NM_IMPCAL_VTH_MASK        (0x7 << 8)
0077
0078 #define PHY_28NM_PLLCAL_START_SHIFT     22
0079 #define PHY_28NM_IMPCAL_START_SHIFT     13
0080
0081 /* PHY_28NM_TX_REG0 */
0082 #define PHY_28NM_TX_PU_BY_REG           BIT(25)
0083
0084 #define PHY_28NM_TX_PU_ANA          BIT(24)
0085
0086 #define PHY_28NM_TX_AMP_SHIFT           20
0087 #define PHY_28NM_TX_AMP_MASK            (0x7 << 20)
0088
0089 /* PHY_28NM_RX_REG0 */
0090 #define PHY_28NM_RX_SQ_THRESH_SHIFT     0
0091 #define PHY_28NM_RX_SQ_THRESH_MASK      (0xf << 0)
0092
0093 /* PHY_28NM_RX_REG1 */
0094 #define PHY_28NM_RX_SQCAL_DONE          BIT(31)
0095
0096 /* PHY_28NM_DIG_REG0 */
0097 #define PHY_28NM_DIG_BITSTAFFING_ERR        BIT(31)
0098 #define PHY_28NM_DIG_SYNC_ERR           BIT(30)
0099
0100 #define PHY_28NM_DIG_SQ_FILT_SHIFT      16
0101 #define PHY_28NM_DIG_SQ_FILT_MASK       (0x7 << 16)
0102
0103 #define PHY_28NM_DIG_SQ_BLK_SHIFT       12
0104 #define PHY_28NM_DIG_SQ_BLK_MASK        (0x7 << 12)
0105
0106 #define PHY_28NM_DIG_SYNC_NUM_SHIFT     0
0107 #define PHY_28NM_DIG_SYNC_NUM_MASK      (0x3 << 0)
0108
0109 #define PHY_28NM_PLL_LOCK_BYPASS        BIT(7)
0110
0111 /* PHY_28NM_OTG_REG */
0112 #define PHY_28NM_OTG_CONTROL_BY_PIN     BIT(5)
0113 #define PHY_28NM_OTG_PU_OTG         BIT(4)
0114
0115 #define PHY_28NM_CHGDTC_ENABLE_SWITCH_DM_SHIFT_28 13
0116 #define PHY_28NM_CHGDTC_ENABLE_SWITCH_DP_SHIFT_28 12
0117 #define PHY_28NM_CHGDTC_VSRC_CHARGE_SHIFT_28    10
0118 #define PHY_28NM_CHGDTC_VDAT_CHARGE_SHIFT_28    8
0119 #define PHY_28NM_CHGDTC_CDP_DM_AUTO_SWITCH_SHIFT_28 7
0120 #define PHY_28NM_CHGDTC_DP_DM_SWAP_SHIFT_28 6
0121 #define PHY_28NM_CHGDTC_PU_CHRG_DTC_SHIFT_28    5
0122 #define PHY_28NM_CHGDTC_PD_EN_SHIFT_28      4
0123 #define PHY_28NM_CHGDTC_DCP_EN_SHIFT_28     3
0124 #define PHY_28NM_CHGDTC_CDP_EN_SHIFT_28     2
0125 #define PHY_28NM_CHGDTC_TESTMON_CHRGDTC_SHIFT_28 0
0126
0127 #define PHY_28NM_CTRL1_CHRG_DTC_OUT_SHIFT_28    4
0128 #define PHY_28NM_CTRL1_VBUSDTC_OUT_SHIFT_28 2
0129
0130 #define PHY_28NM_CTRL3_OVERWRITE        BIT(0)
0131 #define PHY_28NM_CTRL3_VBUS_VALID       BIT(4)
0132 #define PHY_28NM_CTRL3_AVALID           BIT(5)
0133 #define PHY_28NM_CTRL3_BVALID           BIT(6)
0134
0135 struct mv_usb2_phy {
0136     struct phy      *phy;
0137     struct platform_device  *pdev;
0138     void __iomem        *base;
0139     struct clk      *clk;
0140 };
0141
0142 static int wait_for_reg(void __iomem *reg, u32 mask, u32 ms)
0143 {
0144     u32 val;
0145
0146     return readl_poll_timeout(reg, val, ((val & mask) == mask),
0147                    1000, 1000 * ms);
0148 }
0149
0150 static int mv_usb2_phy_28nm_init(struct phy *phy)
0151 {
0152     struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy);
0153     struct platform_device *pdev = mv_phy->pdev;
0154     void __iomem *base = mv_phy->base;
0155     u32 reg;
0156     int ret;
0157
0158     clk_prepare_enable(mv_phy->clk);
0159
0160     /* PHY_28NM_PLL_REG0 */
0161     reg = readl(base + PHY_28NM_PLL_REG0) &
0162         ~(PHY_28NM_PLL_SELLPFR_MASK | PHY_28NM_PLL_FBDIV_MASK
0163         | PHY_28NM_PLL_ICP_MASK | PHY_28NM_PLL_REFDIV_MASK);
0164     writel(reg | (0x1 << PHY_28NM_PLL_SELLPFR_SHIFT
0165         | 0xf0 << PHY_28NM_PLL_FBDIV_SHIFT
0166         | 0x3 << PHY_28NM_PLL_ICP_SHIFT
0167         | 0xd << PHY_28NM_PLL_REFDIV_SHIFT),
0168         base + PHY_28NM_PLL_REG0);
0169
0170     /* PHY_28NM_PLL_REG1 */
0171     reg = readl(base + PHY_28NM_PLL_REG1);
0172     writel(reg | PHY_28NM_PLL_PU_PLL | PHY_28NM_PLL_PU_BY_REG,
0173         base + PHY_28NM_PLL_REG1);
0174
0175     /* PHY_28NM_TX_REG0 */
0176     reg = readl(base + PHY_28NM_TX_REG0) & ~PHY_28NM_TX_AMP_MASK;
0177     writel(reg | PHY_28NM_TX_PU_BY_REG | 0x3 << PHY_28NM_TX_AMP_SHIFT |
0178         PHY_28NM_TX_PU_ANA,
0179         base + PHY_28NM_TX_REG0);
0180
0181     /* PHY_28NM_RX_REG0 */
0182     reg = readl(base + PHY_28NM_RX_REG0) & ~PHY_28NM_RX_SQ_THRESH_MASK;
0183     writel(reg | 0xa << PHY_28NM_RX_SQ_THRESH_SHIFT,
0184         base + PHY_28NM_RX_REG0);
0185
0186     /* PHY_28NM_DIG_REG0 */
0187     reg = readl(base + PHY_28NM_DIG_REG0) &
0188         ~(PHY_28NM_DIG_BITSTAFFING_ERR | PHY_28NM_DIG_SYNC_ERR |
0189         PHY_28NM_DIG_SQ_FILT_MASK | PHY_28NM_DIG_SQ_BLK_MASK |
0190         PHY_28NM_DIG_SYNC_NUM_MASK);
0191     writel(reg | (0x1 << PHY_28NM_DIG_SYNC_NUM_SHIFT |
0192         PHY_28NM_PLL_LOCK_BYPASS),
0193         base + PHY_28NM_DIG_REG0);
0194
0195     /* PHY_28NM_OTG_REG */
0196     reg = readl(base + PHY_28NM_OTG_REG) | PHY_28NM_OTG_PU_OTG;
0197     writel(reg & ~PHY_28NM_OTG_CONTROL_BY_PIN, base + PHY_28NM_OTG_REG);
0198
0199     /*
0200      *  Calibration Timing
0201      *         ____________________________
0202      *  CAL START   ___|
0203      *             ____________________
0204      *  CAL_DONE    ___________|
0205      *         | 400us |
0206      */
0207
0208     /* Make sure PHY Calibration is ready */
0209     ret = wait_for_reg(base + PHY_28NM_CAL_REG,
0210                PHY_28NM_PLL_PLLCAL_DONE | PHY_28NM_PLL_IMPCAL_DONE,
0211                100);
0212     if (ret) {
0213         dev_warn(&pdev->dev, "USB PHY PLL calibrate not done after 100mS.");
0214         goto err_clk;
0215     }
0216     ret = wait_for_reg(base + PHY_28NM_RX_REG1,
0217                PHY_28NM_RX_SQCAL_DONE, 100);
0218     if (ret) {
0219         dev_warn(&pdev->dev, "USB PHY RX SQ calibrate not done after 100mS.");
0220         goto err_clk;
0221     }
0222     /* Make sure PHY PLL is ready */
0223     ret = wait_for_reg(base + PHY_28NM_PLL_REG0, PHY_28NM_PLL_READY, 100);
0224     if (ret) {
0225         dev_warn(&pdev->dev, "PLL_READY not set after 100mS.");
0226         goto err_clk;
0227     }
0228
0229     return 0;
0230 err_clk:
0231     clk_disable_unprepare(mv_phy->clk);
0232     return ret;
0233 }
0234
0235 static int mv_usb2_phy_28nm_power_on(struct phy *phy)
0236 {
0237     struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy);
0238     void __iomem *base = mv_phy->base;
0239
0240     writel(readl(base + PHY_28NM_CTRL_REG3) |
0241         (PHY_28NM_CTRL3_OVERWRITE | PHY_28NM_CTRL3_VBUS_VALID |
0242         PHY_28NM_CTRL3_AVALID | PHY_28NM_CTRL3_BVALID),
0243         base + PHY_28NM_CTRL_REG3);
0244
0245     return 0;
0246 }
0247
0248 static int mv_usb2_phy_28nm_power_off(struct phy *phy)
0249 {
0250     struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy);
0251     void __iomem *base = mv_phy->base;
0252
0253     writel(readl(base + PHY_28NM_CTRL_REG3) |
0254         ~(PHY_28NM_CTRL3_OVERWRITE | PHY_28NM_CTRL3_VBUS_VALID
0255         | PHY_28NM_CTRL3_AVALID | PHY_28NM_CTRL3_BVALID),
0256         base + PHY_28NM_CTRL_REG3);
0257
0258     return 0;
0259 }
0260
0261 static int mv_usb2_phy_28nm_exit(struct phy *phy)
0262 {
0263     struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy);
0264     void __iomem *base = mv_phy->base;
0265     unsigned int val;
0266
0267     val = readw(base + PHY_28NM_PLL_REG1);
0268     val &= ~PHY_28NM_PLL_PU_PLL;
0269     writew(val, base + PHY_28NM_PLL_REG1);
0270
0271     /* power down PHY Analog part */
0272     val = readw(base + PHY_28NM_TX_REG0);
0273     val &= ~PHY_28NM_TX_PU_ANA;
0274     writew(val, base + PHY_28NM_TX_REG0);
0275
0276     /* power down PHY OTG part */
0277     val = readw(base + PHY_28NM_OTG_REG);
0278     val &= ~PHY_28NM_OTG_PU_OTG;
0279     writew(val, base + PHY_28NM_OTG_REG);
0280
0281     clk_disable_unprepare(mv_phy->clk);
0282     return 0;
0283 }
0284
0285 static const struct phy_ops usb_ops = {
0286     .init       = mv_usb2_phy_28nm_init,
0287     .power_on   = mv_usb2_phy_28nm_power_on,
0288     .power_off  = mv_usb2_phy_28nm_power_off,
0289     .exit       = mv_usb2_phy_28nm_exit,
0290     .owner      = THIS_MODULE,
0291 };
0292
0293 static int mv_usb2_phy_probe(struct platform_device *pdev)
0294 {
0295     struct phy_provider *phy_provider;
0296     struct mv_usb2_phy *mv_phy;
0297
0298     mv_phy = devm_kzalloc(&pdev->dev, sizeof(*mv_phy), GFP_KERNEL);
0299     if (!mv_phy)
0300         return -ENOMEM;
0301
0302     mv_phy->pdev = pdev;
0303
0304     mv_phy->clk = devm_clk_get(&pdev->dev, NULL);
0305     if (IS_ERR(mv_phy->clk)) {
0306         dev_err(&pdev->dev, "failed to get clock.\n");
0307         return PTR_ERR(mv_phy->clk);
0308     }
0309
0310     mv_phy->base = devm_platform_ioremap_resource(pdev, 0);
0311     if (IS_ERR(mv_phy->base))
0312         return PTR_ERR(mv_phy->base);
0313
0314     mv_phy->phy = devm_phy_create(&pdev->dev, pdev->dev.of_node, &usb_ops);
0315     if (IS_ERR(mv_phy->phy))
0316         return PTR_ERR(mv_phy->phy);
0317
0318     phy_set_drvdata(mv_phy->phy, mv_phy);
0319
0320     phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
0321     return PTR_ERR_OR_ZERO(phy_provider);
0322 }
0323
0324 static const struct of_device_id mv_usbphy_dt_match[] = {
0325     { .compatible = "marvell,pxa1928-usb-phy", },
0326     {},
0327 };
0328 MODULE_DEVICE_TABLE(of, mv_usbphy_dt_match);
0329
0330 static struct platform_driver mv_usb2_phy_driver = {
0331     .probe  = mv_usb2_phy_probe,
0332     .driver = {
0333         .name   = "mv-usb2-phy",
0334         .of_match_table = of_match_ptr(mv_usbphy_dt_match),
0335     },
0336 };
0337 module_platform_driver(mv_usb2_phy_driver);
0338
0339 MODULE_AUTHOR("Rob Herring <robh@kernel.org>");
0340 MODULE_DESCRIPTION("Marvell USB2 phy driver");
0341 MODULE_LICENSE("GPL v2");