phy/marvell/phy-pxa-28nm-hsic.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2015 Linaro, Ltd.
0004  * Rob Herring <robh@kernel.org>
0005  *
0006  * Based on vendor driver:
0007  * Copyright (C) 2013 Marvell Inc.
0008  * Author: Chao Xie <xiechao.mail@gmail.com>
0009  */
0010
0011 #include <linux/delay.h>
0012 #include <linux/slab.h>
0013 #include <linux/of.h>
0014 #include <linux/io.h>
0015 #include <linux/iopoll.h>
0016 #include <linux/err.h>
0017 #include <linux/clk.h>
0018 #include <linux/module.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/phy/phy.h>
0021
0022 #define PHY_28NM_HSIC_CTRL          0x08
0023 #define PHY_28NM_HSIC_IMPCAL_CAL        0x18
0024 #define PHY_28NM_HSIC_PLL_CTRL01        0x1c
0025 #define PHY_28NM_HSIC_PLL_CTRL2         0x20
0026 #define PHY_28NM_HSIC_INT           0x28
0027
0028 #define PHY_28NM_HSIC_PLL_SELLPFR_SHIFT     26
0029 #define PHY_28NM_HSIC_PLL_FBDIV_SHIFT       0
0030 #define PHY_28NM_HSIC_PLL_REFDIV_SHIFT      9
0031
0032 #define PHY_28NM_HSIC_S2H_PU_PLL        BIT(10)
0033 #define PHY_28NM_HSIC_H2S_PLL_LOCK      BIT(15)
0034 #define PHY_28NM_HSIC_S2H_HSIC_EN       BIT(7)
0035 #define S2H_DRV_SE0_4RESUME         BIT(14)
0036 #define PHY_28NM_HSIC_H2S_IMPCAL_DONE       BIT(27)
0037
0038 #define PHY_28NM_HSIC_CONNECT_INT       BIT(1)
0039 #define PHY_28NM_HSIC_HS_READY_INT      BIT(2)
0040
0041 struct mv_hsic_phy {
0042     struct phy      *phy;
0043     struct platform_device  *pdev;
0044     void __iomem        *base;
0045     struct clk      *clk;
0046 };
0047
0048 static int wait_for_reg(void __iomem *reg, u32 mask, u32 ms)
0049 {
0050     u32 val;
0051
0052     return readl_poll_timeout(reg, val, ((val & mask) == mask),
0053                   1000, 1000 * ms);
0054 }
0055
0056 static int mv_hsic_phy_init(struct phy *phy)
0057 {
0058     struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy);
0059     struct platform_device *pdev = mv_phy->pdev;
0060     void __iomem *base = mv_phy->base;
0061     int ret;
0062
0063     clk_prepare_enable(mv_phy->clk);
0064
0065     /* Set reference clock */
0066     writel(0x1 << PHY_28NM_HSIC_PLL_SELLPFR_SHIFT |
0067         0xf0 << PHY_28NM_HSIC_PLL_FBDIV_SHIFT |
0068         0xd << PHY_28NM_HSIC_PLL_REFDIV_SHIFT,
0069         base + PHY_28NM_HSIC_PLL_CTRL01);
0070
0071     /* Turn on PLL */
0072     writel(readl(base + PHY_28NM_HSIC_PLL_CTRL2) |
0073         PHY_28NM_HSIC_S2H_PU_PLL,
0074         base + PHY_28NM_HSIC_PLL_CTRL2);
0075
0076     /* Make sure PHY PLL is locked */
0077     ret = wait_for_reg(base + PHY_28NM_HSIC_PLL_CTRL2,
0078                PHY_28NM_HSIC_H2S_PLL_LOCK, 100);
0079     if (ret) {
0080         dev_err(&pdev->dev, "HSIC PHY PLL not locked after 100mS.");
0081         clk_disable_unprepare(mv_phy->clk);
0082     }
0083
0084     return ret;
0085 }
0086
0087 static int mv_hsic_phy_power_on(struct phy *phy)
0088 {
0089     struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy);
0090     struct platform_device *pdev = mv_phy->pdev;
0091     void __iomem *base = mv_phy->base;
0092     u32 reg;
0093     int ret;
0094
0095     reg = readl(base + PHY_28NM_HSIC_CTRL);
0096     /* Avoid SE0 state when resume for some device will take it as reset */
0097     reg &= ~S2H_DRV_SE0_4RESUME;
0098     reg |= PHY_28NM_HSIC_S2H_HSIC_EN;   /* Enable HSIC PHY */
0099     writel(reg, base + PHY_28NM_HSIC_CTRL);
0100
0101     /*
0102      *  Calibration Timing
0103      *         ____________________________
0104      *  CAL START   ___|
0105      *             ____________________
0106      *  CAL_DONE    ___________|
0107      *         | 400us |
0108      */
0109
0110     /* Make sure PHY Calibration is ready */
0111     ret = wait_for_reg(base + PHY_28NM_HSIC_IMPCAL_CAL,
0112                PHY_28NM_HSIC_H2S_IMPCAL_DONE, 100);
0113     if (ret) {
0114         dev_warn(&pdev->dev, "HSIC PHY READY not set after 100mS.");
0115         return ret;
0116     }
0117
0118     /* Waiting for HSIC connect int*/
0119     ret = wait_for_reg(base + PHY_28NM_HSIC_INT,
0120                PHY_28NM_HSIC_CONNECT_INT, 200);
0121     if (ret)
0122         dev_warn(&pdev->dev, "HSIC wait for connect interrupt timeout.");
0123
0124     return ret;
0125 }
0126
0127 static int mv_hsic_phy_power_off(struct phy *phy)
0128 {
0129     struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy);
0130     void __iomem *base = mv_phy->base;
0131
0132     writel(readl(base + PHY_28NM_HSIC_CTRL) & ~PHY_28NM_HSIC_S2H_HSIC_EN,
0133         base + PHY_28NM_HSIC_CTRL);
0134
0135     return 0;
0136 }
0137
0138 static int mv_hsic_phy_exit(struct phy *phy)
0139 {
0140     struct mv_hsic_phy *mv_phy = phy_get_drvdata(phy);
0141     void __iomem *base = mv_phy->base;
0142
0143     /* Turn off PLL */
0144     writel(readl(base + PHY_28NM_HSIC_PLL_CTRL2) &
0145         ~PHY_28NM_HSIC_S2H_PU_PLL,
0146         base + PHY_28NM_HSIC_PLL_CTRL2);
0147
0148     clk_disable_unprepare(mv_phy->clk);
0149     return 0;
0150 }
0151
0152
0153 static const struct phy_ops hsic_ops = {
0154     .init       = mv_hsic_phy_init,
0155     .power_on   = mv_hsic_phy_power_on,
0156     .power_off  = mv_hsic_phy_power_off,
0157     .exit       = mv_hsic_phy_exit,
0158     .owner      = THIS_MODULE,
0159 };
0160
0161 static int mv_hsic_phy_probe(struct platform_device *pdev)
0162 {
0163     struct phy_provider *phy_provider;
0164     struct mv_hsic_phy *mv_phy;
0165
0166     mv_phy = devm_kzalloc(&pdev->dev, sizeof(*mv_phy), GFP_KERNEL);
0167     if (!mv_phy)
0168         return -ENOMEM;
0169
0170     mv_phy->pdev = pdev;
0171
0172     mv_phy->clk = devm_clk_get(&pdev->dev, NULL);
0173     if (IS_ERR(mv_phy->clk)) {
0174         dev_err(&pdev->dev, "failed to get clock.\n");
0175         return PTR_ERR(mv_phy->clk);
0176     }
0177
0178     mv_phy->base = devm_platform_ioremap_resource(pdev, 0);
0179     if (IS_ERR(mv_phy->base))
0180         return PTR_ERR(mv_phy->base);
0181
0182     mv_phy->phy = devm_phy_create(&pdev->dev, pdev->dev.of_node, &hsic_ops);
0183     if (IS_ERR(mv_phy->phy))
0184         return PTR_ERR(mv_phy->phy);
0185
0186     phy_set_drvdata(mv_phy->phy, mv_phy);
0187
0188     phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
0189     return PTR_ERR_OR_ZERO(phy_provider);
0190 }
0191
0192 static const struct of_device_id mv_hsic_phy_dt_match[] = {
0193     { .compatible = "marvell,pxa1928-hsic-phy", },
0194     {},
0195 };
0196 MODULE_DEVICE_TABLE(of, mv_hsic_phy_dt_match);
0197
0198 static struct platform_driver mv_hsic_phy_driver = {
0199     .probe  = mv_hsic_phy_probe,
0200     .driver = {
0201         .name   = "mv-hsic-phy",
0202         .of_match_table = of_match_ptr(mv_hsic_phy_dt_match),
0203     },
0204 };
0205 module_platform_driver(mv_hsic_phy_driver);
0206
0207 MODULE_AUTHOR("Rob Herring <robh@kernel.org>");
0208 MODULE_DESCRIPTION("Marvell HSIC phy driver");
0209 MODULE_LICENSE("GPL v2");