phy/marvell/phy-berlin-usb.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2014 Marvell Technology Group Ltd.
0004  *
0005  * Antoine Tenart <antoine.tenart@free-electrons.com>
0006  * Jisheng Zhang <jszhang@marvell.com>
0007  */
0008
0009 #include <linux/io.h>
0010 #include <linux/module.h>
0011 #include <linux/of_device.h>
0012 #include <linux/phy/phy.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/reset.h>
0015
0016 #define USB_PHY_PLL     0x04
0017 #define USB_PHY_PLL_CONTROL 0x08
0018 #define USB_PHY_TX_CTRL0    0x10
0019 #define USB_PHY_TX_CTRL1    0x14
0020 #define USB_PHY_TX_CTRL2    0x18
0021 #define USB_PHY_RX_CTRL     0x20
0022 #define USB_PHY_ANALOG      0x34
0023
0024 /* USB_PHY_PLL */
0025 #define CLK_REF_DIV(x)      ((x) << 4)
0026 #define FEEDBACK_CLK_DIV(x) ((x) << 8)
0027
0028 /* USB_PHY_PLL_CONTROL */
0029 #define CLK_STABLE      BIT(0)
0030 #define PLL_CTRL_PIN        BIT(1)
0031 #define PLL_CTRL_REG        BIT(2)
0032 #define PLL_ON          BIT(3)
0033 #define PHASE_OFF_TOL_125   (0x0 << 5)
0034 #define PHASE_OFF_TOL_250   BIT(5)
0035 #define KVC0_CALIB      (0x0 << 9)
0036 #define KVC0_REG_CTRL       BIT(9)
0037 #define KVC0_HIGH       (0x0 << 10)
0038 #define KVC0_LOW        (0x3 << 10)
0039 #define CLK_BLK_EN      BIT(13)
0040
0041 /* USB_PHY_TX_CTRL0 */
0042 #define EXT_HS_RCAL_EN      BIT(3)
0043 #define EXT_FS_RCAL_EN      BIT(4)
0044 #define IMPCAL_VTH_DIV(x)   ((x) << 5)
0045 #define EXT_RS_RCAL_DIV(x)  ((x) << 8)
0046 #define EXT_FS_RCAL_DIV(x)  ((x) << 12)
0047
0048 /* USB_PHY_TX_CTRL1 */
0049 #define TX_VDD15_14     (0x0 << 4)
0050 #define TX_VDD15_15     BIT(4)
0051 #define TX_VDD15_16     (0x2 << 4)
0052 #define TX_VDD15_17     (0x3 << 4)
0053 #define TX_VDD12_VDD        (0x0 << 6)
0054 #define TX_VDD12_11     BIT(6)
0055 #define TX_VDD12_12     (0x2 << 6)
0056 #define TX_VDD12_13     (0x3 << 6)
0057 #define LOW_VDD_EN      BIT(8)
0058 #define TX_OUT_AMP(x)       ((x) << 9)
0059
0060 /* USB_PHY_TX_CTRL2 */
0061 #define TX_CHAN_CTRL_REG(x) ((x) << 0)
0062 #define DRV_SLEWRATE(x)     ((x) << 4)
0063 #define IMP_CAL_FS_HS_DLY_0 (0x0 << 6)
0064 #define IMP_CAL_FS_HS_DLY_1 BIT(6)
0065 #define IMP_CAL_FS_HS_DLY_2 (0x2 << 6)
0066 #define IMP_CAL_FS_HS_DLY_3 (0x3 << 6)
0067 #define FS_DRV_EN_MASK(x)   ((x) << 8)
0068 #define HS_DRV_EN_MASK(x)   ((x) << 12)
0069
0070 /* USB_PHY_RX_CTRL */
0071 #define PHASE_FREEZE_DLY_2_CL   (0x0 << 0)
0072 #define PHASE_FREEZE_DLY_4_CL   BIT(0)
0073 #define ACK_LENGTH_8_CL     (0x0 << 2)
0074 #define ACK_LENGTH_12_CL    BIT(2)
0075 #define ACK_LENGTH_16_CL    (0x2 << 2)
0076 #define ACK_LENGTH_20_CL    (0x3 << 2)
0077 #define SQ_LENGTH_3     (0x0 << 4)
0078 #define SQ_LENGTH_6     BIT(4)
0079 #define SQ_LENGTH_9     (0x2 << 4)
0080 #define SQ_LENGTH_12        (0x3 << 4)
0081 #define DISCON_THRESHOLD_260    (0x0 << 6)
0082 #define DISCON_THRESHOLD_270    BIT(6)
0083 #define DISCON_THRESHOLD_280    (0x2 << 6)
0084 #define DISCON_THRESHOLD_290    (0x3 << 6)
0085 #define SQ_THRESHOLD(x)     ((x) << 8)
0086 #define LPF_COEF(x)     ((x) << 12)
0087 #define INTPL_CUR_10        (0x0 << 14)
0088 #define INTPL_CUR_20        BIT(14)
0089 #define INTPL_CUR_30        (0x2 << 14)
0090 #define INTPL_CUR_40        (0x3 << 14)
0091
0092 /* USB_PHY_ANALOG */
0093 #define ANA_PWR_UP      BIT(1)
0094 #define ANA_PWR_DOWN        BIT(2)
0095 #define V2I_VCO_RATIO(x)    ((x) << 7)
0096 #define R_ROTATE_90     (0x0 << 10)
0097 #define R_ROTATE_0      BIT(10)
0098 #define MODE_TEST_EN        BIT(11)
0099 #define ANA_TEST_DC_CTRL(x) ((x) << 12)
0100
0101 static const u32 phy_berlin_pll_dividers[] = {
0102     /* Berlin 2 */
0103     CLK_REF_DIV(0x6) | FEEDBACK_CLK_DIV(0x55),
0104     /* Berlin 2CD/Q */
0105     CLK_REF_DIV(0xc) | FEEDBACK_CLK_DIV(0x54),
0106 };
0107
0108 struct phy_berlin_usb_priv {
0109     void __iomem        *base;
0110     struct reset_control    *rst_ctrl;
0111     u32         pll_divider;
0112 };
0113
0114 static int phy_berlin_usb_power_on(struct phy *phy)
0115 {
0116     struct phy_berlin_usb_priv *priv = phy_get_drvdata(phy);
0117
0118     reset_control_reset(priv->rst_ctrl);
0119
0120     writel(priv->pll_divider,
0121            priv->base + USB_PHY_PLL);
0122     writel(CLK_STABLE | PLL_CTRL_REG | PHASE_OFF_TOL_250 | KVC0_REG_CTRL |
0123            CLK_BLK_EN, priv->base + USB_PHY_PLL_CONTROL);
0124     writel(V2I_VCO_RATIO(0x5) | R_ROTATE_0 | ANA_TEST_DC_CTRL(0x5),
0125            priv->base + USB_PHY_ANALOG);
0126     writel(PHASE_FREEZE_DLY_4_CL | ACK_LENGTH_16_CL | SQ_LENGTH_12 |
0127            DISCON_THRESHOLD_270 | SQ_THRESHOLD(0xa) | LPF_COEF(0x2) |
0128            INTPL_CUR_30, priv->base + USB_PHY_RX_CTRL);
0129
0130     writel(TX_VDD12_13 | TX_OUT_AMP(0x3), priv->base + USB_PHY_TX_CTRL1);
0131     writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4),
0132            priv->base + USB_PHY_TX_CTRL0);
0133
0134     writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4) |
0135            EXT_FS_RCAL_DIV(0x2), priv->base + USB_PHY_TX_CTRL0);
0136
0137     writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4),
0138            priv->base + USB_PHY_TX_CTRL0);
0139     writel(TX_CHAN_CTRL_REG(0xf) | DRV_SLEWRATE(0x3) | IMP_CAL_FS_HS_DLY_3 |
0140            FS_DRV_EN_MASK(0xd), priv->base + USB_PHY_TX_CTRL2);
0141
0142     return 0;
0143 }
0144
0145 static const struct phy_ops phy_berlin_usb_ops = {
0146     .power_on   = phy_berlin_usb_power_on,
0147     .owner      = THIS_MODULE,
0148 };
0149
0150 static const struct of_device_id phy_berlin_usb_of_match[] = {
0151     {
0152         .compatible = "marvell,berlin2-usb-phy",
0153         .data = &phy_berlin_pll_dividers[0],
0154     },
0155     {
0156         .compatible = "marvell,berlin2cd-usb-phy",
0157         .data = &phy_berlin_pll_dividers[1],
0158     },
0159     { },
0160 };
0161 MODULE_DEVICE_TABLE(of, phy_berlin_usb_of_match);
0162
0163 static int phy_berlin_usb_probe(struct platform_device *pdev)
0164 {
0165     const struct of_device_id *match =
0166         of_match_device(phy_berlin_usb_of_match, &pdev->dev);
0167     struct phy_berlin_usb_priv *priv;
0168     struct phy *phy;
0169     struct phy_provider *phy_provider;
0170
0171     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
0172     if (!priv)
0173         return -ENOMEM;
0174
0175     priv->base = devm_platform_ioremap_resource(pdev, 0);
0176     if (IS_ERR(priv->base))
0177         return PTR_ERR(priv->base);
0178
0179     priv->rst_ctrl = devm_reset_control_get(&pdev->dev, NULL);
0180     if (IS_ERR(priv->rst_ctrl))
0181         return PTR_ERR(priv->rst_ctrl);
0182
0183     priv->pll_divider = *((u32 *)match->data);
0184
0185     phy = devm_phy_create(&pdev->dev, NULL, &phy_berlin_usb_ops);
0186     if (IS_ERR(phy)) {
0187         dev_err(&pdev->dev, "failed to create PHY\n");
0188         return PTR_ERR(phy);
0189     }
0190
0191     phy_set_drvdata(phy, priv);
0192
0193     phy_provider =
0194         devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
0195     return PTR_ERR_OR_ZERO(phy_provider);
0196 }
0197
0198 static struct platform_driver phy_berlin_usb_driver = {
0199     .probe  = phy_berlin_usb_probe,
0200     .driver = {
0201         .name       = "phy-berlin-usb",
0202         .of_match_table = phy_berlin_usb_of_match,
0203     },
0204 };
0205 module_platform_driver(phy_berlin_usb_driver);
0206
0207 MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");
0208 MODULE_DESCRIPTION("Marvell Berlin PHY driver for USB");
0209 MODULE_LICENSE("GPL");