phy/marvell/phy-berlin-sata.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Marvell Berlin SATA PHY driver
0004  *
0005  * Copyright (C) 2014 Marvell Technology Group Ltd.
0006  *
0007  * Antoine Ténart <antoine.tenart@free-electrons.com>
0008  */
0009
0010 #include <linux/clk.h>
0011 #include <linux/module.h>
0012 #include <linux/phy/phy.h>
0013 #include <linux/io.h>
0014 #include <linux/platform_device.h>
0015
0016 #define HOST_VSA_ADDR       0x0
0017 #define HOST_VSA_DATA       0x4
0018 #define PORT_SCR_CTL        0x2c
0019 #define PORT_VSR_ADDR       0x78
0020 #define PORT_VSR_DATA       0x7c
0021
0022 #define CONTROL_REGISTER    0x0
0023 #define MBUS_SIZE_CONTROL   0x4
0024
0025 #define POWER_DOWN_PHY0         BIT(6)
0026 #define POWER_DOWN_PHY1         BIT(14)
0027 #define MBUS_WRITE_REQUEST_SIZE_128 (BIT(2) << 16)
0028 #define MBUS_READ_REQUEST_SIZE_128  (BIT(2) << 19)
0029
0030 #define BG2_PHY_BASE        0x080
0031 #define BG2Q_PHY_BASE       0x200
0032
0033 /* register 0x01 */
0034 #define REF_FREF_SEL_25     BIT(0)
0035 #define PHY_BERLIN_MODE_SATA    (0x0 << 5)
0036
0037 /* register 0x02 */
0038 #define USE_MAX_PLL_RATE    BIT(12)
0039
0040 /* register 0x23 */
0041 #define DATA_BIT_WIDTH_10   (0x0 << 10)
0042 #define DATA_BIT_WIDTH_20   (0x1 << 10)
0043 #define DATA_BIT_WIDTH_40   (0x2 << 10)
0044
0045 /* register 0x25 */
0046 #define PHY_GEN_MAX_1_5     (0x0 << 10)
0047 #define PHY_GEN_MAX_3_0     (0x1 << 10)
0048 #define PHY_GEN_MAX_6_0     (0x2 << 10)
0049
0050 struct phy_berlin_desc {
0051     struct phy  *phy;
0052     u32     power_bit;
0053     unsigned    index;
0054 };
0055
0056 struct phy_berlin_priv {
0057     void __iomem        *base;
0058     spinlock_t      lock;
0059     struct clk      *clk;
0060     struct phy_berlin_desc  **phys;
0061     unsigned        nphys;
0062     u32         phy_base;
0063 };
0064
0065 static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg,
0066                    u32 phy_base, u32 reg, u32 mask, u32 val)
0067 {
0068     u32 regval;
0069
0070     /* select register */
0071     writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR);
0072
0073     /* set bits */
0074     regval = readl(ctrl_reg + PORT_VSR_DATA);
0075     regval &= ~mask;
0076     regval |= val;
0077     writel(regval, ctrl_reg + PORT_VSR_DATA);
0078 }
0079
0080 static int phy_berlin_sata_power_on(struct phy *phy)
0081 {
0082     struct phy_berlin_desc *desc = phy_get_drvdata(phy);
0083     struct phy_berlin_priv *priv = dev_get_drvdata(phy->dev.parent);
0084     void __iomem *ctrl_reg = priv->base + 0x60 + (desc->index * 0x80);
0085     u32 regval;
0086
0087     clk_prepare_enable(priv->clk);
0088
0089     spin_lock(&priv->lock);
0090
0091     /* Power on PHY */
0092     writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR);
0093     regval = readl(priv->base + HOST_VSA_DATA);
0094     regval &= ~desc->power_bit;
0095     writel(regval, priv->base + HOST_VSA_DATA);
0096
0097     /* Configure MBus */
0098     writel(MBUS_SIZE_CONTROL, priv->base + HOST_VSA_ADDR);
0099     regval = readl(priv->base + HOST_VSA_DATA);
0100     regval |= MBUS_WRITE_REQUEST_SIZE_128 | MBUS_READ_REQUEST_SIZE_128;
0101     writel(regval, priv->base + HOST_VSA_DATA);
0102
0103     /* set PHY mode and ref freq to 25 MHz */
0104     phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01,
0105                     0x00ff,
0106                     REF_FREF_SEL_25 | PHY_BERLIN_MODE_SATA);
0107
0108     /* set PHY up to 6 Gbps */
0109     phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25,
0110                     0x0c00, PHY_GEN_MAX_6_0);
0111
0112     /* set 40 bits width */
0113     phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23,
0114                     0x0c00, DATA_BIT_WIDTH_40);
0115
0116     /* use max pll rate */
0117     phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02,
0118                     0x0000, USE_MAX_PLL_RATE);
0119
0120     /* set Gen3 controller speed */
0121     regval = readl(ctrl_reg + PORT_SCR_CTL);
0122     regval &= ~GENMASK(7, 4);
0123     regval |= 0x30;
0124     writel(regval, ctrl_reg + PORT_SCR_CTL);
0125
0126     spin_unlock(&priv->lock);
0127
0128     clk_disable_unprepare(priv->clk);
0129
0130     return 0;
0131 }
0132
0133 static int phy_berlin_sata_power_off(struct phy *phy)
0134 {
0135     struct phy_berlin_desc *desc = phy_get_drvdata(phy);
0136     struct phy_berlin_priv *priv = dev_get_drvdata(phy->dev.parent);
0137     u32 regval;
0138
0139     clk_prepare_enable(priv->clk);
0140
0141     spin_lock(&priv->lock);
0142
0143     /* Power down PHY */
0144     writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR);
0145     regval = readl(priv->base + HOST_VSA_DATA);
0146     regval |= desc->power_bit;
0147     writel(regval, priv->base + HOST_VSA_DATA);
0148
0149     spin_unlock(&priv->lock);
0150
0151     clk_disable_unprepare(priv->clk);
0152
0153     return 0;
0154 }
0155
0156 static struct phy *phy_berlin_sata_phy_xlate(struct device *dev,
0157                          struct of_phandle_args *args)
0158 {
0159     struct phy_berlin_priv *priv = dev_get_drvdata(dev);
0160     int i;
0161
0162     if (WARN_ON(args->args[0] >= priv->nphys))
0163         return ERR_PTR(-ENODEV);
0164
0165     for (i = 0; i < priv->nphys; i++) {
0166         if (priv->phys[i]->index == args->args[0])
0167             break;
0168     }
0169
0170     if (i == priv->nphys)
0171         return ERR_PTR(-ENODEV);
0172
0173     return priv->phys[i]->phy;
0174 }
0175
0176 static const struct phy_ops phy_berlin_sata_ops = {
0177     .power_on   = phy_berlin_sata_power_on,
0178     .power_off  = phy_berlin_sata_power_off,
0179     .owner      = THIS_MODULE,
0180 };
0181
0182 static u32 phy_berlin_power_down_bits[] = {
0183     POWER_DOWN_PHY0,
0184     POWER_DOWN_PHY1,
0185 };
0186
0187 static int phy_berlin_sata_probe(struct platform_device *pdev)
0188 {
0189     struct device *dev = &pdev->dev;
0190     struct device_node *child;
0191     struct phy *phy;
0192     struct phy_provider *phy_provider;
0193     struct phy_berlin_priv *priv;
0194     struct resource *res;
0195     int ret, i = 0;
0196     u32 phy_id;
0197
0198     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0199     if (!priv)
0200         return -ENOMEM;
0201
0202     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0203     if (!res)
0204         return -EINVAL;
0205
0206     priv->base = devm_ioremap(dev, res->start, resource_size(res));
0207     if (!priv->base)
0208         return -ENOMEM;
0209
0210     priv->clk = devm_clk_get(dev, NULL);
0211     if (IS_ERR(priv->clk))
0212         return PTR_ERR(priv->clk);
0213
0214     priv->nphys = of_get_child_count(dev->of_node);
0215     if (priv->nphys == 0)
0216         return -ENODEV;
0217
0218     priv->phys = devm_kcalloc(dev, priv->nphys, sizeof(*priv->phys),
0219                   GFP_KERNEL);
0220     if (!priv->phys)
0221         return -ENOMEM;
0222
0223     if (of_device_is_compatible(dev->of_node, "marvell,berlin2-sata-phy"))
0224         priv->phy_base = BG2_PHY_BASE;
0225     else
0226         priv->phy_base = BG2Q_PHY_BASE;
0227
0228     dev_set_drvdata(dev, priv);
0229     spin_lock_init(&priv->lock);
0230
0231     for_each_available_child_of_node(dev->of_node, child) {
0232         struct phy_berlin_desc *phy_desc;
0233
0234         if (of_property_read_u32(child, "reg", &phy_id)) {
0235             dev_err(dev, "missing reg property in node %pOFn\n",
0236                 child);
0237             ret = -EINVAL;
0238             goto put_child;
0239         }
0240
0241         if (phy_id >= ARRAY_SIZE(phy_berlin_power_down_bits)) {
0242             dev_err(dev, "invalid reg in node %pOFn\n", child);
0243             ret = -EINVAL;
0244             goto put_child;
0245         }
0246
0247         phy_desc = devm_kzalloc(dev, sizeof(*phy_desc), GFP_KERNEL);
0248         if (!phy_desc) {
0249             ret = -ENOMEM;
0250             goto put_child;
0251         }
0252
0253         phy = devm_phy_create(dev, NULL, &phy_berlin_sata_ops);
0254         if (IS_ERR(phy)) {
0255             dev_err(dev, "failed to create PHY %d\n", phy_id);
0256             ret = PTR_ERR(phy);
0257             goto put_child;
0258         }
0259
0260         phy_desc->phy = phy;
0261         phy_desc->power_bit = phy_berlin_power_down_bits[phy_id];
0262         phy_desc->index = phy_id;
0263         phy_set_drvdata(phy, phy_desc);
0264
0265         priv->phys[i++] = phy_desc;
0266
0267         /* Make sure the PHY is off */
0268         phy_berlin_sata_power_off(phy);
0269     }
0270
0271     phy_provider =
0272         devm_of_phy_provider_register(dev, phy_berlin_sata_phy_xlate);
0273     return PTR_ERR_OR_ZERO(phy_provider);
0274 put_child:
0275     of_node_put(child);
0276     return ret;
0277 }
0278
0279 static const struct of_device_id phy_berlin_sata_of_match[] = {
0280     { .compatible = "marvell,berlin2-sata-phy" },
0281     { .compatible = "marvell,berlin2q-sata-phy" },
0282     { },
0283 };
0284 MODULE_DEVICE_TABLE(of, phy_berlin_sata_of_match);
0285
0286 static struct platform_driver phy_berlin_sata_driver = {
0287     .probe  = phy_berlin_sata_probe,
0288     .driver = {
0289         .name       = "phy-berlin-sata",
0290         .of_match_table = phy_berlin_sata_of_match,
0291     },
0292 };
0293 module_platform_driver(phy_berlin_sata_driver);
0294
0295 MODULE_DESCRIPTION("Marvell Berlin SATA PHY driver");
0296 MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>");
0297 MODULE_LICENSE("GPL v2");