phy/marvell/phy-armada38x-comphy.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2018 Russell King, Deep Blue Solutions Ltd.
0004  *
0005  * Partly derived from CP110 comphy driver by Antoine Tenart
0006  * <antoine.tenart@bootlin.com>
0007  */
0008 #include <linux/delay.h>
0009 #include <linux/iopoll.h>
0010 #include <linux/module.h>
0011 #include <linux/phy/phy.h>
0012 #include <linux/phy.h>
0013 #include <linux/platform_device.h>
0014
0015 #define MAX_A38X_COMPHY 6
0016 #define MAX_A38X_PORTS  3
0017
0018 #define COMPHY_CFG1     0x00
0019 #define  COMPHY_CFG1_GEN_TX(x)      ((x) << 26)
0020 #define  COMPHY_CFG1_GEN_TX_MSK     COMPHY_CFG1_GEN_TX(15)
0021 #define  COMPHY_CFG1_GEN_RX(x)      ((x) << 22)
0022 #define  COMPHY_CFG1_GEN_RX_MSK     COMPHY_CFG1_GEN_RX(15)
0023 #define  GEN_SGMII_1_25GBPS     6
0024 #define  GEN_SGMII_3_125GBPS        8
0025
0026 #define COMPHY_STAT1        0x18
0027 #define  COMPHY_STAT1_PLL_RDY_TX    BIT(3)
0028 #define  COMPHY_STAT1_PLL_RDY_RX    BIT(2)
0029
0030 #define COMPHY_SELECTOR     0xfc
0031
0032 struct a38x_comphy;
0033
0034 struct a38x_comphy_lane {
0035     void __iomem *base;
0036     struct a38x_comphy *priv;
0037     unsigned int n;
0038
0039     int port;
0040 };
0041
0042 struct a38x_comphy {
0043     void __iomem *base;
0044     void __iomem *conf;
0045     struct device *dev;
0046     struct a38x_comphy_lane lane[MAX_A38X_COMPHY];
0047 };
0048
0049 static const u8 gbe_mux[MAX_A38X_COMPHY][MAX_A38X_PORTS] = {
0050     { 0, 0, 0 },
0051     { 4, 5, 0 },
0052     { 0, 4, 0 },
0053     { 0, 0, 4 },
0054     { 0, 3, 0 },
0055     { 0, 0, 3 },
0056 };
0057
0058 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable)
0059 {
0060     struct a38x_comphy *priv = lane->priv;
0061     u32 conf;
0062
0063     if (priv->conf) {
0064         conf = readl_relaxed(priv->conf);
0065         if (enable)
0066             conf |= BIT(lane->port);
0067         else
0068             conf &= ~BIT(lane->port);
0069         writel(conf, priv->conf);
0070     }
0071 }
0072
0073 static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane,
0074                 unsigned int offset, u32 mask, u32 value)
0075 {
0076     u32 val;
0077
0078     val = readl_relaxed(lane->base + offset) & ~mask;
0079     writel(val | value, lane->base + offset);
0080 }
0081
0082 static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane,
0083                   unsigned int gen_tx, unsigned int gen_rx)
0084 {
0085     a38x_comphy_set_reg(lane, COMPHY_CFG1,
0086                 COMPHY_CFG1_GEN_TX_MSK | COMPHY_CFG1_GEN_RX_MSK,
0087                 COMPHY_CFG1_GEN_TX(gen_tx) |
0088                     COMPHY_CFG1_GEN_RX(gen_rx));
0089 }
0090
0091 static int a38x_comphy_poll(struct a38x_comphy_lane *lane,
0092                 unsigned int offset, u32 mask, u32 value)
0093 {
0094     u32 val;
0095     int ret;
0096
0097     ret = readl_relaxed_poll_timeout_atomic(lane->base + offset, val,
0098                         (val & mask) == value,
0099                         1000, 150000);
0100
0101     if (ret)
0102         dev_err(lane->priv->dev,
0103             "comphy%u: timed out waiting for status\n", lane->n);
0104
0105     return ret;
0106 }
0107
0108 /*
0109  * We only support changing the speed for comphys configured for GBE.
0110  * Since that is all we do, we only poll for PLL ready status.
0111  */
0112 static int a38x_comphy_set_mode(struct phy *phy, enum phy_mode mode, int sub)
0113 {
0114     struct a38x_comphy_lane *lane = phy_get_drvdata(phy);
0115     unsigned int gen;
0116     int ret;
0117
0118     if (mode != PHY_MODE_ETHERNET)
0119         return -EINVAL;
0120
0121     switch (sub) {
0122     case PHY_INTERFACE_MODE_SGMII:
0123     case PHY_INTERFACE_MODE_1000BASEX:
0124         gen = GEN_SGMII_1_25GBPS;
0125         break;
0126
0127     case PHY_INTERFACE_MODE_2500BASEX:
0128         gen = GEN_SGMII_3_125GBPS;
0129         break;
0130
0131     default:
0132         return -EINVAL;
0133     }
0134
0135     a38x_set_conf(lane, false);
0136
0137     a38x_comphy_set_speed(lane, gen, gen);
0138
0139     ret = a38x_comphy_poll(lane, COMPHY_STAT1,
0140                    COMPHY_STAT1_PLL_RDY_TX |
0141                    COMPHY_STAT1_PLL_RDY_RX,
0142                    COMPHY_STAT1_PLL_RDY_TX |
0143                    COMPHY_STAT1_PLL_RDY_RX);
0144
0145     if (ret == 0)
0146         a38x_set_conf(lane, true);
0147
0148     return ret;
0149 }
0150
0151 static const struct phy_ops a38x_comphy_ops = {
0152     .set_mode   = a38x_comphy_set_mode,
0153     .owner      = THIS_MODULE,
0154 };
0155
0156 static struct phy *a38x_comphy_xlate(struct device *dev,
0157                      struct of_phandle_args *args)
0158 {
0159     struct a38x_comphy_lane *lane;
0160     struct phy *phy;
0161     u32 val;
0162
0163     if (WARN_ON(args->args[0] >= MAX_A38X_PORTS))
0164         return ERR_PTR(-EINVAL);
0165
0166     phy = of_phy_simple_xlate(dev, args);
0167     if (IS_ERR(phy))
0168         return phy;
0169
0170     lane = phy_get_drvdata(phy);
0171     if (lane->port >= 0)
0172         return ERR_PTR(-EBUSY);
0173
0174     lane->port = args->args[0];
0175
0176     val = readl_relaxed(lane->priv->base + COMPHY_SELECTOR);
0177     val = (val >> (4 * lane->n)) & 0xf;
0178
0179     if (!gbe_mux[lane->n][lane->port] ||
0180         val != gbe_mux[lane->n][lane->port]) {
0181         dev_warn(lane->priv->dev,
0182              "comphy%u: not configured for GBE\n", lane->n);
0183         phy = ERR_PTR(-EINVAL);
0184     }
0185
0186     return phy;
0187 }
0188
0189 static int a38x_comphy_probe(struct platform_device *pdev)
0190 {
0191     struct phy_provider *provider;
0192     struct device_node *child;
0193     struct a38x_comphy *priv;
0194     struct resource *res;
0195     void __iomem *base;
0196
0197     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
0198     if (!priv)
0199         return -ENOMEM;
0200
0201     base = devm_platform_ioremap_resource(pdev, 0);
0202     if (IS_ERR(base))
0203         return PTR_ERR(base);
0204
0205     priv->dev = &pdev->dev;
0206     priv->base = base;
0207
0208     /* Optional */
0209     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "conf");
0210     if (res) {
0211         priv->conf = devm_ioremap_resource(&pdev->dev, res);
0212         if (IS_ERR(priv->conf))
0213             return PTR_ERR(priv->conf);
0214     }
0215
0216     for_each_available_child_of_node(pdev->dev.of_node, child) {
0217         struct phy *phy;
0218         int ret;
0219         u32 val;
0220
0221         ret = of_property_read_u32(child, "reg", &val);
0222         if (ret < 0) {
0223             dev_err(&pdev->dev, "missing 'reg' property (%d)\n",
0224                 ret);
0225             continue;
0226         }
0227
0228         if (val >= MAX_A38X_COMPHY || priv->lane[val].base) {
0229             dev_err(&pdev->dev, "invalid 'reg' property\n");
0230             continue;
0231         }
0232
0233         phy = devm_phy_create(&pdev->dev, child, &a38x_comphy_ops);
0234         if (IS_ERR(phy)) {
0235             of_node_put(child);
0236             return PTR_ERR(phy);
0237         }
0238
0239         priv->lane[val].base = base + 0x28 * val;
0240         priv->lane[val].priv = priv;
0241         priv->lane[val].n = val;
0242         priv->lane[val].port = -1;
0243         phy_set_drvdata(phy, &priv->lane[val]);
0244     }
0245
0246     dev_set_drvdata(&pdev->dev, priv);
0247
0248     provider = devm_of_phy_provider_register(&pdev->dev, a38x_comphy_xlate);
0249
0250     return PTR_ERR_OR_ZERO(provider);
0251 }
0252
0253 static const struct of_device_id a38x_comphy_of_match_table[] = {
0254     { .compatible = "marvell,armada-380-comphy" },
0255     { },
0256 };
0257 MODULE_DEVICE_TABLE(of, a38x_comphy_of_match_table);
0258
0259 static struct platform_driver a38x_comphy_driver = {
0260     .probe  = a38x_comphy_probe,
0261     .driver = {
0262         .name = "armada-38x-comphy",
0263         .of_match_table = a38x_comphy_of_match_table,
0264     },
0265 };
0266 module_platform_driver(a38x_comphy_driver);
0267
0268 MODULE_AUTHOR("Russell King <rmk+kernel@armlinux.org.uk>");
0269 MODULE_DESCRIPTION("Common PHY driver for Armada 38x SoCs");
0270 MODULE_LICENSE("GPL v2");