phy/lantiq/phy-lantiq-vrx200-pcie.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * PCIe PHY driver for Lantiq VRX200 and ARX300 SoCs.
0004  *
0005  * Copyright (C) 2019 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
0006  *
0007  * Based on the BSP (called "UGW") driver:
0008  *  Copyright (C) 2009-2015 Lei Chuanhua <chuanhua.lei@lantiq.com>
0009  *  Copyright (C) 2016 Intel Corporation
0010  *
0011  * TODO: PHY modes other than 36MHz (without "SSC")
0012  */
0013
0014 #include <linux/bitfield.h>
0015 #include <linux/bits.h>
0016 #include <linux/clk.h>
0017 #include <linux/delay.h>
0018 #include <linux/mfd/syscon.h>
0019 #include <linux/module.h>
0020 #include <linux/of.h>
0021 #include <linux/phy/phy.h>
0022 #include <linux/platform_device.h>
0023 #include <linux/property.h>
0024 #include <linux/regmap.h>
0025 #include <linux/reset.h>
0026
0027 #include <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
0028
0029 #define PCIE_PHY_PLL_CTRL1              0x44
0030
0031 #define PCIE_PHY_PLL_CTRL2              0x46
0032 #define PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK       GENMASK(7, 0)
0033 #define PCIE_PHY_PLL_CTRL2_CONST_SDM_EN         BIT(8)
0034 #define PCIE_PHY_PLL_CTRL2_PLL_SDM_EN           BIT(9)
0035
0036 #define PCIE_PHY_PLL_CTRL3              0x48
0037 #define PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN     BIT(1)
0038 #define PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK   GENMASK(6, 4)
0039
0040 #define PCIE_PHY_PLL_CTRL4              0x4a
0041 #define PCIE_PHY_PLL_CTRL5              0x4c
0042 #define PCIE_PHY_PLL_CTRL6              0x4e
0043 #define PCIE_PHY_PLL_CTRL7              0x50
0044 #define PCIE_PHY_PLL_A_CTRL1                0x52
0045
0046 #define PCIE_PHY_PLL_A_CTRL2                0x54
0047 #define PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN         BIT(14)
0048
0049 #define PCIE_PHY_PLL_A_CTRL3                0x56
0050 #define PCIE_PHY_PLL_A_CTRL3_MMD_MASK           GENMASK(15, 13)
0051
0052 #define PCIE_PHY_PLL_STATUS             0x58
0053
0054 #define PCIE_PHY_TX1_CTRL1              0x60
0055 #define PCIE_PHY_TX1_CTRL1_FORCE_EN         BIT(3)
0056 #define PCIE_PHY_TX1_CTRL1_LOAD_EN          BIT(4)
0057
0058 #define PCIE_PHY_TX1_CTRL2              0x62
0059 #define PCIE_PHY_TX1_CTRL3              0x64
0060 #define PCIE_PHY_TX1_A_CTRL1                0x66
0061 #define PCIE_PHY_TX1_A_CTRL2                0x68
0062 #define PCIE_PHY_TX1_MOD1               0x6a
0063 #define PCIE_PHY_TX1_MOD2               0x6c
0064 #define PCIE_PHY_TX1_MOD3               0x6e
0065
0066 #define PCIE_PHY_TX2_CTRL1              0x70
0067 #define PCIE_PHY_TX2_CTRL1_LOAD_EN          BIT(4)
0068
0069 #define PCIE_PHY_TX2_CTRL2              0x72
0070 #define PCIE_PHY_TX2_A_CTRL1                0x76
0071 #define PCIE_PHY_TX2_A_CTRL2                0x78
0072 #define PCIE_PHY_TX2_MOD1               0x7a
0073 #define PCIE_PHY_TX2_MOD2               0x7c
0074 #define PCIE_PHY_TX2_MOD3               0x7e
0075
0076 #define PCIE_PHY_RX1_CTRL1              0xa0
0077 #define PCIE_PHY_RX1_CTRL1_LOAD_EN          BIT(1)
0078
0079 #define PCIE_PHY_RX1_CTRL2              0xa2
0080 #define PCIE_PHY_RX1_CDR                0xa4
0081 #define PCIE_PHY_RX1_EI                 0xa6
0082 #define PCIE_PHY_RX1_A_CTRL             0xaa
0083
0084 struct ltq_vrx200_pcie_phy_priv {
0085     struct phy          *phy;
0086     unsigned int            mode;
0087     struct device           *dev;
0088     struct regmap           *phy_regmap;
0089     struct regmap           *rcu_regmap;
0090     struct clk          *pdi_clk;
0091     struct clk          *phy_clk;
0092     struct reset_control        *phy_reset;
0093     struct reset_control        *pcie_reset;
0094     u32             rcu_ahb_endian_offset;
0095     u32             rcu_ahb_endian_big_endian_mask;
0096 };
0097
0098 static void ltq_vrx200_pcie_phy_common_setup(struct phy *phy)
0099 {
0100     struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
0101
0102     /* PLL Setting */
0103     regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL1, 0x120e);
0104
0105     /* increase the bias reference voltage */
0106     regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2, 0x39d7);
0107     regmap_write(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3, 0x0900);
0108
0109     /* Endcnt */
0110     regmap_write(priv->phy_regmap, PCIE_PHY_RX1_EI, 0x0004);
0111     regmap_write(priv->phy_regmap, PCIE_PHY_RX1_A_CTRL, 0x6803);
0112
0113     regmap_update_bits(priv->phy_regmap, PCIE_PHY_TX1_CTRL1,
0114                PCIE_PHY_TX1_CTRL1_FORCE_EN,
0115                PCIE_PHY_TX1_CTRL1_FORCE_EN);
0116
0117     /* predrv_ser_en */
0118     regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL2, 0x0706);
0119
0120     /* ctrl_lim */
0121     regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL3, 0x1fff);
0122
0123     /* ctrl */
0124     regmap_write(priv->phy_regmap, PCIE_PHY_TX1_A_CTRL1, 0x0810);
0125
0126     /* predrv_ser_en */
0127     regmap_update_bits(priv->phy_regmap, PCIE_PHY_TX2_A_CTRL2, 0x7f00,
0128                0x4700);
0129
0130     /* RTERM */
0131     regmap_write(priv->phy_regmap, PCIE_PHY_TX1_CTRL2, 0x2e00);
0132
0133     /* Improved 100MHz clock output  */
0134     regmap_write(priv->phy_regmap, PCIE_PHY_TX2_CTRL2, 0x3096);
0135     regmap_write(priv->phy_regmap, PCIE_PHY_TX2_A_CTRL2, 0x4707);
0136
0137     /* Reduced CDR BW to avoid glitches */
0138     regmap_write(priv->phy_regmap, PCIE_PHY_RX1_CDR, 0x0235);
0139 }
0140
0141 static void pcie_phy_36mhz_mode_setup(struct phy *phy)
0142 {
0143     struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
0144
0145     regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL3,
0146                PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_EN, 0x0000);
0147
0148     regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL3,
0149                PCIE_PHY_PLL_CTRL3_EXT_MMD_DIV_RATIO_MASK, 0x0000);
0150
0151     regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
0152                PCIE_PHY_PLL_CTRL2_PLL_SDM_EN,
0153                PCIE_PHY_PLL_CTRL2_PLL_SDM_EN);
0154
0155     regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
0156                PCIE_PHY_PLL_CTRL2_CONST_SDM_EN,
0157                PCIE_PHY_PLL_CTRL2_CONST_SDM_EN);
0158
0159     regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL3,
0160                PCIE_PHY_PLL_A_CTRL3_MMD_MASK,
0161                FIELD_PREP(PCIE_PHY_PLL_A_CTRL3_MMD_MASK, 0x1));
0162
0163     regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_A_CTRL2,
0164                PCIE_PHY_PLL_A_CTRL2_LF_MODE_EN, 0x0000);
0165
0166     /* const_sdm */
0167     regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL1, 0x38e4);
0168
0169     regmap_update_bits(priv->phy_regmap, PCIE_PHY_PLL_CTRL2,
0170                PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK,
0171                FIELD_PREP(PCIE_PHY_PLL_CTRL2_CONST_SDM_MASK,
0172                       0xee));
0173
0174     /* pllmod */
0175     regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL7, 0x0002);
0176     regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL6, 0x3a04);
0177     regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL5, 0xfae3);
0178     regmap_write(priv->phy_regmap, PCIE_PHY_PLL_CTRL4, 0x1b72);
0179 }
0180
0181 static int ltq_vrx200_pcie_phy_wait_for_pll(struct phy *phy)
0182 {
0183     struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
0184     unsigned int tmp;
0185     int ret;
0186
0187     ret = regmap_read_poll_timeout(priv->phy_regmap, PCIE_PHY_PLL_STATUS,
0188                        tmp, ((tmp & 0x0070) == 0x0070), 10,
0189                        10000);
0190     if (ret) {
0191         dev_err(priv->dev, "PLL Link timeout, PLL status = 0x%04x\n",
0192             tmp);
0193         return ret;
0194     }
0195
0196     return 0;
0197 }
0198
0199 static void ltq_vrx200_pcie_phy_apply_workarounds(struct phy *phy)
0200 {
0201     struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
0202     static const struct reg_default slices[] =  {
0203         {
0204             .reg = PCIE_PHY_TX1_CTRL1,
0205             .def = PCIE_PHY_TX1_CTRL1_LOAD_EN,
0206         },
0207         {
0208             .reg = PCIE_PHY_TX2_CTRL1,
0209             .def = PCIE_PHY_TX2_CTRL1_LOAD_EN,
0210         },
0211         {
0212             .reg = PCIE_PHY_RX1_CTRL1,
0213             .def = PCIE_PHY_RX1_CTRL1_LOAD_EN,
0214         }
0215     };
0216     int i;
0217
0218     for (i = 0; i < ARRAY_SIZE(slices); i++) {
0219         /* enable load_en */
0220         regmap_update_bits(priv->phy_regmap, slices[i].reg,
0221                    slices[i].def, slices[i].def);
0222
0223         udelay(1);
0224
0225         /* disable load_en */
0226         regmap_update_bits(priv->phy_regmap, slices[i].reg,
0227                    slices[i].def, 0x0);
0228     }
0229
0230     for (i = 0; i < 5; i++) {
0231         /* TX2 modulation */
0232         regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD1, 0x1ffe);
0233         regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD2, 0xfffe);
0234         regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD3, 0x0601);
0235         usleep_range(1000, 2000);
0236         regmap_write(priv->phy_regmap, PCIE_PHY_TX2_MOD3, 0x0001);
0237
0238         /* TX1 modulation */
0239         regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD1, 0x1ffe);
0240         regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD2, 0xfffe);
0241         regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD3, 0x0601);
0242         usleep_range(1000, 2000);
0243         regmap_write(priv->phy_regmap, PCIE_PHY_TX1_MOD3, 0x0001);
0244     }
0245 }
0246
0247 static int ltq_vrx200_pcie_phy_init(struct phy *phy)
0248 {
0249     struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
0250     int ret;
0251
0252     if (of_device_is_big_endian(priv->dev->of_node))
0253         regmap_update_bits(priv->rcu_regmap,
0254                    priv->rcu_ahb_endian_offset,
0255                    priv->rcu_ahb_endian_big_endian_mask,
0256                    priv->rcu_ahb_endian_big_endian_mask);
0257     else
0258         regmap_update_bits(priv->rcu_regmap,
0259                    priv->rcu_ahb_endian_offset,
0260                    priv->rcu_ahb_endian_big_endian_mask, 0x0);
0261
0262     ret = reset_control_assert(priv->phy_reset);
0263     if (ret)
0264         goto err;
0265
0266     udelay(1);
0267
0268     ret = reset_control_deassert(priv->phy_reset);
0269     if (ret)
0270         goto err;
0271
0272     udelay(1);
0273
0274     ret = reset_control_deassert(priv->pcie_reset);
0275     if (ret)
0276         goto err_assert_phy_reset;
0277
0278     /* Make sure PHY PLL is stable */
0279     usleep_range(20, 40);
0280
0281     return 0;
0282
0283 err_assert_phy_reset:
0284     reset_control_assert(priv->phy_reset);
0285 err:
0286     return ret;
0287 }
0288
0289 static int ltq_vrx200_pcie_phy_exit(struct phy *phy)
0290 {
0291     struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
0292     int ret;
0293
0294     ret = reset_control_assert(priv->pcie_reset);
0295     if (ret)
0296         return ret;
0297
0298     ret = reset_control_assert(priv->phy_reset);
0299     if (ret)
0300         return ret;
0301
0302     return 0;
0303 }
0304
0305 static int ltq_vrx200_pcie_phy_power_on(struct phy *phy)
0306 {
0307     struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
0308     int ret;
0309
0310     /* Enable PDI to access PCIe PHY register */
0311     ret = clk_prepare_enable(priv->pdi_clk);
0312     if (ret)
0313         goto err;
0314
0315     /* Configure PLL and PHY clock */
0316     ltq_vrx200_pcie_phy_common_setup(phy);
0317
0318     pcie_phy_36mhz_mode_setup(phy);
0319
0320     /* Enable the PCIe PHY and make PLL setting take effect */
0321     ret = clk_prepare_enable(priv->phy_clk);
0322     if (ret)
0323         goto err_disable_pdi_clk;
0324
0325     /* Check if we are in "startup ready" status */
0326     ret = ltq_vrx200_pcie_phy_wait_for_pll(phy);
0327     if (ret)
0328         goto err_disable_phy_clk;
0329
0330     ltq_vrx200_pcie_phy_apply_workarounds(phy);
0331
0332     return 0;
0333
0334 err_disable_phy_clk:
0335     clk_disable_unprepare(priv->phy_clk);
0336 err_disable_pdi_clk:
0337     clk_disable_unprepare(priv->pdi_clk);
0338 err:
0339     return ret;
0340 }
0341
0342 static int ltq_vrx200_pcie_phy_power_off(struct phy *phy)
0343 {
0344     struct ltq_vrx200_pcie_phy_priv *priv = phy_get_drvdata(phy);
0345
0346     clk_disable_unprepare(priv->phy_clk);
0347     clk_disable_unprepare(priv->pdi_clk);
0348
0349     return 0;
0350 }
0351
0352 static const struct phy_ops ltq_vrx200_pcie_phy_ops = {
0353     .init       = ltq_vrx200_pcie_phy_init,
0354     .exit       = ltq_vrx200_pcie_phy_exit,
0355     .power_on   = ltq_vrx200_pcie_phy_power_on,
0356     .power_off  = ltq_vrx200_pcie_phy_power_off,
0357     .owner      = THIS_MODULE,
0358 };
0359
0360 static struct phy *ltq_vrx200_pcie_phy_xlate(struct device *dev,
0361                          struct of_phandle_args *args)
0362 {
0363     struct ltq_vrx200_pcie_phy_priv *priv = dev_get_drvdata(dev);
0364     unsigned int mode;
0365
0366     if (args->args_count != 1) {
0367         dev_err(dev, "invalid number of arguments\n");
0368         return ERR_PTR(-EINVAL);
0369     }
0370
0371     mode = args->args[0];
0372
0373     switch (mode) {
0374     case LANTIQ_PCIE_PHY_MODE_36MHZ:
0375         priv->mode = mode;
0376         break;
0377
0378     case LANTIQ_PCIE_PHY_MODE_25MHZ:
0379     case LANTIQ_PCIE_PHY_MODE_25MHZ_SSC:
0380     case LANTIQ_PCIE_PHY_MODE_36MHZ_SSC:
0381     case LANTIQ_PCIE_PHY_MODE_100MHZ:
0382     case LANTIQ_PCIE_PHY_MODE_100MHZ_SSC:
0383         dev_err(dev, "PHY mode not implemented yet: %u\n", mode);
0384         return ERR_PTR(-EINVAL);
0385
0386     default:
0387         dev_err(dev, "invalid PHY mode %u\n", mode);
0388         return ERR_PTR(-EINVAL);
0389     }
0390
0391     return priv->phy;
0392 }
0393
0394 static int ltq_vrx200_pcie_phy_probe(struct platform_device *pdev)
0395 {
0396     static const struct regmap_config regmap_config = {
0397         .reg_bits = 8,
0398         .val_bits = 16,
0399         .reg_stride = 2,
0400         .max_register = PCIE_PHY_RX1_A_CTRL,
0401     };
0402     struct ltq_vrx200_pcie_phy_priv *priv;
0403     struct device *dev = &pdev->dev;
0404     struct phy_provider *provider;
0405     void __iomem *base;
0406     int ret;
0407
0408     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0409     if (!priv)
0410         return -ENOMEM;
0411
0412     base = devm_platform_ioremap_resource(pdev, 0);
0413     if (IS_ERR(base))
0414         return PTR_ERR(base);
0415
0416     priv->phy_regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
0417     if (IS_ERR(priv->phy_regmap))
0418         return PTR_ERR(priv->phy_regmap);
0419
0420     priv->rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
0421                                "lantiq,rcu");
0422     if (IS_ERR(priv->rcu_regmap))
0423         return PTR_ERR(priv->rcu_regmap);
0424
0425     ret = device_property_read_u32(dev, "lantiq,rcu-endian-offset",
0426                        &priv->rcu_ahb_endian_offset);
0427     if (ret) {
0428         dev_err(dev,
0429             "failed to parse the 'lantiq,rcu-endian-offset' property\n");
0430         return ret;
0431     }
0432
0433     ret = device_property_read_u32(dev, "lantiq,rcu-big-endian-mask",
0434                        &priv->rcu_ahb_endian_big_endian_mask);
0435     if (ret) {
0436         dev_err(dev,
0437             "failed to parse the 'lantiq,rcu-big-endian-mask' property\n");
0438         return ret;
0439     }
0440
0441     priv->pdi_clk = devm_clk_get(dev, "pdi");
0442     if (IS_ERR(priv->pdi_clk))
0443         return PTR_ERR(priv->pdi_clk);
0444
0445     priv->phy_clk = devm_clk_get(dev, "phy");
0446     if (IS_ERR(priv->phy_clk))
0447         return PTR_ERR(priv->phy_clk);
0448
0449     priv->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
0450     if (IS_ERR(priv->phy_reset))
0451         return PTR_ERR(priv->phy_reset);
0452
0453     priv->pcie_reset = devm_reset_control_get_shared(dev, "pcie");
0454     if (IS_ERR(priv->pcie_reset))
0455         return PTR_ERR(priv->pcie_reset);
0456
0457     priv->dev = dev;
0458
0459     priv->phy = devm_phy_create(dev, dev->of_node,
0460                     &ltq_vrx200_pcie_phy_ops);
0461     if (IS_ERR(priv->phy)) {
0462         dev_err(dev, "failed to create PHY\n");
0463         return PTR_ERR(priv->phy);
0464     }
0465
0466     phy_set_drvdata(priv->phy, priv);
0467     dev_set_drvdata(dev, priv);
0468
0469     provider = devm_of_phy_provider_register(dev,
0470                          ltq_vrx200_pcie_phy_xlate);
0471
0472     return PTR_ERR_OR_ZERO(provider);
0473 }
0474
0475 static const struct of_device_id ltq_vrx200_pcie_phy_of_match[] = {
0476     { .compatible = "lantiq,vrx200-pcie-phy", },
0477     { .compatible = "lantiq,arx300-pcie-phy", },
0478     { /* sentinel */ },
0479 };
0480 MODULE_DEVICE_TABLE(of, ltq_vrx200_pcie_phy_of_match);
0481
0482 static struct platform_driver ltq_vrx200_pcie_phy_driver = {
0483     .probe  = ltq_vrx200_pcie_phy_probe,
0484     .driver = {
0485         .name   = "ltq-vrx200-pcie-phy",
0486         .of_match_table = ltq_vrx200_pcie_phy_of_match,
0487     }
0488 };
0489 module_platform_driver(ltq_vrx200_pcie_phy_driver);
0490
0491 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
0492 MODULE_DESCRIPTION("Lantiq VRX200 and ARX300 PCIe PHY driver");
0493 MODULE_LICENSE("GPL v2");