phy/intel/phy-intel-lgm-emmc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Intel eMMC PHY driver
0004  * Copyright (C) 2019 Intel, Corp.
0005  */
0006
0007 #include <linux/bits.h>
0008 #include <linux/clk.h>
0009 #include <linux/delay.h>
0010 #include <linux/mfd/syscon.h>
0011 #include <linux/module.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014 #include <linux/phy/phy.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/regmap.h>
0017
0018 /* eMMC phy register definitions */
0019 #define EMMC_PHYCTRL0_REG   0xa8
0020 #define DR_TY_MASK      GENMASK(30, 28)
0021 #define DR_TY_SHIFT(x)      (((x) << 28) & DR_TY_MASK)
0022 #define OTAPDLYENA      BIT(14)
0023 #define OTAPDLYSEL_MASK     GENMASK(13, 10)
0024 #define OTAPDLYSEL_SHIFT(x) (((x) << 10) & OTAPDLYSEL_MASK)
0025
0026 #define EMMC_PHYCTRL1_REG   0xac
0027 #define PDB_MASK        BIT(0)
0028 #define PDB_SHIFT(x)        (((x) << 0) & PDB_MASK)
0029 #define ENDLL_MASK      BIT(7)
0030 #define ENDLL_SHIFT(x)      (((x) << 7) & ENDLL_MASK)
0031
0032 #define EMMC_PHYCTRL2_REG   0xb0
0033 #define FRQSEL_25M      0
0034 #define FRQSEL_50M      1
0035 #define FRQSEL_100M     2
0036 #define FRQSEL_150M     3
0037 #define FRQSEL_MASK     GENMASK(24, 22)
0038 #define FRQSEL_SHIFT(x)     (((x) << 22) & FRQSEL_MASK)
0039
0040 #define EMMC_PHYSTAT_REG    0xbc
0041 #define CALDONE_MASK        BIT(9)
0042 #define DLLRDY_MASK     BIT(8)
0043 #define IS_CALDONE(x)   ((x) & CALDONE_MASK)
0044 #define IS_DLLRDY(x)    ((x) & DLLRDY_MASK)
0045
0046 struct intel_emmc_phy {
0047     struct regmap *syscfg;
0048     struct clk *emmcclk;
0049 };
0050
0051 static int intel_emmc_phy_power(struct phy *phy, bool on_off)
0052 {
0053     struct intel_emmc_phy *priv = phy_get_drvdata(phy);
0054     unsigned int caldone;
0055     unsigned int dllrdy;
0056     unsigned int freqsel;
0057     unsigned long rate;
0058     int ret, quot;
0059
0060     /*
0061      * Keep phyctrl_pdb and phyctrl_endll low to allow
0062      * initialization of CALIO state M/C DFFs
0063      */
0064     ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK,
0065                  PDB_SHIFT(0));
0066     if (ret) {
0067         dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret);
0068         return ret;
0069     }
0070
0071     /* Already finish power_off above */
0072     if (!on_off)
0073         return 0;
0074
0075     rate = clk_get_rate(priv->emmcclk);
0076     quot = DIV_ROUND_CLOSEST(rate, 50000000);
0077     if (quot > FRQSEL_150M)
0078         dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate);
0079     freqsel = clamp_t(int, quot, FRQSEL_25M, FRQSEL_150M);
0080
0081     /*
0082      * According to the user manual, calpad calibration
0083      * cycle takes more than 2us without the minimal recommended
0084      * value, so we may need a little margin here
0085      */
0086     udelay(5);
0087
0088     ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK,
0089                  PDB_SHIFT(1));
0090     if (ret) {
0091         dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret);
0092         return ret;
0093     }
0094
0095     /*
0096      * According to the user manual, it asks driver to wait 5us for
0097      * calpad busy trimming. However it is documented that this value is
0098      * PVT(A.K.A process,voltage and temperature) relevant, so some
0099      * failure cases are found which indicates we should be more tolerant
0100      * to calpad busy trimming.
0101      */
0102     ret = regmap_read_poll_timeout(priv->syscfg, EMMC_PHYSTAT_REG,
0103                        caldone, IS_CALDONE(caldone),
0104                        0, 50);
0105     if (ret) {
0106         dev_err(&phy->dev, "caldone failed, ret=%d\n", ret);
0107         return ret;
0108     }
0109
0110     /* Set the frequency of the DLL operation */
0111     ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL2_REG, FRQSEL_MASK,
0112                  FRQSEL_SHIFT(freqsel));
0113     if (ret) {
0114         dev_err(&phy->dev, "set the frequency of dll failed:%d\n", ret);
0115         return ret;
0116     }
0117
0118     /* Turn on the DLL */
0119     ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, ENDLL_MASK,
0120                  ENDLL_SHIFT(1));
0121     if (ret) {
0122         dev_err(&phy->dev, "turn on the dll failed: %d\n", ret);
0123         return ret;
0124     }
0125
0126     /*
0127      * After enabling analog DLL circuits docs say that we need 10.2 us if
0128      * our source clock is at 50 MHz and that lock time scales linearly
0129      * with clock speed.  If we are powering on the PHY and the card clock
0130      * is super slow (like 100 kHZ) this could take as long as 5.1 ms as
0131      * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms
0132      * Hopefully we won't be running at 100 kHz, but we should still make
0133      * sure we wait long enough.
0134      *
0135      * NOTE: There appear to be corner cases where the DLL seems to take
0136      * extra long to lock for reasons that aren't understood.  In some
0137      * extreme cases we've seen it take up to over 10ms (!).  We'll be
0138      * generous and give it 50ms.
0139      */
0140     ret = regmap_read_poll_timeout(priv->syscfg,
0141                        EMMC_PHYSTAT_REG,
0142                        dllrdy, IS_DLLRDY(dllrdy),
0143                        0, 50 * USEC_PER_MSEC);
0144     if (ret) {
0145         dev_err(&phy->dev, "dllrdy failed. ret=%d\n", ret);
0146         return ret;
0147     }
0148
0149     return 0;
0150 }
0151
0152 static int intel_emmc_phy_init(struct phy *phy)
0153 {
0154     struct intel_emmc_phy *priv = phy_get_drvdata(phy);
0155
0156     /*
0157      * We purposely get the clock here and not in probe to avoid the
0158      * circular dependency problem. We expect:
0159      * - PHY driver to probe
0160      * - SDHCI driver to start probe
0161      * - SDHCI driver to register it's clock
0162      * - SDHCI driver to get the PHY
0163      * - SDHCI driver to init the PHY
0164      *
0165      * The clock is optional, so upon any error just return it like
0166      * any other error to user.
0167      *
0168      */
0169     priv->emmcclk = clk_get_optional(&phy->dev, "emmcclk");
0170     if (IS_ERR(priv->emmcclk)) {
0171         dev_err(&phy->dev, "ERROR: getting emmcclk\n");
0172         return PTR_ERR(priv->emmcclk);
0173     }
0174
0175     return 0;
0176 }
0177
0178 static int intel_emmc_phy_exit(struct phy *phy)
0179 {
0180     struct intel_emmc_phy *priv = phy_get_drvdata(phy);
0181
0182     clk_put(priv->emmcclk);
0183
0184     return 0;
0185 }
0186
0187 static int intel_emmc_phy_power_on(struct phy *phy)
0188 {
0189     struct intel_emmc_phy *priv = phy_get_drvdata(phy);
0190     int ret;
0191
0192     /* Drive impedance: 50 Ohm */
0193     ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL0_REG, DR_TY_MASK,
0194                  DR_TY_SHIFT(6));
0195     if (ret) {
0196         dev_err(&phy->dev, "ERROR set drive-impednce-50ohm: %d\n", ret);
0197         return ret;
0198     }
0199
0200     /* Output tap delay: disable */
0201     ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL0_REG, OTAPDLYENA,
0202                  0);
0203     if (ret) {
0204         dev_err(&phy->dev, "ERROR Set output tap delay : %d\n", ret);
0205         return ret;
0206     }
0207
0208     /* Output tap delay */
0209     ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL0_REG,
0210                  OTAPDLYSEL_MASK, OTAPDLYSEL_SHIFT(4));
0211     if (ret) {
0212         dev_err(&phy->dev, "ERROR: output tap dly select: %d\n", ret);
0213         return ret;
0214     }
0215
0216     /* Power up eMMC phy analog blocks */
0217     return intel_emmc_phy_power(phy, true);
0218 }
0219
0220 static int intel_emmc_phy_power_off(struct phy *phy)
0221 {
0222     /* Power down eMMC phy analog blocks */
0223     return intel_emmc_phy_power(phy, false);
0224 }
0225
0226 static const struct phy_ops ops = {
0227     .init       = intel_emmc_phy_init,
0228     .exit       = intel_emmc_phy_exit,
0229     .power_on   = intel_emmc_phy_power_on,
0230     .power_off  = intel_emmc_phy_power_off,
0231     .owner      = THIS_MODULE,
0232 };
0233
0234 static int intel_emmc_phy_probe(struct platform_device *pdev)
0235 {
0236     struct device *dev = &pdev->dev;
0237     struct device_node *np = dev->of_node;
0238     struct intel_emmc_phy *priv;
0239     struct phy *generic_phy;
0240     struct phy_provider *phy_provider;
0241
0242     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0243     if (!priv)
0244         return -ENOMEM;
0245
0246     /* Get eMMC phy (accessed via chiptop) regmap */
0247     priv->syscfg = syscon_regmap_lookup_by_phandle(np, "intel,syscon");
0248     if (IS_ERR(priv->syscfg)) {
0249         dev_err(dev, "failed to find syscon\n");
0250         return PTR_ERR(priv->syscfg);
0251     }
0252
0253     generic_phy = devm_phy_create(dev, np, &ops);
0254     if (IS_ERR(generic_phy)) {
0255         dev_err(dev, "failed to create PHY\n");
0256         return PTR_ERR(generic_phy);
0257     }
0258
0259     phy_set_drvdata(generic_phy, priv);
0260     phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0261
0262     return PTR_ERR_OR_ZERO(phy_provider);
0263 }
0264
0265 static const struct of_device_id intel_emmc_phy_dt_ids[] = {
0266     { .compatible = "intel,lgm-emmc-phy" },
0267     {}
0268 };
0269
0270 MODULE_DEVICE_TABLE(of, intel_emmc_phy_dt_ids);
0271
0272 static struct platform_driver intel_emmc_driver = {
0273     .probe      = intel_emmc_phy_probe,
0274     .driver     = {
0275         .name   = "intel-emmc-phy",
0276         .of_match_table = intel_emmc_phy_dt_ids,
0277     },
0278 };
0279
0280 module_platform_driver(intel_emmc_driver);
0281
0282 MODULE_AUTHOR("Peter Harliman Liem <peter.harliman.liem@intel.com>");
0283 MODULE_DESCRIPTION("Intel eMMC PHY driver");
0284 MODULE_LICENSE("GPL v2");