phy/ingenic/phy-ingenic-usb.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Ingenic SoCs USB PHY driver
0004  * Copyright (c) Paul Cercueil <paul@crapouillou.net>
0005  * Copyright (c) 漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com>
0006  * Copyright (c) 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
0007  */
0008
0009 #include <linux/bitfield.h>
0010 #include <linux/clk.h>
0011 #include <linux/delay.h>
0012 #include <linux/io.h>
0013 #include <linux/module.h>
0014 #include <linux/phy/phy.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/regulator/consumer.h>
0017
0018 /* OTGPHY register offsets */
0019 #define REG_USBPCR_OFFSET           0x00
0020 #define REG_USBRDT_OFFSET           0x04
0021 #define REG_USBVBFIL_OFFSET         0x08
0022 #define REG_USBPCR1_OFFSET          0x0c
0023
0024 /* bits within the USBPCR register */
0025 #define USBPCR_USB_MODE             BIT(31)
0026 #define USBPCR_AVLD_REG             BIT(30)
0027 #define USBPCR_COMMONONN            BIT(25)
0028 #define USBPCR_VBUSVLDEXT           BIT(24)
0029 #define USBPCR_VBUSVLDEXTSEL        BIT(23)
0030 #define USBPCR_POR                  BIT(22)
0031 #define USBPCR_SIDDQ                BIT(21)
0032 #define USBPCR_OTG_DISABLE          BIT(20)
0033 #define USBPCR_TXPREEMPHTUNE        BIT(6)
0034
0035 #define USBPCR_IDPULLUP_MASK        GENMASK(29, 28)
0036 #define USBPCR_IDPULLUP_ALWAYS      0x2
0037 #define USBPCR_IDPULLUP_SUSPEND     0x1
0038 #define USBPCR_IDPULLUP_OTG         0x0
0039
0040 #define USBPCR_COMPDISTUNE_MASK     GENMASK(19, 17)
0041 #define USBPCR_COMPDISTUNE_DFT      0x4
0042
0043 #define USBPCR_OTGTUNE_MASK         GENMASK(16, 14)
0044 #define USBPCR_OTGTUNE_DFT          0x4
0045
0046 #define USBPCR_SQRXTUNE_MASK        GENMASK(13, 11)
0047 #define USBPCR_SQRXTUNE_DCR_20PCT   0x7
0048 #define USBPCR_SQRXTUNE_DFT         0x3
0049
0050 #define USBPCR_TXFSLSTUNE_MASK      GENMASK(10, 7)
0051 #define USBPCR_TXFSLSTUNE_DCR_50PPT 0xf
0052 #define USBPCR_TXFSLSTUNE_DCR_25PPT 0x7
0053 #define USBPCR_TXFSLSTUNE_DFT       0x3
0054 #define USBPCR_TXFSLSTUNE_INC_25PPT 0x1
0055 #define USBPCR_TXFSLSTUNE_INC_50PPT 0x0
0056
0057 #define USBPCR_TXHSXVTUNE_MASK      GENMASK(5, 4)
0058 #define USBPCR_TXHSXVTUNE_DFT       0x3
0059 #define USBPCR_TXHSXVTUNE_DCR_15MV  0x1
0060
0061 #define USBPCR_TXRISETUNE_MASK      GENMASK(5, 4)
0062 #define USBPCR_TXRISETUNE_DFT       0x3
0063
0064 #define USBPCR_TXVREFTUNE_MASK      GENMASK(3, 0)
0065 #define USBPCR_TXVREFTUNE_INC_75PPT 0xb
0066 #define USBPCR_TXVREFTUNE_INC_25PPT 0x7
0067 #define USBPCR_TXVREFTUNE_DFT       0x5
0068
0069 /* bits within the USBRDTR register */
0070 #define USBRDT_UTMI_RST             BIT(27)
0071 #define USBRDT_HB_MASK              BIT(26)
0072 #define USBRDT_VBFIL_LD_EN          BIT(25)
0073 #define USBRDT_IDDIG_EN             BIT(24)
0074 #define USBRDT_IDDIG_REG            BIT(23)
0075 #define USBRDT_VBFIL_EN             BIT(2)
0076
0077 /* bits within the USBPCR1 register */
0078 #define USBPCR1_BVLD_REG            BIT(31)
0079 #define USBPCR1_DPPD                BIT(29)
0080 #define USBPCR1_DMPD                BIT(28)
0081 #define USBPCR1_USB_SEL             BIT(28)
0082 #define USBPCR1_PORT_RST            BIT(21)
0083 #define USBPCR1_WORD_IF_16BIT       BIT(19)
0084
0085 struct ingenic_soc_info {
0086     void (*usb_phy_init)(struct phy *phy);
0087 };
0088
0089 struct ingenic_usb_phy {
0090     const struct ingenic_soc_info *soc_info;
0091
0092     struct phy *phy;
0093     void __iomem *base;
0094     struct clk *clk;
0095     struct regulator *vcc_supply;
0096 };
0097
0098 static int ingenic_usb_phy_init(struct phy *phy)
0099 {
0100     struct ingenic_usb_phy *priv = phy_get_drvdata(phy);
0101     int err;
0102     u32 reg;
0103
0104     err = clk_prepare_enable(priv->clk);
0105     if (err) {
0106         dev_err(&phy->dev, "Unable to start clock: %d\n", err);
0107         return err;
0108     }
0109
0110     priv->soc_info->usb_phy_init(phy);
0111
0112     /* Wait for PHY to reset */
0113     usleep_range(30, 300);
0114     reg = readl(priv->base + REG_USBPCR_OFFSET);
0115     writel(reg & ~USBPCR_POR, priv->base + REG_USBPCR_OFFSET);
0116     usleep_range(300, 1000);
0117
0118     return 0;
0119 }
0120
0121 static int ingenic_usb_phy_exit(struct phy *phy)
0122 {
0123     struct ingenic_usb_phy *priv = phy_get_drvdata(phy);
0124
0125     clk_disable_unprepare(priv->clk);
0126     regulator_disable(priv->vcc_supply);
0127
0128     return 0;
0129 }
0130
0131 static int ingenic_usb_phy_power_on(struct phy *phy)
0132 {
0133     struct ingenic_usb_phy *priv = phy_get_drvdata(phy);
0134     int err;
0135
0136     err = regulator_enable(priv->vcc_supply);
0137     if (err) {
0138         dev_err(&phy->dev, "Unable to enable VCC: %d\n", err);
0139         return err;
0140     }
0141
0142     return 0;
0143 }
0144
0145 static int ingenic_usb_phy_power_off(struct phy *phy)
0146 {
0147     struct ingenic_usb_phy *priv = phy_get_drvdata(phy);
0148
0149     regulator_disable(priv->vcc_supply);
0150
0151     return 0;
0152 }
0153
0154 static int ingenic_usb_phy_set_mode(struct phy *phy,
0155                   enum phy_mode mode, int submode)
0156 {
0157     struct ingenic_usb_phy *priv = phy_get_drvdata(phy);
0158     u32 reg;
0159
0160     switch (mode) {
0161     case PHY_MODE_USB_HOST:
0162         reg = readl(priv->base + REG_USBPCR_OFFSET);
0163         u32p_replace_bits(&reg, 1, USBPCR_USB_MODE);
0164         u32p_replace_bits(&reg, 0, USBPCR_VBUSVLDEXT);
0165         u32p_replace_bits(&reg, 0, USBPCR_VBUSVLDEXTSEL);
0166         u32p_replace_bits(&reg, 0, USBPCR_OTG_DISABLE);
0167         writel(reg, priv->base + REG_USBPCR_OFFSET);
0168
0169         break;
0170     case PHY_MODE_USB_DEVICE:
0171         reg = readl(priv->base + REG_USBPCR_OFFSET);
0172         u32p_replace_bits(&reg, 0, USBPCR_USB_MODE);
0173         u32p_replace_bits(&reg, 1, USBPCR_VBUSVLDEXT);
0174         u32p_replace_bits(&reg, 1, USBPCR_VBUSVLDEXTSEL);
0175         u32p_replace_bits(&reg, 1, USBPCR_OTG_DISABLE);
0176         writel(reg, priv->base + REG_USBPCR_OFFSET);
0177
0178         break;
0179     case PHY_MODE_USB_OTG:
0180         reg = readl(priv->base + REG_USBPCR_OFFSET);
0181         u32p_replace_bits(&reg, 1, USBPCR_USB_MODE);
0182         u32p_replace_bits(&reg, 1, USBPCR_VBUSVLDEXT);
0183         u32p_replace_bits(&reg, 1, USBPCR_VBUSVLDEXTSEL);
0184         u32p_replace_bits(&reg, 0, USBPCR_OTG_DISABLE);
0185         writel(reg, priv->base + REG_USBPCR_OFFSET);
0186
0187         break;
0188     default:
0189         return -EINVAL;
0190     }
0191
0192     return 0;
0193 }
0194
0195 static const struct phy_ops ingenic_usb_phy_ops = {
0196     .init       = ingenic_usb_phy_init,
0197     .exit       = ingenic_usb_phy_exit,
0198     .power_on   = ingenic_usb_phy_power_on,
0199     .power_off  = ingenic_usb_phy_power_off,
0200     .set_mode   = ingenic_usb_phy_set_mode,
0201     .owner      = THIS_MODULE,
0202 };
0203
0204 static void jz4770_usb_phy_init(struct phy *phy)
0205 {
0206     struct ingenic_usb_phy *priv = phy_get_drvdata(phy);
0207     u32 reg;
0208
0209     reg = USBPCR_AVLD_REG | USBPCR_COMMONONN | USBPCR_POR |
0210         FIELD_PREP(USBPCR_IDPULLUP_MASK, USBPCR_IDPULLUP_ALWAYS) |
0211         FIELD_PREP(USBPCR_COMPDISTUNE_MASK, USBPCR_COMPDISTUNE_DFT) |
0212         FIELD_PREP(USBPCR_OTGTUNE_MASK, USBPCR_OTGTUNE_DFT) |
0213         FIELD_PREP(USBPCR_SQRXTUNE_MASK, USBPCR_SQRXTUNE_DFT) |
0214         FIELD_PREP(USBPCR_TXFSLSTUNE_MASK, USBPCR_TXFSLSTUNE_DFT) |
0215         FIELD_PREP(USBPCR_TXRISETUNE_MASK, USBPCR_TXRISETUNE_DFT) |
0216         FIELD_PREP(USBPCR_TXVREFTUNE_MASK, USBPCR_TXVREFTUNE_DFT);
0217     writel(reg, priv->base + REG_USBPCR_OFFSET);
0218 }
0219
0220 static void jz4775_usb_phy_init(struct phy *phy)
0221 {
0222     struct ingenic_usb_phy *priv = phy_get_drvdata(phy);
0223     u32 reg;
0224
0225     reg = readl(priv->base + REG_USBPCR1_OFFSET) | USBPCR1_USB_SEL |
0226         USBPCR1_WORD_IF_16BIT;
0227     writel(reg, priv->base + REG_USBPCR1_OFFSET);
0228
0229     reg = USBPCR_COMMONONN | USBPCR_POR |
0230         FIELD_PREP(USBPCR_TXVREFTUNE_MASK, USBPCR_TXVREFTUNE_INC_75PPT);
0231     writel(reg, priv->base + REG_USBPCR_OFFSET);
0232 }
0233
0234 static void jz4780_usb_phy_init(struct phy *phy)
0235 {
0236     struct ingenic_usb_phy *priv = phy_get_drvdata(phy);
0237     u32 reg;
0238
0239     reg = readl(priv->base + REG_USBPCR1_OFFSET) | USBPCR1_USB_SEL |
0240         USBPCR1_WORD_IF_16BIT;
0241     writel(reg, priv->base + REG_USBPCR1_OFFSET);
0242
0243     reg = USBPCR_TXPREEMPHTUNE | USBPCR_COMMONONN | USBPCR_POR;
0244     writel(reg, priv->base + REG_USBPCR_OFFSET);
0245 }
0246
0247 static void x1000_usb_phy_init(struct phy *phy)
0248 {
0249     struct ingenic_usb_phy *priv = phy_get_drvdata(phy);
0250     u32 reg;
0251
0252     reg = readl(priv->base + REG_USBPCR1_OFFSET) | USBPCR1_WORD_IF_16BIT;
0253     writel(reg, priv->base + REG_USBPCR1_OFFSET);
0254
0255     reg = USBPCR_TXPREEMPHTUNE | USBPCR_COMMONONN | USBPCR_POR |
0256         FIELD_PREP(USBPCR_SQRXTUNE_MASK, USBPCR_SQRXTUNE_DCR_20PCT) |
0257         FIELD_PREP(USBPCR_TXHSXVTUNE_MASK, USBPCR_TXHSXVTUNE_DCR_15MV) |
0258         FIELD_PREP(USBPCR_TXVREFTUNE_MASK, USBPCR_TXVREFTUNE_INC_25PPT);
0259     writel(reg, priv->base + REG_USBPCR_OFFSET);
0260 }
0261
0262 static void x1830_usb_phy_init(struct phy *phy)
0263 {
0264     struct ingenic_usb_phy *priv = phy_get_drvdata(phy);
0265     u32 reg;
0266
0267     /* rdt */
0268     writel(USBRDT_VBFIL_EN | USBRDT_UTMI_RST, priv->base + REG_USBRDT_OFFSET);
0269
0270     reg = readl(priv->base + REG_USBPCR1_OFFSET) | USBPCR1_WORD_IF_16BIT |
0271         USBPCR1_DMPD | USBPCR1_DPPD;
0272     writel(reg, priv->base + REG_USBPCR1_OFFSET);
0273
0274     reg = USBPCR_VBUSVLDEXT | USBPCR_TXPREEMPHTUNE | USBPCR_COMMONONN | USBPCR_POR |
0275         FIELD_PREP(USBPCR_IDPULLUP_MASK, USBPCR_IDPULLUP_OTG);
0276     writel(reg, priv->base + REG_USBPCR_OFFSET);
0277 }
0278
0279 static void x2000_usb_phy_init(struct phy *phy)
0280 {
0281     struct ingenic_usb_phy *priv = phy_get_drvdata(phy);
0282     u32 reg;
0283
0284     reg = readl(priv->base + REG_USBPCR1_OFFSET) | USBPCR1_DPPD | USBPCR1_DMPD;
0285     writel(reg & ~USBPCR1_PORT_RST, priv->base + REG_USBPCR1_OFFSET);
0286
0287     reg = USBPCR_POR | FIELD_PREP(USBPCR_IDPULLUP_MASK, USBPCR_IDPULLUP_OTG);
0288     writel(reg, priv->base + REG_USBPCR_OFFSET);
0289 }
0290
0291 static const struct ingenic_soc_info jz4770_soc_info = {
0292     .usb_phy_init = jz4770_usb_phy_init,
0293 };
0294
0295 static const struct ingenic_soc_info jz4775_soc_info = {
0296     .usb_phy_init = jz4775_usb_phy_init,
0297 };
0298
0299 static const struct ingenic_soc_info jz4780_soc_info = {
0300     .usb_phy_init = jz4780_usb_phy_init,
0301 };
0302
0303 static const struct ingenic_soc_info x1000_soc_info = {
0304     .usb_phy_init = x1000_usb_phy_init,
0305 };
0306
0307 static const struct ingenic_soc_info x1830_soc_info = {
0308     .usb_phy_init = x1830_usb_phy_init,
0309 };
0310
0311 static const struct ingenic_soc_info x2000_soc_info = {
0312     .usb_phy_init = x2000_usb_phy_init,
0313 };
0314
0315 static int ingenic_usb_phy_probe(struct platform_device *pdev)
0316 {
0317     struct ingenic_usb_phy *priv;
0318     struct phy_provider *provider;
0319     struct device *dev = &pdev->dev;
0320     int err;
0321
0322     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0323     if (!priv)
0324         return -ENOMEM;
0325
0326     priv->soc_info = device_get_match_data(dev);
0327     if (!priv->soc_info) {
0328         dev_err(dev, "Error: No device match found\n");
0329         return -ENODEV;
0330     }
0331
0332     priv->base = devm_platform_ioremap_resource(pdev, 0);
0333     if (IS_ERR(priv->base)) {
0334         dev_err(dev, "Failed to map registers\n");
0335         return PTR_ERR(priv->base);
0336     }
0337
0338     priv->clk = devm_clk_get(dev, NULL);
0339     if (IS_ERR(priv->clk)) {
0340         err = PTR_ERR(priv->clk);
0341         if (err != -EPROBE_DEFER)
0342             dev_err(dev, "Failed to get clock\n");
0343         return err;
0344     }
0345
0346     priv->vcc_supply = devm_regulator_get(dev, "vcc");
0347     if (IS_ERR(priv->vcc_supply)) {
0348         err = PTR_ERR(priv->vcc_supply);
0349         if (err != -EPROBE_DEFER)
0350             dev_err(dev, "Failed to get regulator\n");
0351         return err;
0352     }
0353
0354     priv->phy = devm_phy_create(dev, NULL, &ingenic_usb_phy_ops);
0355     if (IS_ERR(priv->phy))
0356         return PTR_ERR(priv->phy);
0357
0358     phy_set_drvdata(priv->phy, priv);
0359
0360     provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0361
0362     return PTR_ERR_OR_ZERO(provider);
0363 }
0364
0365 static const struct of_device_id ingenic_usb_phy_of_matches[] = {
0366     { .compatible = "ingenic,jz4770-phy", .data = &jz4770_soc_info },
0367     { .compatible = "ingenic,jz4775-phy", .data = &jz4775_soc_info },
0368     { .compatible = "ingenic,jz4780-phy", .data = &jz4780_soc_info },
0369     { .compatible = "ingenic,x1000-phy", .data = &x1000_soc_info },
0370     { .compatible = "ingenic,x1830-phy", .data = &x1830_soc_info },
0371     { .compatible = "ingenic,x2000-phy", .data = &x2000_soc_info },
0372     { /* sentinel */ }
0373 };
0374 MODULE_DEVICE_TABLE(of, ingenic_usb_phy_of_matches);
0375
0376 static struct platform_driver ingenic_usb_phy_driver = {
0377     .probe      = ingenic_usb_phy_probe,
0378     .driver     = {
0379         .name   = "ingenic-usb-phy",
0380         .of_match_table = ingenic_usb_phy_of_matches,
0381     },
0382 };
0383 module_platform_driver(ingenic_usb_phy_driver);
0384
0385 MODULE_AUTHOR("周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>");
0386 MODULE_AUTHOR("漆鹏振 (Qi Pengzhen) <aric.pzqi@ingenic.com>");
0387 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
0388 MODULE_DESCRIPTION("Ingenic SoCs USB PHY driver");
0389 MODULE_LICENSE("GPL");