0001
0002
0003
0004
0005
0006
0007 #include <linux/delay.h>
0008 #include <linux/io.h>
0009 #include <linux/mfd/syscon.h>
0010 #include <linux/module.h>
0011 #include <linux/phy/phy.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/regmap.h>
0014
0015 #define SATA_PHY0_CTLL 0xa0
0016 #define MPLL_MULTIPLIER_SHIFT 1
0017 #define MPLL_MULTIPLIER_MASK 0xfe
0018 #define MPLL_MULTIPLIER_50M 0x3c
0019 #define MPLL_MULTIPLIER_100M 0x1e
0020 #define PHY_RESET BIT(0)
0021 #define REF_SSP_EN BIT(9)
0022 #define SSC_EN BIT(10)
0023 #define REF_USE_PAD BIT(23)
0024
0025 #define SATA_PORT_PHYCTL 0x174
0026 #define SPEED_MODE_MASK 0x6f0000
0027 #define HALF_RATE_SHIFT 16
0028 #define PHY_CONFIG_SHIFT 18
0029 #define GEN2_EN_SHIFT 21
0030 #define SPEED_CTRL BIT(20)
0031
0032 #define SATA_PORT_PHYCTL1 0x148
0033 #define AMPLITUDE_MASK 0x3ffffe
0034 #define AMPLITUDE_GEN3 0x68
0035 #define AMPLITUDE_GEN3_SHIFT 15
0036 #define AMPLITUDE_GEN2 0x56
0037 #define AMPLITUDE_GEN2_SHIFT 8
0038 #define AMPLITUDE_GEN1 0x56
0039 #define AMPLITUDE_GEN1_SHIFT 1
0040
0041 #define SATA_PORT_PHYCTL2 0x14c
0042 #define PREEMPH_MASK 0x3ffff
0043 #define PREEMPH_GEN3 0x20
0044 #define PREEMPH_GEN3_SHIFT 12
0045 #define PREEMPH_GEN2 0x15
0046 #define PREEMPH_GEN2_SHIFT 6
0047 #define PREEMPH_GEN1 0x5
0048 #define PREEMPH_GEN1_SHIFT 0
0049
0050 struct hix5hd2_priv {
0051 void __iomem *base;
0052 struct regmap *peri_ctrl;
0053 };
0054
0055 enum phy_speed_mode {
0056 SPEED_MODE_GEN1 = 0,
0057 SPEED_MODE_GEN2 = 1,
0058 SPEED_MODE_GEN3 = 2,
0059 };
0060
0061 static int hix5hd2_sata_phy_init(struct phy *phy)
0062 {
0063 struct hix5hd2_priv *priv = phy_get_drvdata(phy);
0064 u32 val, data[2];
0065 int ret;
0066
0067 if (priv->peri_ctrl) {
0068 ret = of_property_read_u32_array(phy->dev.of_node,
0069 "hisilicon,power-reg",
0070 &data[0], 2);
0071 if (ret) {
0072 dev_err(&phy->dev, "Fail read hisilicon,power-reg\n");
0073 return ret;
0074 }
0075
0076 regmap_update_bits(priv->peri_ctrl, data[0],
0077 BIT(data[1]), BIT(data[1]));
0078 }
0079
0080
0081 val = readl_relaxed(priv->base + SATA_PHY0_CTLL);
0082 val &= ~(MPLL_MULTIPLIER_MASK | REF_USE_PAD);
0083 val |= MPLL_MULTIPLIER_50M << MPLL_MULTIPLIER_SHIFT |
0084 REF_SSP_EN | PHY_RESET;
0085 writel_relaxed(val, priv->base + SATA_PHY0_CTLL);
0086 msleep(20);
0087 val &= ~PHY_RESET;
0088 writel_relaxed(val, priv->base + SATA_PHY0_CTLL);
0089
0090 val = readl_relaxed(priv->base + SATA_PORT_PHYCTL1);
0091 val &= ~AMPLITUDE_MASK;
0092 val |= AMPLITUDE_GEN3 << AMPLITUDE_GEN3_SHIFT |
0093 AMPLITUDE_GEN2 << AMPLITUDE_GEN2_SHIFT |
0094 AMPLITUDE_GEN1 << AMPLITUDE_GEN1_SHIFT;
0095 writel_relaxed(val, priv->base + SATA_PORT_PHYCTL1);
0096
0097 val = readl_relaxed(priv->base + SATA_PORT_PHYCTL2);
0098 val &= ~PREEMPH_MASK;
0099 val |= PREEMPH_GEN3 << PREEMPH_GEN3_SHIFT |
0100 PREEMPH_GEN2 << PREEMPH_GEN2_SHIFT |
0101 PREEMPH_GEN1 << PREEMPH_GEN1_SHIFT;
0102 writel_relaxed(val, priv->base + SATA_PORT_PHYCTL2);
0103
0104
0105 val = readl_relaxed(priv->base + SATA_PORT_PHYCTL);
0106 val &= ~SPEED_MODE_MASK;
0107 val |= SPEED_MODE_GEN1 << HALF_RATE_SHIFT |
0108 SPEED_MODE_GEN1 << PHY_CONFIG_SHIFT |
0109 SPEED_MODE_GEN1 << GEN2_EN_SHIFT | SPEED_CTRL;
0110 writel_relaxed(val, priv->base + SATA_PORT_PHYCTL);
0111
0112 msleep(20);
0113 val &= ~SPEED_MODE_MASK;
0114 val |= SPEED_MODE_GEN3 << HALF_RATE_SHIFT |
0115 SPEED_MODE_GEN3 << PHY_CONFIG_SHIFT |
0116 SPEED_MODE_GEN3 << GEN2_EN_SHIFT | SPEED_CTRL;
0117 writel_relaxed(val, priv->base + SATA_PORT_PHYCTL);
0118
0119 val &= ~(SPEED_MODE_MASK | SPEED_CTRL);
0120 val |= SPEED_MODE_GEN2 << HALF_RATE_SHIFT |
0121 SPEED_MODE_GEN2 << PHY_CONFIG_SHIFT |
0122 SPEED_MODE_GEN2 << GEN2_EN_SHIFT;
0123 writel_relaxed(val, priv->base + SATA_PORT_PHYCTL);
0124
0125 return 0;
0126 }
0127
0128 static const struct phy_ops hix5hd2_sata_phy_ops = {
0129 .init = hix5hd2_sata_phy_init,
0130 .owner = THIS_MODULE,
0131 };
0132
0133 static int hix5hd2_sata_phy_probe(struct platform_device *pdev)
0134 {
0135 struct phy_provider *phy_provider;
0136 struct device *dev = &pdev->dev;
0137 struct resource *res;
0138 struct phy *phy;
0139 struct hix5hd2_priv *priv;
0140
0141 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0142 if (!priv)
0143 return -ENOMEM;
0144
0145 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0146 if (!res)
0147 return -EINVAL;
0148
0149 priv->base = devm_ioremap(dev, res->start, resource_size(res));
0150 if (!priv->base)
0151 return -ENOMEM;
0152
0153 priv->peri_ctrl = syscon_regmap_lookup_by_phandle(dev->of_node,
0154 "hisilicon,peripheral-syscon");
0155 if (IS_ERR(priv->peri_ctrl))
0156 priv->peri_ctrl = NULL;
0157
0158 phy = devm_phy_create(dev, NULL, &hix5hd2_sata_phy_ops);
0159 if (IS_ERR(phy)) {
0160 dev_err(dev, "failed to create PHY\n");
0161 return PTR_ERR(phy);
0162 }
0163
0164 phy_set_drvdata(phy, priv);
0165 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0166 return PTR_ERR_OR_ZERO(phy_provider);
0167 }
0168
0169 static const struct of_device_id hix5hd2_sata_phy_of_match[] = {
0170 {.compatible = "hisilicon,hix5hd2-sata-phy",},
0171 { },
0172 };
0173 MODULE_DEVICE_TABLE(of, hix5hd2_sata_phy_of_match);
0174
0175 static struct platform_driver hix5hd2_sata_phy_driver = {
0176 .probe = hix5hd2_sata_phy_probe,
0177 .driver = {
0178 .name = "hix5hd2-sata-phy",
0179 .of_match_table = hix5hd2_sata_phy_of_match,
0180 }
0181 };
0182 module_platform_driver(hix5hd2_sata_phy_driver);
0183
0184 MODULE_AUTHOR("Jiancheng Xue <xuejiancheng@huawei.com>");
0185 MODULE_DESCRIPTION("HISILICON HIX5HD2 SATA PHY driver");
0186 MODULE_ALIAS("platform:hix5hd2-sata-phy");
0187 MODULE_LICENSE("GPL v2");
