phy/hisilicon/phy-hisi-inno-usb2.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * HiSilicon INNO USB2 PHY Driver.
0004  *
0005  * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
0006  */
0007
0008 #include <linux/clk.h>
0009 #include <linux/delay.h>
0010 #include <linux/io.h>
0011 #include <linux/module.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/phy/phy.h>
0014 #include <linux/reset.h>
0015
0016 #define INNO_PHY_PORT_NUM   2
0017 #define REF_CLK_STABLE_TIME 100 /* unit:us */
0018 #define UTMI_CLK_STABLE_TIME    200 /* unit:us */
0019 #define TEST_CLK_STABLE_TIME    2   /* unit:ms */
0020 #define PHY_CLK_STABLE_TIME 2   /* unit:ms */
0021 #define UTMI_RST_COMPLETE_TIME  2   /* unit:ms */
0022 #define POR_RST_COMPLETE_TIME   300 /* unit:us */
0023 #define PHY_TEST_DATA       GENMASK(7, 0)
0024 #define PHY_TEST_ADDR       GENMASK(15, 8)
0025 #define PHY_TEST_PORT       GENMASK(18, 16)
0026 #define PHY_TEST_WREN       BIT(21)
0027 #define PHY_TEST_CLK        BIT(22) /* rising edge active */
0028 #define PHY_TEST_RST        BIT(23) /* low active */
0029 #define PHY_CLK_ENABLE      BIT(2)
0030
0031 struct hisi_inno_phy_port {
0032     struct reset_control *utmi_rst;
0033     struct hisi_inno_phy_priv *priv;
0034 };
0035
0036 struct hisi_inno_phy_priv {
0037     void __iomem *mmio;
0038     struct clk *ref_clk;
0039     struct reset_control *por_rst;
0040     struct hisi_inno_phy_port ports[INNO_PHY_PORT_NUM];
0041 };
0042
0043 static void hisi_inno_phy_write_reg(struct hisi_inno_phy_priv *priv,
0044                     u8 port, u32 addr, u32 data)
0045 {
0046     void __iomem *reg = priv->mmio;
0047     u32 val;
0048
0049     val = (data & PHY_TEST_DATA) |
0050           ((addr << 8) & PHY_TEST_ADDR) |
0051           ((port << 16) & PHY_TEST_PORT) |
0052           PHY_TEST_WREN | PHY_TEST_RST;
0053     writel(val, reg);
0054
0055     val |= PHY_TEST_CLK;
0056     writel(val, reg);
0057
0058     val &= ~PHY_TEST_CLK;
0059     writel(val, reg);
0060 }
0061
0062 static void hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv)
0063 {
0064     /* The phy clk is controlled by the port0 register 0x06. */
0065     hisi_inno_phy_write_reg(priv, 0, 0x06, PHY_CLK_ENABLE);
0066     msleep(PHY_CLK_STABLE_TIME);
0067 }
0068
0069 static int hisi_inno_phy_init(struct phy *phy)
0070 {
0071     struct hisi_inno_phy_port *port = phy_get_drvdata(phy);
0072     struct hisi_inno_phy_priv *priv = port->priv;
0073     int ret;
0074
0075     ret = clk_prepare_enable(priv->ref_clk);
0076     if (ret)
0077         return ret;
0078     udelay(REF_CLK_STABLE_TIME);
0079
0080     reset_control_deassert(priv->por_rst);
0081     udelay(POR_RST_COMPLETE_TIME);
0082
0083     /* Set up phy registers */
0084     hisi_inno_phy_setup(priv);
0085
0086     reset_control_deassert(port->utmi_rst);
0087     udelay(UTMI_RST_COMPLETE_TIME);
0088
0089     return 0;
0090 }
0091
0092 static int hisi_inno_phy_exit(struct phy *phy)
0093 {
0094     struct hisi_inno_phy_port *port = phy_get_drvdata(phy);
0095     struct hisi_inno_phy_priv *priv = port->priv;
0096
0097     reset_control_assert(port->utmi_rst);
0098     reset_control_assert(priv->por_rst);
0099     clk_disable_unprepare(priv->ref_clk);
0100
0101     return 0;
0102 }
0103
0104 static const struct phy_ops hisi_inno_phy_ops = {
0105     .init = hisi_inno_phy_init,
0106     .exit = hisi_inno_phy_exit,
0107     .owner = THIS_MODULE,
0108 };
0109
0110 static int hisi_inno_phy_probe(struct platform_device *pdev)
0111 {
0112     struct device *dev = &pdev->dev;
0113     struct device_node *np = dev->of_node;
0114     struct hisi_inno_phy_priv *priv;
0115     struct phy_provider *provider;
0116     struct device_node *child;
0117     int i = 0;
0118     int ret;
0119
0120     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0121     if (!priv)
0122         return -ENOMEM;
0123
0124     priv->mmio = devm_platform_ioremap_resource(pdev, 0);
0125     if (IS_ERR(priv->mmio)) {
0126         ret = PTR_ERR(priv->mmio);
0127         return ret;
0128     }
0129
0130     priv->ref_clk = devm_clk_get(dev, NULL);
0131     if (IS_ERR(priv->ref_clk))
0132         return PTR_ERR(priv->ref_clk);
0133
0134     priv->por_rst = devm_reset_control_get_exclusive(dev, NULL);
0135     if (IS_ERR(priv->por_rst))
0136         return PTR_ERR(priv->por_rst);
0137
0138     for_each_child_of_node(np, child) {
0139         struct reset_control *rst;
0140         struct phy *phy;
0141
0142         rst = of_reset_control_get_exclusive(child, NULL);
0143         if (IS_ERR(rst)) {
0144             of_node_put(child);
0145             return PTR_ERR(rst);
0146         }
0147
0148         priv->ports[i].utmi_rst = rst;
0149         priv->ports[i].priv = priv;
0150
0151         phy = devm_phy_create(dev, child, &hisi_inno_phy_ops);
0152         if (IS_ERR(phy)) {
0153             of_node_put(child);
0154             return PTR_ERR(phy);
0155         }
0156
0157         phy_set_bus_width(phy, 8);
0158         phy_set_drvdata(phy, &priv->ports[i]);
0159         i++;
0160
0161         if (i > INNO_PHY_PORT_NUM) {
0162             dev_warn(dev, "Support %d ports in maximum\n", i);
0163             of_node_put(child);
0164             break;
0165         }
0166     }
0167
0168     provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0169     return PTR_ERR_OR_ZERO(provider);
0170 }
0171
0172 static const struct of_device_id hisi_inno_phy_of_match[] = {
0173     { .compatible = "hisilicon,inno-usb2-phy", },
0174     { .compatible = "hisilicon,hi3798cv200-usb2-phy", },
0175     { },
0176 };
0177 MODULE_DEVICE_TABLE(of, hisi_inno_phy_of_match);
0178
0179 static struct platform_driver hisi_inno_phy_driver = {
0180     .probe  = hisi_inno_phy_probe,
0181     .driver = {
0182         .name   = "hisi-inno-phy",
0183         .of_match_table = hisi_inno_phy_of_match,
0184     }
0185 };
0186 module_platform_driver(hisi_inno_phy_driver);
0187
0188 MODULE_DESCRIPTION("HiSilicon INNO USB2 PHY Driver");
0189 MODULE_LICENSE("GPL v2");