phy/hisilicon/phy-hi6220-usb.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (c) 2015 Linaro Ltd.
0004  * Copyright (c) 2015 HiSilicon Limited.
0005  */
0006
0007 #include <linux/mfd/syscon.h>
0008 #include <linux/module.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/phy/phy.h>
0011 #include <linux/regmap.h>
0012
0013 #define SC_PERIPH_CTRL4         0x00c
0014
0015 #define CTRL4_PICO_SIDDQ        BIT(6)
0016 #define CTRL4_PICO_OGDISABLE        BIT(8)
0017 #define CTRL4_PICO_VBUSVLDEXT       BIT(10)
0018 #define CTRL4_PICO_VBUSVLDEXTSEL    BIT(11)
0019 #define CTRL4_OTG_PHY_SEL       BIT(21)
0020
0021 #define SC_PERIPH_CTRL5         0x010
0022
0023 #define CTRL5_USBOTG_RES_SEL        BIT(3)
0024 #define CTRL5_PICOPHY_ACAENB        BIT(4)
0025 #define CTRL5_PICOPHY_BC_MODE       BIT(5)
0026 #define CTRL5_PICOPHY_CHRGSEL       BIT(6)
0027 #define CTRL5_PICOPHY_VDATSRCEND    BIT(7)
0028 #define CTRL5_PICOPHY_VDATDETENB    BIT(8)
0029 #define CTRL5_PICOPHY_DCDENB        BIT(9)
0030 #define CTRL5_PICOPHY_IDDIG     BIT(10)
0031
0032 #define SC_PERIPH_CTRL8         0x018
0033 #define SC_PERIPH_RSTEN0        0x300
0034 #define SC_PERIPH_RSTDIS0       0x304
0035
0036 #define RST0_USBOTG_BUS         BIT(4)
0037 #define RST0_POR_PICOPHY        BIT(5)
0038 #define RST0_USBOTG         BIT(6)
0039 #define RST0_USBOTG_32K         BIT(7)
0040
0041 #define EYE_PATTERN_PARA        0x7053348c
0042
0043 struct hi6220_priv {
0044     struct regmap *reg;
0045     struct device *dev;
0046 };
0047
0048 static void hi6220_phy_init(struct hi6220_priv *priv)
0049 {
0050     struct regmap *reg = priv->reg;
0051     u32 val, mask;
0052
0053     val = RST0_USBOTG_BUS | RST0_POR_PICOPHY |
0054           RST0_USBOTG | RST0_USBOTG_32K;
0055     mask = val;
0056     regmap_update_bits(reg, SC_PERIPH_RSTEN0, mask, val);
0057     regmap_update_bits(reg, SC_PERIPH_RSTDIS0, mask, val);
0058 }
0059
0060 static int hi6220_phy_setup(struct hi6220_priv *priv, bool on)
0061 {
0062     struct regmap *reg = priv->reg;
0063     u32 val, mask;
0064     int ret;
0065
0066     if (on) {
0067         val = CTRL5_USBOTG_RES_SEL | CTRL5_PICOPHY_ACAENB;
0068         mask = val | CTRL5_PICOPHY_BC_MODE;
0069         ret = regmap_update_bits(reg, SC_PERIPH_CTRL5, mask, val);
0070         if (ret)
0071             goto out;
0072
0073         val =  CTRL4_PICO_VBUSVLDEXT | CTRL4_PICO_VBUSVLDEXTSEL |
0074                CTRL4_OTG_PHY_SEL;
0075         mask = val | CTRL4_PICO_SIDDQ | CTRL4_PICO_OGDISABLE;
0076         ret = regmap_update_bits(reg, SC_PERIPH_CTRL4, mask, val);
0077         if (ret)
0078             goto out;
0079
0080         ret = regmap_write(reg, SC_PERIPH_CTRL8, EYE_PATTERN_PARA);
0081         if (ret)
0082             goto out;
0083     } else {
0084         val = CTRL4_PICO_SIDDQ;
0085         mask = val;
0086         ret = regmap_update_bits(reg, SC_PERIPH_CTRL4, mask, val);
0087         if (ret)
0088             goto out;
0089     }
0090
0091     return 0;
0092 out:
0093     dev_err(priv->dev, "failed to setup phy ret: %d\n", ret);
0094     return ret;
0095 }
0096
0097 static int hi6220_phy_start(struct phy *phy)
0098 {
0099     struct hi6220_priv *priv = phy_get_drvdata(phy);
0100
0101     return hi6220_phy_setup(priv, true);
0102 }
0103
0104 static int hi6220_phy_exit(struct phy *phy)
0105 {
0106     struct hi6220_priv *priv = phy_get_drvdata(phy);
0107
0108     return hi6220_phy_setup(priv, false);
0109 }
0110
0111 static const struct phy_ops hi6220_phy_ops = {
0112     .init       = hi6220_phy_start,
0113     .exit       = hi6220_phy_exit,
0114     .owner      = THIS_MODULE,
0115 };
0116
0117 static int hi6220_phy_probe(struct platform_device *pdev)
0118 {
0119     struct phy_provider *phy_provider;
0120     struct device *dev = &pdev->dev;
0121     struct phy *phy;
0122     struct hi6220_priv *priv;
0123
0124     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0125     if (!priv)
0126         return -ENOMEM;
0127
0128     priv->dev = dev;
0129     priv->reg = syscon_regmap_lookup_by_phandle(dev->of_node,
0130                     "hisilicon,peripheral-syscon");
0131     if (IS_ERR(priv->reg)) {
0132         dev_err(dev, "no hisilicon,peripheral-syscon\n");
0133         return PTR_ERR(priv->reg);
0134     }
0135
0136     hi6220_phy_init(priv);
0137
0138     phy = devm_phy_create(dev, NULL, &hi6220_phy_ops);
0139     if (IS_ERR(phy))
0140         return PTR_ERR(phy);
0141
0142     phy_set_drvdata(phy, priv);
0143     phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0144     return PTR_ERR_OR_ZERO(phy_provider);
0145 }
0146
0147 static const struct of_device_id hi6220_phy_of_match[] = {
0148     {.compatible = "hisilicon,hi6220-usb-phy",},
0149     { },
0150 };
0151 MODULE_DEVICE_TABLE(of, hi6220_phy_of_match);
0152
0153 static struct platform_driver hi6220_phy_driver = {
0154     .probe  = hi6220_phy_probe,
0155     .driver = {
0156         .name   = "hi6220-usb-phy",
0157         .of_match_table = hi6220_phy_of_match,
0158     }
0159 };
0160 module_platform_driver(hi6220_phy_driver);
0161
0162 MODULE_DESCRIPTION("HISILICON HI6220 USB PHY driver");
0163 MODULE_ALIAS("platform:hi6220-usb-phy");
0164 MODULE_LICENSE("GPL");