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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright 2017,2018 NXP
0004  * Copyright 2019 Purism SPC
0005  */
0006 
0007 #include <linux/bitfield.h>
0008 #include <linux/clk.h>
0009 #include <linux/clk-provider.h>
0010 #include <linux/delay.h>
0011 #include <linux/firmware/imx/ipc.h>
0012 #include <linux/firmware/imx/svc/misc.h>
0013 #include <linux/io.h>
0014 #include <linux/kernel.h>
0015 #include <linux/mfd/syscon.h>
0016 #include <linux/module.h>
0017 #include <linux/of.h>
0018 #include <linux/of_platform.h>
0019 #include <linux/phy/phy.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/regmap.h>
0022 #include <dt-bindings/firmware/imx/rsrc.h>
0023 
0024 /* Control and Status Registers(CSR) */
0025 #define PHY_CTRL            0x00
0026 #define  CCM_MASK           GENMASK(7, 5)
0027 #define  CCM(n)             FIELD_PREP(CCM_MASK, (n))
0028 #define  CCM_1_2V           0x5
0029 #define  CA_MASK            GENMASK(4, 2)
0030 #define  CA_3_51MA          0x4
0031 #define  CA(n)              FIELD_PREP(CA_MASK, (n))
0032 #define  RFB                BIT(1)
0033 #define  LVDS_EN            BIT(0)
0034 
0035 /* DPHY registers */
0036 #define DPHY_PD_DPHY            0x00
0037 #define DPHY_M_PRG_HS_PREPARE       0x04
0038 #define DPHY_MC_PRG_HS_PREPARE      0x08
0039 #define DPHY_M_PRG_HS_ZERO      0x0c
0040 #define DPHY_MC_PRG_HS_ZERO     0x10
0041 #define DPHY_M_PRG_HS_TRAIL     0x14
0042 #define DPHY_MC_PRG_HS_TRAIL        0x18
0043 #define DPHY_PD_PLL         0x1c
0044 #define DPHY_TST            0x20
0045 #define DPHY_CN             0x24
0046 #define DPHY_CM             0x28
0047 #define DPHY_CO             0x2c
0048 #define DPHY_LOCK           0x30
0049 #define DPHY_LOCK_BYP           0x34
0050 #define DPHY_REG_BYPASS_PLL     0x4C
0051 
0052 #define MBPS(x) ((x) * 1000000)
0053 
0054 #define DATA_RATE_MAX_SPEED MBPS(1500)
0055 #define DATA_RATE_MIN_SPEED MBPS(80)
0056 
0057 #define PLL_LOCK_SLEEP 10
0058 #define PLL_LOCK_TIMEOUT 1000
0059 
0060 #define CN_BUF  0xcb7a89c0
0061 #define CO_BUF  0x63
0062 #define CM(x)   (                 \
0063         ((x) <  32) ? 0xe0 | ((x) - 16) : \
0064         ((x) <  64) ? 0xc0 | ((x) - 32) : \
0065         ((x) < 128) ? 0x80 | ((x) - 64) : \
0066         ((x) - 128))
0067 #define CN(x)   (((x) == 1) ? 0x1f : (((CN_BUF) >> ((x) - 1)) & 0x1f))
0068 #define CO(x)   ((CO_BUF) >> (8 - (x)) & 0x03)
0069 
0070 /* PHY power on is active low */
0071 #define PWR_ON  0
0072 #define PWR_OFF 1
0073 
0074 #define MIN_VCO_FREQ 640000000
0075 #define MAX_VCO_FREQ 1500000000
0076 
0077 #define MIN_LVDS_REFCLK_FREQ 24000000
0078 #define MAX_LVDS_REFCLK_FREQ 150000000
0079 
0080 enum mixel_dphy_devtype {
0081     MIXEL_IMX8MQ,
0082     MIXEL_IMX8QXP,
0083 };
0084 
0085 struct mixel_dphy_devdata {
0086     u8 reg_tx_rcal;
0087     u8 reg_auto_pd_en;
0088     u8 reg_rxlprp;
0089     u8 reg_rxcdrp;
0090     u8 reg_rxhs_settle;
0091     bool is_combo;  /* MIPI DPHY and LVDS PHY combo */
0092 };
0093 
0094 static const struct mixel_dphy_devdata mixel_dphy_devdata[] = {
0095     [MIXEL_IMX8MQ] = {
0096         .reg_tx_rcal = 0x38,
0097         .reg_auto_pd_en = 0x3c,
0098         .reg_rxlprp = 0x40,
0099         .reg_rxcdrp = 0x44,
0100         .reg_rxhs_settle = 0x48,
0101         .is_combo = false,
0102     },
0103     [MIXEL_IMX8QXP] = {
0104         .is_combo = true,
0105     },
0106 };
0107 
0108 struct mixel_dphy_cfg {
0109     /* DPHY PLL parameters */
0110     u32 cm;
0111     u32 cn;
0112     u32 co;
0113     /* DPHY register values */
0114     u8 mc_prg_hs_prepare;
0115     u8 m_prg_hs_prepare;
0116     u8 mc_prg_hs_zero;
0117     u8 m_prg_hs_zero;
0118     u8 mc_prg_hs_trail;
0119     u8 m_prg_hs_trail;
0120     u8 rxhs_settle;
0121 };
0122 
0123 struct mixel_dphy_priv {
0124     struct mixel_dphy_cfg cfg;
0125     struct regmap *regmap;
0126     struct regmap *lvds_regmap;
0127     struct clk *phy_ref_clk;
0128     const struct mixel_dphy_devdata *devdata;
0129     struct imx_sc_ipc *ipc_handle;
0130     bool is_slave;
0131     int id;
0132 };
0133 
0134 static const struct regmap_config mixel_dphy_regmap_config = {
0135     .reg_bits = 8,
0136     .val_bits = 32,
0137     .reg_stride = 4,
0138     .max_register = DPHY_REG_BYPASS_PLL,
0139     .name = "mipi-dphy",
0140 };
0141 
0142 static int phy_write(struct phy *phy, u32 value, unsigned int reg)
0143 {
0144     struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
0145     int ret;
0146 
0147     ret = regmap_write(priv->regmap, reg, value);
0148     if (ret < 0)
0149         dev_err(&phy->dev, "Failed to write DPHY reg %d: %d\n", reg,
0150             ret);
0151     return ret;
0152 }
0153 
0154 /*
0155  * Find a ratio close to the desired one using continued fraction
0156  * approximation ending either at exact match or maximum allowed
0157  * nominator, denominator.
0158  */
0159 static void get_best_ratio(u32 *pnum, u32 *pdenom, u32 max_n, u32 max_d)
0160 {
0161     u32 a = *pnum;
0162     u32 b = *pdenom;
0163     u32 c;
0164     u32 n[] = {0, 1};
0165     u32 d[] = {1, 0};
0166     u32 whole;
0167     unsigned int i = 1;
0168 
0169     while (b) {
0170         i ^= 1;
0171         whole = a / b;
0172         n[i] += (n[i ^ 1] * whole);
0173         d[i] += (d[i ^ 1] * whole);
0174         if ((n[i] > max_n) || (d[i] > max_d)) {
0175             i ^= 1;
0176             break;
0177         }
0178         c = a - (b * whole);
0179         a = b;
0180         b = c;
0181     }
0182     *pnum = n[i];
0183     *pdenom = d[i];
0184 }
0185 
0186 static int mixel_dphy_config_from_opts(struct phy *phy,
0187            struct phy_configure_opts_mipi_dphy *dphy_opts,
0188            struct mixel_dphy_cfg *cfg)
0189 {
0190     struct mixel_dphy_priv *priv = dev_get_drvdata(phy->dev.parent);
0191     unsigned long ref_clk = clk_get_rate(priv->phy_ref_clk);
0192     u32 lp_t, numerator, denominator;
0193     unsigned long long tmp;
0194     u32 n;
0195     int i;
0196 
0197     if (dphy_opts->hs_clk_rate > DATA_RATE_MAX_SPEED ||
0198         dphy_opts->hs_clk_rate < DATA_RATE_MIN_SPEED)
0199         return -EINVAL;
0200 
0201     numerator = dphy_opts->hs_clk_rate;
0202     denominator = ref_clk;
0203     get_best_ratio(&numerator, &denominator, 255, 256);
0204     if (!numerator || !denominator) {
0205         dev_err(&phy->dev, "Invalid %d/%d for %ld/%ld\n",
0206             numerator, denominator,
0207             dphy_opts->hs_clk_rate, ref_clk);
0208         return -EINVAL;
0209     }
0210 
0211     while ((numerator < 16) && (denominator <= 128)) {
0212         numerator <<= 1;
0213         denominator <<= 1;
0214     }
0215     /*
0216      * CM ranges between 16 and 255
0217      * CN ranges between 1 and 32
0218      * CO is power of 2: 1, 2, 4, 8
0219      */
0220     i = __ffs(denominator);
0221     if (i > 3)
0222         i = 3;
0223     cfg->cn = denominator >> i;
0224     cfg->co = 1 << i;
0225     cfg->cm = numerator;
0226 
0227     if (cfg->cm < 16 || cfg->cm > 255 ||
0228         cfg->cn < 1 || cfg->cn > 32 ||
0229         cfg->co < 1 || cfg->co > 8) {
0230         dev_err(&phy->dev, "Invalid CM/CN/CO values: %u/%u/%u\n",
0231             cfg->cm, cfg->cn, cfg->co);
0232         dev_err(&phy->dev, "for hs_clk/ref_clk=%ld/%ld ~ %d/%d\n",
0233             dphy_opts->hs_clk_rate, ref_clk,
0234             numerator, denominator);
0235         return -EINVAL;
0236     }
0237 
0238     dev_dbg(&phy->dev, "hs_clk/ref_clk=%ld/%ld ~ %d/%d\n",
0239         dphy_opts->hs_clk_rate, ref_clk, numerator, denominator);
0240 
0241     /* LP clock period */
0242     tmp = 1000000000000LL;
0243     do_div(tmp, dphy_opts->lp_clk_rate); /* ps */
0244     if (tmp > ULONG_MAX)
0245         return -EINVAL;
0246 
0247     lp_t = tmp;
0248     dev_dbg(&phy->dev, "LP clock %lu, period: %u ps\n",
0249         dphy_opts->lp_clk_rate, lp_t);
0250 
0251     /* hs_prepare: in lp clock periods */
0252     if (2 * dphy_opts->hs_prepare > 5 * lp_t) {
0253         dev_err(&phy->dev,
0254             "hs_prepare (%u) > 2.5 * lp clock period (%u)\n",
0255             dphy_opts->hs_prepare, lp_t);
0256         return -EINVAL;
0257     }
0258     /* 00: lp_t, 01: 1.5 * lp_t, 10: 2 * lp_t, 11: 2.5 * lp_t */
0259     if (dphy_opts->hs_prepare < lp_t) {
0260         n = 0;
0261     } else {
0262         tmp = 2 * (dphy_opts->hs_prepare - lp_t);
0263         do_div(tmp, lp_t);
0264         n = tmp;
0265     }
0266     cfg->m_prg_hs_prepare = n;
0267 
0268     /* clk_prepare: in lp clock periods */
0269     if (2 * dphy_opts->clk_prepare > 3 * lp_t) {
0270         dev_err(&phy->dev,
0271             "clk_prepare (%u) > 1.5 * lp clock period (%u)\n",
0272             dphy_opts->clk_prepare, lp_t);
0273         return -EINVAL;
0274     }
0275     /* 00: lp_t, 01: 1.5 * lp_t */
0276     cfg->mc_prg_hs_prepare = dphy_opts->clk_prepare > lp_t ? 1 : 0;
0277 
0278     /* hs_zero: formula from NXP BSP */
0279     n = (144 * (dphy_opts->hs_clk_rate / 1000000) - 47500) / 10000;
0280     cfg->m_prg_hs_zero = n < 1 ? 1 : n;
0281 
0282     /* clk_zero: formula from NXP BSP */
0283     n = (34 * (dphy_opts->hs_clk_rate / 1000000) - 2500) / 1000;
0284     cfg->mc_prg_hs_zero = n < 1 ? 1 : n;
0285 
0286     /* clk_trail, hs_trail: formula from NXP BSP */
0287     n = (103 * (dphy_opts->hs_clk_rate / 1000000) + 10000) / 10000;
0288     if (n > 15)
0289         n = 15;
0290     if (n < 1)
0291         n = 1;
0292     cfg->m_prg_hs_trail = n;
0293     cfg->mc_prg_hs_trail = n;
0294 
0295     /* rxhs_settle: formula from NXP BSP */
0296     if (dphy_opts->hs_clk_rate < MBPS(80))
0297         cfg->rxhs_settle = 0x0d;
0298     else if (dphy_opts->hs_clk_rate < MBPS(90))
0299         cfg->rxhs_settle = 0x0c;
0300     else if (dphy_opts->hs_clk_rate < MBPS(125))
0301         cfg->rxhs_settle = 0x0b;
0302     else if (dphy_opts->hs_clk_rate < MBPS(150))
0303         cfg->rxhs_settle = 0x0a;
0304     else if (dphy_opts->hs_clk_rate < MBPS(225))
0305         cfg->rxhs_settle = 0x09;
0306     else if (dphy_opts->hs_clk_rate < MBPS(500))
0307         cfg->rxhs_settle = 0x08;
0308     else
0309         cfg->rxhs_settle = 0x07;
0310 
0311     dev_dbg(&phy->dev, "phy_config: %u %u %u %u %u %u %u\n",
0312         cfg->m_prg_hs_prepare, cfg->mc_prg_hs_prepare,
0313         cfg->m_prg_hs_zero, cfg->mc_prg_hs_zero,
0314         cfg->m_prg_hs_trail, cfg->mc_prg_hs_trail,
0315         cfg->rxhs_settle);
0316 
0317     return 0;
0318 }
0319 
0320 static void mixel_phy_set_hs_timings(struct phy *phy)
0321 {
0322     struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
0323 
0324     phy_write(phy, priv->cfg.m_prg_hs_prepare, DPHY_M_PRG_HS_PREPARE);
0325     phy_write(phy, priv->cfg.mc_prg_hs_prepare, DPHY_MC_PRG_HS_PREPARE);
0326     phy_write(phy, priv->cfg.m_prg_hs_zero, DPHY_M_PRG_HS_ZERO);
0327     phy_write(phy, priv->cfg.mc_prg_hs_zero, DPHY_MC_PRG_HS_ZERO);
0328     phy_write(phy, priv->cfg.m_prg_hs_trail, DPHY_M_PRG_HS_TRAIL);
0329     phy_write(phy, priv->cfg.mc_prg_hs_trail, DPHY_MC_PRG_HS_TRAIL);
0330     phy_write(phy, priv->cfg.rxhs_settle, priv->devdata->reg_rxhs_settle);
0331 }
0332 
0333 static int mixel_dphy_set_pll_params(struct phy *phy)
0334 {
0335     struct mixel_dphy_priv *priv = dev_get_drvdata(phy->dev.parent);
0336 
0337     if (priv->cfg.cm < 16 || priv->cfg.cm > 255 ||
0338         priv->cfg.cn < 1 || priv->cfg.cn > 32 ||
0339         priv->cfg.co < 1 || priv->cfg.co > 8) {
0340         dev_err(&phy->dev, "Invalid CM/CN/CO values! (%u/%u/%u)\n",
0341             priv->cfg.cm, priv->cfg.cn, priv->cfg.co);
0342         return -EINVAL;
0343     }
0344     dev_dbg(&phy->dev, "Using CM:%u CN:%u CO:%u\n",
0345         priv->cfg.cm, priv->cfg.cn, priv->cfg.co);
0346     phy_write(phy, CM(priv->cfg.cm), DPHY_CM);
0347     phy_write(phy, CN(priv->cfg.cn), DPHY_CN);
0348     phy_write(phy, CO(priv->cfg.co), DPHY_CO);
0349     return 0;
0350 }
0351 
0352 static int
0353 mixel_dphy_configure_mipi_dphy(struct phy *phy, union phy_configure_opts *opts)
0354 {
0355     struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
0356     struct mixel_dphy_cfg cfg = { 0 };
0357     int ret;
0358 
0359     ret = mixel_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg);
0360     if (ret)
0361         return ret;
0362 
0363     /* Update the configuration */
0364     memcpy(&priv->cfg, &cfg, sizeof(struct mixel_dphy_cfg));
0365 
0366     phy_write(phy, 0x00, DPHY_LOCK_BYP);
0367     phy_write(phy, 0x01, priv->devdata->reg_tx_rcal);
0368     phy_write(phy, 0x00, priv->devdata->reg_auto_pd_en);
0369     phy_write(phy, 0x02, priv->devdata->reg_rxlprp);
0370     phy_write(phy, 0x02, priv->devdata->reg_rxcdrp);
0371     phy_write(phy, 0x25, DPHY_TST);
0372 
0373     mixel_phy_set_hs_timings(phy);
0374     ret = mixel_dphy_set_pll_params(phy);
0375     if (ret < 0)
0376         return ret;
0377 
0378     return 0;
0379 }
0380 
0381 static int
0382 mixel_dphy_configure_lvds_phy(struct phy *phy, union phy_configure_opts *opts)
0383 {
0384     struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
0385     struct phy_configure_opts_lvds *lvds_opts = &opts->lvds;
0386     unsigned long data_rate;
0387     unsigned long fvco;
0388     u32 rsc;
0389     u32 co;
0390     int ret;
0391 
0392     priv->is_slave = lvds_opts->is_slave;
0393 
0394     /* LVDS interface pins */
0395     regmap_write(priv->lvds_regmap, PHY_CTRL,
0396              CCM(CCM_1_2V) | CA(CA_3_51MA) | RFB);
0397 
0398     /* enable MODE8 only for slave LVDS PHY */
0399     rsc = priv->id ? IMX_SC_R_MIPI_1 : IMX_SC_R_MIPI_0;
0400     ret = imx_sc_misc_set_control(priv->ipc_handle, rsc, IMX_SC_C_DUAL_MODE,
0401                       lvds_opts->is_slave);
0402     if (ret) {
0403         dev_err(&phy->dev, "Failed to configure MODE8: %d\n", ret);
0404         return ret;
0405     }
0406 
0407     /*
0408      * Choose an appropriate divider ratio to meet the requirement of
0409      * PLL VCO frequency range.
0410      *
0411      *  -----  640MHz ~ 1500MHz   ------------      ---------------
0412      * | VCO | ----------------> | CO divider | -> | LVDS data rate|
0413      *  -----       FVCO          ------------      ---------------
0414      *                            1/2/4/8 div     7 * differential_clk_rate
0415      */
0416     data_rate = 7 * lvds_opts->differential_clk_rate;
0417     for (co = 1; co <= 8; co *= 2) {
0418         fvco = data_rate * co;
0419 
0420         if (fvco >= MIN_VCO_FREQ)
0421             break;
0422     }
0423 
0424     if (fvco < MIN_VCO_FREQ || fvco > MAX_VCO_FREQ) {
0425         dev_err(&phy->dev, "VCO frequency %lu is out of range\n", fvco);
0426         return -ERANGE;
0427     }
0428 
0429     /*
0430      * CO is configurable, while CN and CM are not,
0431      * as fixed ratios 1 and 7 are applied respectively.
0432      */
0433     phy_write(phy, __ffs(co), DPHY_CO);
0434 
0435     /* set reference clock rate */
0436     clk_set_rate(priv->phy_ref_clk, lvds_opts->differential_clk_rate);
0437 
0438     return ret;
0439 }
0440 
0441 static int mixel_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
0442 {
0443     if (!opts) {
0444         dev_err(&phy->dev, "No configuration options\n");
0445         return -EINVAL;
0446     }
0447 
0448     if (phy->attrs.mode == PHY_MODE_MIPI_DPHY)
0449         return mixel_dphy_configure_mipi_dphy(phy, opts);
0450     else if (phy->attrs.mode == PHY_MODE_LVDS)
0451         return mixel_dphy_configure_lvds_phy(phy, opts);
0452 
0453     dev_err(&phy->dev,
0454         "Failed to configure PHY with invalid PHY mode: %d\n", phy->attrs.mode);
0455 
0456     return -EINVAL;
0457 }
0458 
0459 static int
0460 mixel_dphy_validate_lvds_phy(struct phy *phy, union phy_configure_opts *opts)
0461 {
0462     struct phy_configure_opts_lvds *lvds_cfg = &opts->lvds;
0463 
0464     if (lvds_cfg->bits_per_lane_and_dclk_cycle != 7) {
0465         dev_err(&phy->dev, "Invalid bits per LVDS data lane: %u\n",
0466             lvds_cfg->bits_per_lane_and_dclk_cycle);
0467         return -EINVAL;
0468     }
0469 
0470     if (lvds_cfg->lanes != 4) {
0471         dev_err(&phy->dev, "Invalid LVDS data lanes: %u\n", lvds_cfg->lanes);
0472         return -EINVAL;
0473     }
0474 
0475     if (lvds_cfg->differential_clk_rate < MIN_LVDS_REFCLK_FREQ ||
0476         lvds_cfg->differential_clk_rate > MAX_LVDS_REFCLK_FREQ) {
0477         dev_err(&phy->dev,
0478             "Invalid LVDS differential clock rate: %lu\n",
0479             lvds_cfg->differential_clk_rate);
0480         return -EINVAL;
0481     }
0482 
0483     return 0;
0484 }
0485 
0486 static int mixel_dphy_validate(struct phy *phy, enum phy_mode mode, int submode,
0487                    union phy_configure_opts *opts)
0488 {
0489     if (mode == PHY_MODE_MIPI_DPHY) {
0490         struct mixel_dphy_cfg mipi_dphy_cfg = { 0 };
0491 
0492         return mixel_dphy_config_from_opts(phy, &opts->mipi_dphy,
0493                            &mipi_dphy_cfg);
0494     } else if (mode == PHY_MODE_LVDS) {
0495         return mixel_dphy_validate_lvds_phy(phy, opts);
0496     }
0497 
0498     dev_err(&phy->dev,
0499         "Failed to validate PHY with invalid PHY mode: %d\n", mode);
0500     return -EINVAL;
0501 }
0502 
0503 static int mixel_dphy_init(struct phy *phy)
0504 {
0505     phy_write(phy, PWR_OFF, DPHY_PD_PLL);
0506     phy_write(phy, PWR_OFF, DPHY_PD_DPHY);
0507 
0508     return 0;
0509 }
0510 
0511 static int mixel_dphy_exit(struct phy *phy)
0512 {
0513     phy_write(phy, 0, DPHY_CM);
0514     phy_write(phy, 0, DPHY_CN);
0515     phy_write(phy, 0, DPHY_CO);
0516 
0517     return 0;
0518 }
0519 
0520 static int mixel_dphy_power_on_mipi_dphy(struct phy *phy)
0521 {
0522     struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
0523     u32 locked;
0524     int ret;
0525 
0526     phy_write(phy, PWR_ON, DPHY_PD_PLL);
0527     ret = regmap_read_poll_timeout(priv->regmap, DPHY_LOCK, locked,
0528                        locked, PLL_LOCK_SLEEP,
0529                        PLL_LOCK_TIMEOUT);
0530     if (ret < 0) {
0531         dev_err(&phy->dev, "Could not get DPHY lock (%d)!\n", ret);
0532         return ret;
0533     }
0534     phy_write(phy, PWR_ON, DPHY_PD_DPHY);
0535 
0536     return 0;
0537 }
0538 
0539 static int mixel_dphy_power_on_lvds_phy(struct phy *phy)
0540 {
0541     struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
0542     u32 locked;
0543     int ret;
0544 
0545     regmap_update_bits(priv->lvds_regmap, PHY_CTRL, LVDS_EN, LVDS_EN);
0546 
0547     phy_write(phy, PWR_ON, DPHY_PD_DPHY);
0548     phy_write(phy, PWR_ON, DPHY_PD_PLL);
0549 
0550     /* do not wait for slave LVDS PHY being locked */
0551     if (priv->is_slave)
0552         return 0;
0553 
0554     ret = regmap_read_poll_timeout(priv->regmap, DPHY_LOCK, locked,
0555                        locked, PLL_LOCK_SLEEP,
0556                        PLL_LOCK_TIMEOUT);
0557     if (ret < 0) {
0558         dev_err(&phy->dev, "Could not get LVDS PHY lock (%d)!\n", ret);
0559         return ret;
0560     }
0561 
0562     return 0;
0563 }
0564 
0565 static int mixel_dphy_power_on(struct phy *phy)
0566 {
0567     struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
0568     int ret;
0569 
0570     ret = clk_prepare_enable(priv->phy_ref_clk);
0571     if (ret < 0)
0572         return ret;
0573 
0574     if (phy->attrs.mode == PHY_MODE_MIPI_DPHY) {
0575         ret = mixel_dphy_power_on_mipi_dphy(phy);
0576     } else if (phy->attrs.mode == PHY_MODE_LVDS) {
0577         ret = mixel_dphy_power_on_lvds_phy(phy);
0578     } else {
0579         dev_err(&phy->dev,
0580             "Failed to power on PHY with invalid PHY mode: %d\n",
0581                             phy->attrs.mode);
0582         ret = -EINVAL;
0583     }
0584 
0585     if (ret)
0586         goto clock_disable;
0587 
0588     return 0;
0589 clock_disable:
0590     clk_disable_unprepare(priv->phy_ref_clk);
0591     return ret;
0592 }
0593 
0594 static int mixel_dphy_power_off(struct phy *phy)
0595 {
0596     struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
0597 
0598     phy_write(phy, PWR_OFF, DPHY_PD_PLL);
0599     phy_write(phy, PWR_OFF, DPHY_PD_DPHY);
0600 
0601     if (phy->attrs.mode == PHY_MODE_LVDS)
0602         regmap_update_bits(priv->lvds_regmap, PHY_CTRL, LVDS_EN, 0);
0603 
0604     clk_disable_unprepare(priv->phy_ref_clk);
0605 
0606     return 0;
0607 }
0608 
0609 static int mixel_dphy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
0610 {
0611     struct mixel_dphy_priv *priv = phy_get_drvdata(phy);
0612     int ret;
0613 
0614     if (priv->devdata->is_combo && mode != PHY_MODE_LVDS) {
0615         dev_err(&phy->dev, "Failed to set PHY mode for combo PHY\n");
0616         return -EINVAL;
0617     }
0618 
0619     if (!priv->devdata->is_combo && mode != PHY_MODE_MIPI_DPHY) {
0620         dev_err(&phy->dev, "Failed to set PHY mode to MIPI DPHY\n");
0621         return -EINVAL;
0622     }
0623 
0624     if (priv->devdata->is_combo) {
0625         u32 rsc = priv->id ? IMX_SC_R_MIPI_1 : IMX_SC_R_MIPI_0;
0626 
0627         ret = imx_sc_misc_set_control(priv->ipc_handle,
0628                           rsc, IMX_SC_C_MODE,
0629                           mode == PHY_MODE_LVDS);
0630         if (ret) {
0631             dev_err(&phy->dev,
0632                 "Failed to set PHY mode via SCU ipc: %d\n", ret);
0633             return ret;
0634         }
0635     }
0636 
0637     return 0;
0638 }
0639 
0640 static const struct phy_ops mixel_dphy_phy_ops = {
0641     .init = mixel_dphy_init,
0642     .exit = mixel_dphy_exit,
0643     .power_on = mixel_dphy_power_on,
0644     .power_off = mixel_dphy_power_off,
0645     .set_mode = mixel_dphy_set_mode,
0646     .configure = mixel_dphy_configure,
0647     .validate = mixel_dphy_validate,
0648     .owner = THIS_MODULE,
0649 };
0650 
0651 static const struct of_device_id mixel_dphy_of_match[] = {
0652     { .compatible = "fsl,imx8mq-mipi-dphy",
0653       .data = &mixel_dphy_devdata[MIXEL_IMX8MQ] },
0654     { .compatible = "fsl,imx8qxp-mipi-dphy",
0655       .data = &mixel_dphy_devdata[MIXEL_IMX8QXP] },
0656     { /* sentinel */ },
0657 };
0658 MODULE_DEVICE_TABLE(of, mixel_dphy_of_match);
0659 
0660 static int mixel_dphy_probe(struct platform_device *pdev)
0661 {
0662     struct device *dev = &pdev->dev;
0663     struct device_node *np = dev->of_node;
0664     struct phy_provider *phy_provider;
0665     struct mixel_dphy_priv *priv;
0666     struct phy *phy;
0667     void __iomem *base;
0668     int ret;
0669 
0670     if (!np)
0671         return -ENODEV;
0672 
0673     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0674     if (!priv)
0675         return -ENOMEM;
0676 
0677     priv->devdata = of_device_get_match_data(&pdev->dev);
0678     if (!priv->devdata)
0679         return -EINVAL;
0680 
0681     base = devm_platform_ioremap_resource(pdev, 0);
0682     if (IS_ERR(base))
0683         return PTR_ERR(base);
0684 
0685     priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
0686                          &mixel_dphy_regmap_config);
0687     if (IS_ERR(priv->regmap)) {
0688         dev_err(dev, "Couldn't create the DPHY regmap\n");
0689         return PTR_ERR(priv->regmap);
0690     }
0691 
0692     priv->phy_ref_clk = devm_clk_get(&pdev->dev, "phy_ref");
0693     if (IS_ERR(priv->phy_ref_clk)) {
0694         dev_err(dev, "No phy_ref clock found\n");
0695         return PTR_ERR(priv->phy_ref_clk);
0696     }
0697     dev_dbg(dev, "phy_ref clock rate: %lu\n",
0698         clk_get_rate(priv->phy_ref_clk));
0699 
0700     if (priv->devdata->is_combo) {
0701         priv->lvds_regmap =
0702             syscon_regmap_lookup_by_phandle(np, "fsl,syscon");
0703         if (IS_ERR(priv->lvds_regmap)) {
0704             ret = PTR_ERR(priv->lvds_regmap);
0705             dev_err_probe(dev, ret, "Failed to get LVDS regmap\n");
0706             return ret;
0707         }
0708 
0709         priv->id = of_alias_get_id(np, "mipi_dphy");
0710         if (priv->id < 0) {
0711             dev_err(dev, "Failed to get phy node alias id: %d\n",
0712                 priv->id);
0713             return priv->id;
0714         }
0715 
0716         ret = imx_scu_get_handle(&priv->ipc_handle);
0717         if (ret) {
0718             dev_err_probe(dev, ret,
0719                       "Failed to get SCU ipc handle\n");
0720             return ret;
0721         }
0722     }
0723 
0724     dev_set_drvdata(dev, priv);
0725 
0726     phy = devm_phy_create(dev, np, &mixel_dphy_phy_ops);
0727     if (IS_ERR(phy)) {
0728         dev_err(dev, "Failed to create phy %ld\n", PTR_ERR(phy));
0729         return PTR_ERR(phy);
0730     }
0731     phy_set_drvdata(phy, priv);
0732 
0733     phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0734 
0735     return PTR_ERR_OR_ZERO(phy_provider);
0736 }
0737 
0738 static struct platform_driver mixel_dphy_driver = {
0739     .probe  = mixel_dphy_probe,
0740     .driver = {
0741         .name = "mixel-mipi-dphy",
0742         .of_match_table = mixel_dphy_of_match,
0743     }
0744 };
0745 module_platform_driver(mixel_dphy_driver);
0746 
0747 MODULE_AUTHOR("NXP Semiconductor");
0748 MODULE_DESCRIPTION("Mixel MIPI-DSI PHY driver");
0749 MODULE_LICENSE("GPL");
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