phy/cadence/phy-cadence-salvo.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Salvo PHY is a 28nm PHY, it is a legacy PHY, and only
0004  * for USB3 and USB2.
0005  *
0006  * Copyright (c) 2019-2020 NXP
0007  */
0008
0009 #include <linux/clk.h>
0010 #include <linux/io.h>
0011 #include <linux/module.h>
0012 #include <linux/phy/phy.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/delay.h>
0015 #include <linux/of.h>
0016 #include <linux/of_platform.h>
0017
0018 /* PHY register definition */
0019 #define PHY_PMA_CMN_CTRL1           0xC800
0020 #define TB_ADDR_CMN_DIAG_HSCLK_SEL      0x01e0
0021 #define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR    0x0084
0022 #define TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR    0x0085
0023 #define TB_ADDR_CMN_PLL0_INTDIV                 0x0094
0024 #define TB_ADDR_CMN_PLL0_FRACDIV        0x0095
0025 #define TB_ADDR_CMN_PLL0_HIGH_THR       0x0096
0026 #define TB_ADDR_CMN_PLL0_SS_CTRL1       0x0098
0027 #define TB_ADDR_CMN_PLL0_SS_CTRL2       0x0099
0028 #define TB_ADDR_CMN_PLL0_DSM_DIAG       0x0097
0029 #define TB_ADDR_CMN_DIAG_PLL0_OVRD      0x01c2
0030 #define TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD      0x01c0
0031 #define TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD      0x01c1
0032 #define TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE          0x01C5
0033 #define TB_ADDR_CMN_DIAG_PLL0_CP_TUNE           0x01C6
0034 #define TB_ADDR_CMN_DIAG_PLL0_LF_PROG           0x01C7
0035 #define TB_ADDR_CMN_DIAG_PLL0_TEST_MODE     0x01c4
0036 #define TB_ADDR_CMN_PSM_CLK_CTRL        0x0061
0037 #define TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR   0x40ea
0038 #define TB_ADDR_XCVR_PSM_RCTRL                  0x4001
0039 #define TB_ADDR_TX_PSC_A0               0x4100
0040 #define TB_ADDR_TX_PSC_A1               0x4101
0041 #define TB_ADDR_TX_PSC_A2               0x4102
0042 #define TB_ADDR_TX_PSC_A3               0x4103
0043 #define TB_ADDR_TX_DIAG_ECTRL_OVRD      0x41f5
0044 #define TB_ADDR_TX_PSC_CAL              0x4106
0045 #define TB_ADDR_TX_PSC_RDY              0x4107
0046 #define TB_ADDR_RX_PSC_A0                   0x8000
0047 #define TB_ADDR_RX_PSC_A1                   0x8001
0048 #define TB_ADDR_RX_PSC_A2                   0x8002
0049 #define TB_ADDR_RX_PSC_A3                   0x8003
0050 #define TB_ADDR_RX_PSC_CAL                  0x8006
0051 #define TB_ADDR_RX_PSC_RDY                  0x8007
0052 #define TB_ADDR_TX_TXCC_MGNLS_MULT_000      0x4058
0053 #define TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY  0x41e7
0054 #define TB_ADDR_RX_SLC_CU_ITER_TMR      0x80e3
0055 #define TB_ADDR_RX_SIGDET_HL_FILT_TMR       0x8090
0056 #define TB_ADDR_RX_SAMP_DAC_CTRL        0x8058
0057 #define TB_ADDR_RX_DIAG_SIGDET_TUNE     0x81dc
0058 #define TB_ADDR_RX_DIAG_LFPSDET_TUNE2       0x81df
0059 #define TB_ADDR_RX_DIAG_BS_TM                   0x81f5
0060 #define TB_ADDR_RX_DIAG_DFE_CTRL1       0x81d3
0061 #define TB_ADDR_RX_DIAG_ILL_IQE_TRIM4       0x81c7
0062 #define TB_ADDR_RX_DIAG_ILL_E_TRIM0     0x81c2
0063 #define TB_ADDR_RX_DIAG_ILL_IQ_TRIM0        0x81c1
0064 #define TB_ADDR_RX_DIAG_ILL_IQE_TRIM6       0x81c9
0065 #define TB_ADDR_RX_DIAG_RXFE_TM3        0x81f8
0066 #define TB_ADDR_RX_DIAG_RXFE_TM4        0x81f9
0067 #define TB_ADDR_RX_DIAG_LFPSDET_TUNE        0x81dd
0068 #define TB_ADDR_RX_DIAG_DFE_CTRL3       0x81d5
0069 #define TB_ADDR_RX_DIAG_SC2C_DELAY      0x81e1
0070 #define TB_ADDR_RX_REE_VGA_GAIN_NODFE       0x81bf
0071 #define TB_ADDR_XCVR_PSM_CAL_TMR        0x4002
0072 #define TB_ADDR_XCVR_PSM_A0BYP_TMR      0x4004
0073 #define TB_ADDR_XCVR_PSM_A0IN_TMR       0x4003
0074 #define TB_ADDR_XCVR_PSM_A1IN_TMR       0x4005
0075 #define TB_ADDR_XCVR_PSM_A2IN_TMR       0x4006
0076 #define TB_ADDR_XCVR_PSM_A3IN_TMR       0x4007
0077 #define TB_ADDR_XCVR_PSM_A4IN_TMR       0x4008
0078 #define TB_ADDR_XCVR_PSM_A5IN_TMR       0x4009
0079 #define TB_ADDR_XCVR_PSM_A0OUT_TMR      0x400a
0080 #define TB_ADDR_XCVR_PSM_A1OUT_TMR      0x400b
0081 #define TB_ADDR_XCVR_PSM_A2OUT_TMR      0x400c
0082 #define TB_ADDR_XCVR_PSM_A3OUT_TMR      0x400d
0083 #define TB_ADDR_XCVR_PSM_A4OUT_TMR      0x400e
0084 #define TB_ADDR_XCVR_PSM_A5OUT_TMR      0x400f
0085 #define TB_ADDR_TX_RCVDET_EN_TMR            0x4122
0086 #define TB_ADDR_TX_RCVDET_ST_TMR            0x4123
0087 #define TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR   0x40f2
0088 #define TB_ADDR_TX_RCVDETSC_CTRL            0x4124
0089
0090 /* TB_ADDR_TX_RCVDETSC_CTRL */
0091 #define RXDET_IN_P3_32KHZ           BIT(0)
0092
0093 struct cdns_reg_pairs {
0094     u16 val;
0095     u32 off;
0096 };
0097
0098 struct cdns_salvo_data {
0099     u8 reg_offset_shift;
0100     const struct cdns_reg_pairs *init_sequence_val;
0101     u8 init_sequence_length;
0102 };
0103
0104 struct cdns_salvo_phy {
0105     struct phy *phy;
0106     struct clk *clk;
0107     void __iomem *base;
0108     struct cdns_salvo_data *data;
0109 };
0110
0111 static const struct of_device_id cdns_salvo_phy_of_match[];
0112 static u16 cdns_salvo_read(struct cdns_salvo_phy *salvo_phy, u32 reg)
0113 {
0114     return (u16)readl(salvo_phy->base +
0115         reg * (1 << salvo_phy->data->reg_offset_shift));
0116 }
0117
0118 static void cdns_salvo_write(struct cdns_salvo_phy *salvo_phy,
0119                  u32 reg, u16 val)
0120 {
0121     writel(val, salvo_phy->base +
0122         reg * (1 << salvo_phy->data->reg_offset_shift));
0123 }
0124
0125 /*
0126  * Below bringup sequence pair are from Cadence PHY's User Guide
0127  * and NXP platform tuning results.
0128  */
0129 static const struct cdns_reg_pairs cdns_nxp_sequence_pair[] = {
0130     {0x0830, PHY_PMA_CMN_CTRL1},
0131     {0x0010, TB_ADDR_CMN_DIAG_HSCLK_SEL},
0132     {0x00f0, TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR},
0133     {0x0018, TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR},
0134     {0x00d0, TB_ADDR_CMN_PLL0_INTDIV},
0135     {0x4aaa, TB_ADDR_CMN_PLL0_FRACDIV},
0136     {0x0034, TB_ADDR_CMN_PLL0_HIGH_THR},
0137     {0x01ee, TB_ADDR_CMN_PLL0_SS_CTRL1},
0138     {0x7f03, TB_ADDR_CMN_PLL0_SS_CTRL2},
0139     {0x0020, TB_ADDR_CMN_PLL0_DSM_DIAG},
0140     {0x0000, TB_ADDR_CMN_DIAG_PLL0_OVRD},
0141     {0x0000, TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD},
0142     {0x0000, TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD},
0143     {0x0007, TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE},
0144     {0x0027, TB_ADDR_CMN_DIAG_PLL0_CP_TUNE},
0145     {0x0008, TB_ADDR_CMN_DIAG_PLL0_LF_PROG},
0146     {0x0022, TB_ADDR_CMN_DIAG_PLL0_TEST_MODE},
0147     {0x000a, TB_ADDR_CMN_PSM_CLK_CTRL},
0148     {0x0139, TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR},
0149     {0xbefc, TB_ADDR_XCVR_PSM_RCTRL},
0150
0151     {0x7799, TB_ADDR_TX_PSC_A0},
0152     {0x7798, TB_ADDR_TX_PSC_A1},
0153     {0x509b, TB_ADDR_TX_PSC_A2},
0154     {0x0003, TB_ADDR_TX_DIAG_ECTRL_OVRD},
0155     {0x509b, TB_ADDR_TX_PSC_A3},
0156     {0x2090, TB_ADDR_TX_PSC_CAL},
0157     {0x2090, TB_ADDR_TX_PSC_RDY},
0158
0159     {0xA6FD, TB_ADDR_RX_PSC_A0},
0160     {0xA6FD, TB_ADDR_RX_PSC_A1},
0161     {0xA410, TB_ADDR_RX_PSC_A2},
0162     {0x2410, TB_ADDR_RX_PSC_A3},
0163
0164     {0x23FF, TB_ADDR_RX_PSC_CAL},
0165     {0x2010, TB_ADDR_RX_PSC_RDY},
0166
0167     {0x0020, TB_ADDR_TX_TXCC_MGNLS_MULT_000},
0168     {0x00ff, TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY},
0169     {0x0002, TB_ADDR_RX_SLC_CU_ITER_TMR},
0170     {0x0013, TB_ADDR_RX_SIGDET_HL_FILT_TMR},
0171     {0x0000, TB_ADDR_RX_SAMP_DAC_CTRL},
0172     {0x1004, TB_ADDR_RX_DIAG_SIGDET_TUNE},
0173     {0x4041, TB_ADDR_RX_DIAG_LFPSDET_TUNE2},
0174     {0x0480, TB_ADDR_RX_DIAG_BS_TM},
0175     {0x8006, TB_ADDR_RX_DIAG_DFE_CTRL1},
0176     {0x003f, TB_ADDR_RX_DIAG_ILL_IQE_TRIM4},
0177     {0x543f, TB_ADDR_RX_DIAG_ILL_E_TRIM0},
0178     {0x543f, TB_ADDR_RX_DIAG_ILL_IQ_TRIM0},
0179     {0x0000, TB_ADDR_RX_DIAG_ILL_IQE_TRIM6},
0180     {0x8000, TB_ADDR_RX_DIAG_RXFE_TM3},
0181     {0x0003, TB_ADDR_RX_DIAG_RXFE_TM4},
0182     {0x2408, TB_ADDR_RX_DIAG_LFPSDET_TUNE},
0183     {0x05ca, TB_ADDR_RX_DIAG_DFE_CTRL3},
0184     {0x0258, TB_ADDR_RX_DIAG_SC2C_DELAY},
0185     {0x1fff, TB_ADDR_RX_REE_VGA_GAIN_NODFE},
0186
0187     {0x02c6, TB_ADDR_XCVR_PSM_CAL_TMR},
0188     {0x0002, TB_ADDR_XCVR_PSM_A0BYP_TMR},
0189     {0x02c6, TB_ADDR_XCVR_PSM_A0IN_TMR},
0190     {0x0010, TB_ADDR_XCVR_PSM_A1IN_TMR},
0191     {0x0010, TB_ADDR_XCVR_PSM_A2IN_TMR},
0192     {0x0010, TB_ADDR_XCVR_PSM_A3IN_TMR},
0193     {0x0010, TB_ADDR_XCVR_PSM_A4IN_TMR},
0194     {0x0010, TB_ADDR_XCVR_PSM_A5IN_TMR},
0195
0196     {0x0002, TB_ADDR_XCVR_PSM_A0OUT_TMR},
0197     {0x0002, TB_ADDR_XCVR_PSM_A1OUT_TMR},
0198     {0x0002, TB_ADDR_XCVR_PSM_A2OUT_TMR},
0199     {0x0002, TB_ADDR_XCVR_PSM_A3OUT_TMR},
0200     {0x0002, TB_ADDR_XCVR_PSM_A4OUT_TMR},
0201     {0x0002, TB_ADDR_XCVR_PSM_A5OUT_TMR},
0202     /* Change rx detect parameter */
0203     {0x0960, TB_ADDR_TX_RCVDET_EN_TMR},
0204     {0x01e0, TB_ADDR_TX_RCVDET_ST_TMR},
0205     {0x0090, TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR},
0206 };
0207
0208 static int cdns_salvo_phy_init(struct phy *phy)
0209 {
0210     struct cdns_salvo_phy *salvo_phy = phy_get_drvdata(phy);
0211     struct cdns_salvo_data *data = salvo_phy->data;
0212     int ret, i;
0213     u16 value;
0214
0215     ret = clk_prepare_enable(salvo_phy->clk);
0216     if (ret)
0217         return ret;
0218
0219     for (i = 0; i < data->init_sequence_length; i++) {
0220         const struct cdns_reg_pairs *reg_pair = data->init_sequence_val + i;
0221
0222         cdns_salvo_write(salvo_phy, reg_pair->off, reg_pair->val);
0223     }
0224
0225     /* RXDET_IN_P3_32KHZ, Receiver detect slow clock enable */
0226     value = cdns_salvo_read(salvo_phy, TB_ADDR_TX_RCVDETSC_CTRL);
0227     value |= RXDET_IN_P3_32KHZ;
0228     cdns_salvo_write(salvo_phy, TB_ADDR_TX_RCVDETSC_CTRL,
0229              RXDET_IN_P3_32KHZ);
0230
0231     udelay(10);
0232
0233     clk_disable_unprepare(salvo_phy->clk);
0234
0235     return ret;
0236 }
0237
0238 static int cdns_salvo_phy_power_on(struct phy *phy)
0239 {
0240     struct cdns_salvo_phy *salvo_phy = phy_get_drvdata(phy);
0241
0242     return clk_prepare_enable(salvo_phy->clk);
0243 }
0244
0245 static int cdns_salvo_phy_power_off(struct phy *phy)
0246 {
0247     struct cdns_salvo_phy *salvo_phy = phy_get_drvdata(phy);
0248
0249     clk_disable_unprepare(salvo_phy->clk);
0250
0251     return 0;
0252 }
0253
0254 static const struct phy_ops cdns_salvo_phy_ops = {
0255     .init       = cdns_salvo_phy_init,
0256     .power_on   = cdns_salvo_phy_power_on,
0257     .power_off  = cdns_salvo_phy_power_off,
0258     .owner      = THIS_MODULE,
0259 };
0260
0261 static int cdns_salvo_phy_probe(struct platform_device *pdev)
0262 {
0263     struct phy_provider *phy_provider;
0264     struct device *dev = &pdev->dev;
0265     struct cdns_salvo_phy *salvo_phy;
0266     struct cdns_salvo_data *data;
0267
0268     data = (struct cdns_salvo_data *)of_device_get_match_data(dev);
0269     salvo_phy = devm_kzalloc(dev, sizeof(*salvo_phy), GFP_KERNEL);
0270     if (!salvo_phy)
0271         return -ENOMEM;
0272
0273     salvo_phy->data = data;
0274     salvo_phy->clk = devm_clk_get_optional(dev, "salvo_phy_clk");
0275     if (IS_ERR(salvo_phy->clk))
0276         return PTR_ERR(salvo_phy->clk);
0277
0278     salvo_phy->base = devm_platform_ioremap_resource(pdev, 0);
0279     if (IS_ERR(salvo_phy->base))
0280         return PTR_ERR(salvo_phy->base);
0281
0282     salvo_phy->phy = devm_phy_create(dev, NULL, &cdns_salvo_phy_ops);
0283     if (IS_ERR(salvo_phy->phy))
0284         return PTR_ERR(salvo_phy->phy);
0285
0286     phy_set_drvdata(salvo_phy->phy, salvo_phy);
0287
0288     phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0289     return PTR_ERR_OR_ZERO(phy_provider);
0290 }
0291
0292 static const struct cdns_salvo_data cdns_nxp_salvo_data = {
0293     2,
0294     cdns_nxp_sequence_pair,
0295     ARRAY_SIZE(cdns_nxp_sequence_pair),
0296 };
0297
0298 static const struct of_device_id cdns_salvo_phy_of_match[] = {
0299     {
0300         .compatible = "nxp,salvo-phy",
0301         .data = &cdns_nxp_salvo_data,
0302     },
0303     {}
0304 };
0305 MODULE_DEVICE_TABLE(of, cdns_salvo_phy_of_match);
0306
0307 static struct platform_driver cdns_salvo_phy_driver = {
0308     .probe  = cdns_salvo_phy_probe,
0309     .driver = {
0310         .name   = "cdns-salvo-phy",
0311         .of_match_table = cdns_salvo_phy_of_match,
0312     }
0313 };
0314 module_platform_driver(cdns_salvo_phy_driver);
0315
0316 MODULE_AUTHOR("Peter Chen <peter.chen@nxp.com>");
0317 MODULE_LICENSE("GPL v2");
0318 MODULE_DESCRIPTION("Cadence SALVO PHY Driver");