phy/cadence/cdns-dphy.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright: 2017-2018 Cadence Design Systems, Inc.
0004  */
0005
0006 #include <linux/bitfield.h>
0007 #include <linux/bitops.h>
0008 #include <linux/clk.h>
0009 #include <linux/io.h>
0010 #include <linux/iopoll.h>
0011 #include <linux/module.h>
0012 #include <linux/of_address.h>
0013 #include <linux/of_device.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/reset.h>
0016
0017 #include <linux/phy/phy.h>
0018 #include <linux/phy/phy-mipi-dphy.h>
0019
0020 #define REG_WAKEUP_TIME_NS      800
0021 #define DPHY_PLL_RATE_HZ        108000000
0022 #define POLL_TIMEOUT_US         1000
0023
0024 /* DPHY registers */
0025 #define DPHY_PMA_CMN(reg)       (reg)
0026 #define DPHY_PMA_LCLK(reg)      (0x100 + (reg))
0027 #define DPHY_PMA_LDATA(lane, reg)   (0x200 + ((lane) * 0x100) + (reg))
0028 #define DPHY_PMA_RCLK(reg)      (0x600 + (reg))
0029 #define DPHY_PMA_RDATA(lane, reg)   (0x700 + ((lane) * 0x100) + (reg))
0030 #define DPHY_PCS(reg)           (0xb00 + (reg))
0031
0032 #define DPHY_CMN_SSM            DPHY_PMA_CMN(0x20)
0033 #define DPHY_CMN_SSM_EN         BIT(0)
0034 #define DPHY_CMN_TX_MODE_EN     BIT(9)
0035
0036 #define DPHY_CMN_PWM            DPHY_PMA_CMN(0x40)
0037 #define DPHY_CMN_PWM_DIV(x)     ((x) << 20)
0038 #define DPHY_CMN_PWM_LOW(x)     ((x) << 10)
0039 #define DPHY_CMN_PWM_HIGH(x)        (x)
0040
0041 #define DPHY_CMN_FBDIV          DPHY_PMA_CMN(0x4c)
0042 #define DPHY_CMN_FBDIV_VAL(low, high)   (((high) << 11) | ((low) << 22))
0043 #define DPHY_CMN_FBDIV_FROM_REG     (BIT(10) | BIT(21))
0044
0045 #define DPHY_CMN_OPIPDIV        DPHY_PMA_CMN(0x50)
0046 #define DPHY_CMN_IPDIV_FROM_REG     BIT(0)
0047 #define DPHY_CMN_IPDIV(x)       ((x) << 1)
0048 #define DPHY_CMN_OPDIV_FROM_REG     BIT(6)
0049 #define DPHY_CMN_OPDIV(x)       ((x) << 7)
0050
0051 #define DPHY_BAND_CFG           DPHY_PCS(0x0)
0052 #define DPHY_BAND_CFG_LEFT_BAND     GENMASK(4, 0)
0053 #define DPHY_BAND_CFG_RIGHT_BAND    GENMASK(9, 5)
0054
0055 #define DPHY_PSM_CFG            DPHY_PCS(0x4)
0056 #define DPHY_PSM_CFG_FROM_REG       BIT(0)
0057 #define DPHY_PSM_CLK_DIV(x)     ((x) << 1)
0058
0059 #define DSI_HBP_FRAME_OVERHEAD      12
0060 #define DSI_HSA_FRAME_OVERHEAD      14
0061 #define DSI_HFP_FRAME_OVERHEAD      6
0062 #define DSI_HSS_VSS_VSE_FRAME_OVERHEAD  4
0063 #define DSI_BLANKING_FRAME_OVERHEAD 6
0064 #define DSI_NULL_FRAME_OVERHEAD     6
0065 #define DSI_EOT_PKT_SIZE        4
0066
0067 #define DPHY_TX_J721E_WIZ_PLL_CTRL  0xF04
0068 #define DPHY_TX_J721E_WIZ_STATUS    0xF08
0069 #define DPHY_TX_J721E_WIZ_RST_CTRL  0xF0C
0070 #define DPHY_TX_J721E_WIZ_PSM_FREQ  0xF10
0071
0072 #define DPHY_TX_J721E_WIZ_IPDIV     GENMASK(4, 0)
0073 #define DPHY_TX_J721E_WIZ_OPDIV     GENMASK(13, 8)
0074 #define DPHY_TX_J721E_WIZ_FBDIV     GENMASK(25, 16)
0075 #define DPHY_TX_J721E_WIZ_LANE_RSTB BIT(31)
0076 #define DPHY_TX_WIZ_PLL_LOCK        BIT(31)
0077 #define DPHY_TX_WIZ_O_CMN_READY     BIT(31)
0078
0079 struct cdns_dphy_cfg {
0080     u8 pll_ipdiv;
0081     u8 pll_opdiv;
0082     u16 pll_fbdiv;
0083     unsigned int nlanes;
0084 };
0085
0086 enum cdns_dphy_clk_lane_cfg {
0087     DPHY_CLK_CFG_LEFT_DRIVES_ALL = 0,
0088     DPHY_CLK_CFG_LEFT_DRIVES_RIGHT = 1,
0089     DPHY_CLK_CFG_LEFT_DRIVES_LEFT = 2,
0090     DPHY_CLK_CFG_RIGHT_DRIVES_ALL = 3,
0091 };
0092
0093 struct cdns_dphy;
0094 struct cdns_dphy_ops {
0095     int (*probe)(struct cdns_dphy *dphy);
0096     void (*remove)(struct cdns_dphy *dphy);
0097     void (*set_psm_div)(struct cdns_dphy *dphy, u8 div);
0098     void (*set_clk_lane_cfg)(struct cdns_dphy *dphy,
0099                  enum cdns_dphy_clk_lane_cfg cfg);
0100     void (*set_pll_cfg)(struct cdns_dphy *dphy,
0101                 const struct cdns_dphy_cfg *cfg);
0102     unsigned long (*get_wakeup_time_ns)(struct cdns_dphy *dphy);
0103 };
0104
0105 struct cdns_dphy {
0106     struct cdns_dphy_cfg cfg;
0107     void __iomem *regs;
0108     struct clk *psm_clk;
0109     struct clk *pll_ref_clk;
0110     const struct cdns_dphy_ops *ops;
0111     struct phy *phy;
0112 };
0113
0114 /* Order of bands is important since the index is the band number. */
0115 static const unsigned int tx_bands[] = {
0116     80, 100, 120, 160, 200, 240, 320, 390, 450, 510, 560, 640, 690, 770,
0117     870, 950, 1000, 1200, 1400, 1600, 1800, 2000, 2200, 2500
0118 };
0119
0120 static int cdns_dsi_get_dphy_pll_cfg(struct cdns_dphy *dphy,
0121                      struct cdns_dphy_cfg *cfg,
0122                      struct phy_configure_opts_mipi_dphy *opts,
0123                      unsigned int *dsi_hfp_ext)
0124 {
0125     unsigned long pll_ref_hz = clk_get_rate(dphy->pll_ref_clk);
0126     u64 dlane_bps;
0127
0128     memset(cfg, 0, sizeof(*cfg));
0129
0130     if (pll_ref_hz < 9600000 || pll_ref_hz >= 150000000)
0131         return -EINVAL;
0132     else if (pll_ref_hz < 19200000)
0133         cfg->pll_ipdiv = 1;
0134     else if (pll_ref_hz < 38400000)
0135         cfg->pll_ipdiv = 2;
0136     else if (pll_ref_hz < 76800000)
0137         cfg->pll_ipdiv = 4;
0138     else
0139         cfg->pll_ipdiv = 8;
0140
0141     dlane_bps = opts->hs_clk_rate;
0142
0143     if (dlane_bps > 2500000000UL || dlane_bps < 160000000UL)
0144         return -EINVAL;
0145     else if (dlane_bps >= 1250000000)
0146         cfg->pll_opdiv = 1;
0147     else if (dlane_bps >= 630000000)
0148         cfg->pll_opdiv = 2;
0149     else if (dlane_bps >= 320000000)
0150         cfg->pll_opdiv = 4;
0151     else if (dlane_bps >= 160000000)
0152         cfg->pll_opdiv = 8;
0153
0154     cfg->pll_fbdiv = DIV_ROUND_UP_ULL(dlane_bps * 2 * cfg->pll_opdiv *
0155                       cfg->pll_ipdiv,
0156                       pll_ref_hz);
0157
0158     return 0;
0159 }
0160
0161 static int cdns_dphy_setup_psm(struct cdns_dphy *dphy)
0162 {
0163     unsigned long psm_clk_hz = clk_get_rate(dphy->psm_clk);
0164     unsigned long psm_div;
0165
0166     if (!psm_clk_hz || psm_clk_hz > 100000000)
0167         return -EINVAL;
0168
0169     psm_div = DIV_ROUND_CLOSEST(psm_clk_hz, 1000000);
0170     if (dphy->ops->set_psm_div)
0171         dphy->ops->set_psm_div(dphy, psm_div);
0172
0173     return 0;
0174 }
0175
0176 static void cdns_dphy_set_clk_lane_cfg(struct cdns_dphy *dphy,
0177                        enum cdns_dphy_clk_lane_cfg cfg)
0178 {
0179     if (dphy->ops->set_clk_lane_cfg)
0180         dphy->ops->set_clk_lane_cfg(dphy, cfg);
0181 }
0182
0183 static void cdns_dphy_set_pll_cfg(struct cdns_dphy *dphy,
0184                   const struct cdns_dphy_cfg *cfg)
0185 {
0186     if (dphy->ops->set_pll_cfg)
0187         dphy->ops->set_pll_cfg(dphy, cfg);
0188 }
0189
0190 static unsigned long cdns_dphy_get_wakeup_time_ns(struct cdns_dphy *dphy)
0191 {
0192     return dphy->ops->get_wakeup_time_ns(dphy);
0193 }
0194
0195 static unsigned long cdns_dphy_ref_get_wakeup_time_ns(struct cdns_dphy *dphy)
0196 {
0197     /* Default wakeup time is 800 ns (in a simulated environment). */
0198     return 800;
0199 }
0200
0201 static void cdns_dphy_ref_set_pll_cfg(struct cdns_dphy *dphy,
0202                       const struct cdns_dphy_cfg *cfg)
0203 {
0204     u32 fbdiv_low, fbdiv_high;
0205
0206     fbdiv_low = (cfg->pll_fbdiv / 4) - 2;
0207     fbdiv_high = cfg->pll_fbdiv - fbdiv_low - 2;
0208
0209     writel(DPHY_CMN_IPDIV_FROM_REG | DPHY_CMN_OPDIV_FROM_REG |
0210            DPHY_CMN_IPDIV(cfg->pll_ipdiv) |
0211            DPHY_CMN_OPDIV(cfg->pll_opdiv),
0212            dphy->regs + DPHY_CMN_OPIPDIV);
0213     writel(DPHY_CMN_FBDIV_FROM_REG |
0214            DPHY_CMN_FBDIV_VAL(fbdiv_low, fbdiv_high),
0215            dphy->regs + DPHY_CMN_FBDIV);
0216     writel(DPHY_CMN_PWM_HIGH(6) | DPHY_CMN_PWM_LOW(0x101) |
0217            DPHY_CMN_PWM_DIV(0x8),
0218            dphy->regs + DPHY_CMN_PWM);
0219 }
0220
0221 static void cdns_dphy_ref_set_psm_div(struct cdns_dphy *dphy, u8 div)
0222 {
0223     writel(DPHY_PSM_CFG_FROM_REG | DPHY_PSM_CLK_DIV(div),
0224            dphy->regs + DPHY_PSM_CFG);
0225 }
0226
0227 static unsigned long cdns_dphy_j721e_get_wakeup_time_ns(struct cdns_dphy *dphy)
0228 {
0229     /* Minimum wakeup time as per MIPI D-PHY spec v1.2 */
0230     return 1000000;
0231 }
0232
0233 static void cdns_dphy_j721e_set_pll_cfg(struct cdns_dphy *dphy,
0234                     const struct cdns_dphy_cfg *cfg)
0235 {
0236     u32 status;
0237
0238     /*
0239      * set the PWM and PLL Byteclk divider settings to recommended values
0240      * which is same as that of in ref ops
0241      */
0242     writel(DPHY_CMN_PWM_HIGH(6) | DPHY_CMN_PWM_LOW(0x101) |
0243            DPHY_CMN_PWM_DIV(0x8),
0244            dphy->regs + DPHY_CMN_PWM);
0245
0246     writel((FIELD_PREP(DPHY_TX_J721E_WIZ_IPDIV, cfg->pll_ipdiv) |
0247         FIELD_PREP(DPHY_TX_J721E_WIZ_OPDIV, cfg->pll_opdiv) |
0248         FIELD_PREP(DPHY_TX_J721E_WIZ_FBDIV, cfg->pll_fbdiv)),
0249         dphy->regs + DPHY_TX_J721E_WIZ_PLL_CTRL);
0250
0251     writel(DPHY_TX_J721E_WIZ_LANE_RSTB,
0252            dphy->regs + DPHY_TX_J721E_WIZ_RST_CTRL);
0253
0254     readl_poll_timeout(dphy->regs + DPHY_TX_J721E_WIZ_PLL_CTRL, status,
0255                (status & DPHY_TX_WIZ_PLL_LOCK), 0, POLL_TIMEOUT_US);
0256
0257     readl_poll_timeout(dphy->regs + DPHY_TX_J721E_WIZ_STATUS, status,
0258                (status & DPHY_TX_WIZ_O_CMN_READY), 0,
0259                POLL_TIMEOUT_US);
0260 }
0261
0262 static void cdns_dphy_j721e_set_psm_div(struct cdns_dphy *dphy, u8 div)
0263 {
0264     writel(div, dphy->regs + DPHY_TX_J721E_WIZ_PSM_FREQ);
0265 }
0266
0267 /*
0268  * This is the reference implementation of DPHY hooks. Specific integration of
0269  * this IP may have to re-implement some of them depending on how they decided
0270  * to wire things in the SoC.
0271  */
0272 static const struct cdns_dphy_ops ref_dphy_ops = {
0273     .get_wakeup_time_ns = cdns_dphy_ref_get_wakeup_time_ns,
0274     .set_pll_cfg = cdns_dphy_ref_set_pll_cfg,
0275     .set_psm_div = cdns_dphy_ref_set_psm_div,
0276 };
0277
0278 static const struct cdns_dphy_ops j721e_dphy_ops = {
0279     .get_wakeup_time_ns = cdns_dphy_j721e_get_wakeup_time_ns,
0280     .set_pll_cfg = cdns_dphy_j721e_set_pll_cfg,
0281     .set_psm_div = cdns_dphy_j721e_set_psm_div,
0282 };
0283
0284 static int cdns_dphy_config_from_opts(struct phy *phy,
0285                       struct phy_configure_opts_mipi_dphy *opts,
0286                       struct cdns_dphy_cfg *cfg)
0287 {
0288     struct cdns_dphy *dphy = phy_get_drvdata(phy);
0289     unsigned int dsi_hfp_ext = 0;
0290     int ret;
0291
0292     ret = phy_mipi_dphy_config_validate(opts);
0293     if (ret)
0294         return ret;
0295
0296     ret = cdns_dsi_get_dphy_pll_cfg(dphy, cfg,
0297                     opts, &dsi_hfp_ext);
0298     if (ret)
0299         return ret;
0300
0301     opts->wakeup = cdns_dphy_get_wakeup_time_ns(dphy) / 1000;
0302
0303     return 0;
0304 }
0305
0306 static int cdns_dphy_tx_get_band_ctrl(unsigned long hs_clk_rate)
0307 {
0308     unsigned int rate;
0309     int i;
0310
0311     rate = hs_clk_rate / 1000000UL;
0312
0313     if (rate < tx_bands[0])
0314         return -EOPNOTSUPP;
0315
0316     for (i = 0; i < ARRAY_SIZE(tx_bands) - 1; i++) {
0317         if (rate >= tx_bands[i] && rate < tx_bands[i + 1])
0318             return i;
0319     }
0320
0321     return -EOPNOTSUPP;
0322 }
0323
0324 static int cdns_dphy_validate(struct phy *phy, enum phy_mode mode, int submode,
0325                   union phy_configure_opts *opts)
0326 {
0327     struct cdns_dphy_cfg cfg = { 0 };
0328
0329     if (mode != PHY_MODE_MIPI_DPHY)
0330         return -EINVAL;
0331
0332     return cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg);
0333 }
0334
0335 static int cdns_dphy_configure(struct phy *phy, union phy_configure_opts *opts)
0336 {
0337     struct cdns_dphy *dphy = phy_get_drvdata(phy);
0338     struct cdns_dphy_cfg cfg = { 0 };
0339     int ret, band_ctrl;
0340     unsigned int reg;
0341
0342     ret = cdns_dphy_config_from_opts(phy, &opts->mipi_dphy, &cfg);
0343     if (ret)
0344         return ret;
0345
0346     /*
0347      * Configure the internal PSM clk divider so that the DPHY has a
0348      * 1MHz clk (or something close).
0349      */
0350     ret = cdns_dphy_setup_psm(dphy);
0351     if (ret)
0352         return ret;
0353
0354     /*
0355      * Configure attach clk lanes to data lanes: the DPHY has 2 clk lanes
0356      * and 8 data lanes, each clk lane can be attache different set of
0357      * data lanes. The 2 groups are named 'left' and 'right', so here we
0358      * just say that we want the 'left' clk lane to drive the 'left' data
0359      * lanes.
0360      */
0361     cdns_dphy_set_clk_lane_cfg(dphy, DPHY_CLK_CFG_LEFT_DRIVES_LEFT);
0362
0363     /*
0364      * Configure the DPHY PLL that will be used to generate the TX byte
0365      * clk.
0366      */
0367     cdns_dphy_set_pll_cfg(dphy, &cfg);
0368
0369     band_ctrl = cdns_dphy_tx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate);
0370     if (band_ctrl < 0)
0371         return band_ctrl;
0372
0373     reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, band_ctrl) |
0374           FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, band_ctrl);
0375     writel(reg, dphy->regs + DPHY_BAND_CFG);
0376
0377     return 0;
0378 }
0379
0380 static int cdns_dphy_power_on(struct phy *phy)
0381 {
0382     struct cdns_dphy *dphy = phy_get_drvdata(phy);
0383
0384     clk_prepare_enable(dphy->psm_clk);
0385     clk_prepare_enable(dphy->pll_ref_clk);
0386
0387     /* Start TX state machine. */
0388     writel(DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN,
0389            dphy->regs + DPHY_CMN_SSM);
0390
0391     return 0;
0392 }
0393
0394 static int cdns_dphy_power_off(struct phy *phy)
0395 {
0396     struct cdns_dphy *dphy = phy_get_drvdata(phy);
0397
0398     clk_disable_unprepare(dphy->pll_ref_clk);
0399     clk_disable_unprepare(dphy->psm_clk);
0400
0401     return 0;
0402 }
0403
0404 static const struct phy_ops cdns_dphy_ops = {
0405     .configure  = cdns_dphy_configure,
0406     .validate   = cdns_dphy_validate,
0407     .power_on   = cdns_dphy_power_on,
0408     .power_off  = cdns_dphy_power_off,
0409 };
0410
0411 static int cdns_dphy_probe(struct platform_device *pdev)
0412 {
0413     struct phy_provider *phy_provider;
0414     struct cdns_dphy *dphy;
0415     int ret;
0416
0417     dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL);
0418     if (!dphy)
0419         return -ENOMEM;
0420     dev_set_drvdata(&pdev->dev, dphy);
0421
0422     dphy->ops = of_device_get_match_data(&pdev->dev);
0423     if (!dphy->ops)
0424         return -EINVAL;
0425
0426     dphy->regs = devm_platform_ioremap_resource(pdev, 0);
0427     if (IS_ERR(dphy->regs))
0428         return PTR_ERR(dphy->regs);
0429
0430     dphy->psm_clk = devm_clk_get(&pdev->dev, "psm");
0431     if (IS_ERR(dphy->psm_clk))
0432         return PTR_ERR(dphy->psm_clk);
0433
0434     dphy->pll_ref_clk = devm_clk_get(&pdev->dev, "pll_ref");
0435     if (IS_ERR(dphy->pll_ref_clk))
0436         return PTR_ERR(dphy->pll_ref_clk);
0437
0438     if (dphy->ops->probe) {
0439         ret = dphy->ops->probe(dphy);
0440         if (ret)
0441             return ret;
0442     }
0443
0444     dphy->phy = devm_phy_create(&pdev->dev, NULL, &cdns_dphy_ops);
0445     if (IS_ERR(dphy->phy)) {
0446         dev_err(&pdev->dev, "failed to create PHY\n");
0447         if (dphy->ops->remove)
0448             dphy->ops->remove(dphy);
0449         return PTR_ERR(dphy->phy);
0450     }
0451
0452     phy_set_drvdata(dphy->phy, dphy);
0453     phy_provider = devm_of_phy_provider_register(&pdev->dev,
0454                              of_phy_simple_xlate);
0455
0456     return PTR_ERR_OR_ZERO(phy_provider);
0457 }
0458
0459 static int cdns_dphy_remove(struct platform_device *pdev)
0460 {
0461     struct cdns_dphy *dphy = dev_get_drvdata(&pdev->dev);
0462
0463     if (dphy->ops->remove)
0464         dphy->ops->remove(dphy);
0465
0466     return 0;
0467 }
0468
0469 static const struct of_device_id cdns_dphy_of_match[] = {
0470     { .compatible = "cdns,dphy", .data = &ref_dphy_ops },
0471     { .compatible = "ti,j721e-dphy", .data = &j721e_dphy_ops },
0472     { /* sentinel */ },
0473 };
0474 MODULE_DEVICE_TABLE(of, cdns_dphy_of_match);
0475
0476 static struct platform_driver cdns_dphy_platform_driver = {
0477     .probe      = cdns_dphy_probe,
0478     .remove     = cdns_dphy_remove,
0479     .driver     = {
0480         .name       = "cdns-mipi-dphy",
0481         .of_match_table = cdns_dphy_of_match,
0482     },
0483 };
0484 module_platform_driver(cdns_dphy_platform_driver);
0485
0486 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@bootlin.com>");
0487 MODULE_DESCRIPTION("Cadence MIPI D-PHY Driver");
0488 MODULE_LICENSE("GPL");