phy/cadence/cdns-dphy-rx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
0004  */
0005
0006 #include <linux/bitfield.h>
0007 #include <linux/bitops.h>
0008 #include <linux/io.h>
0009 #include <linux/iopoll.h>
0010 #include <linux/module.h>
0011 #include <linux/phy/phy.h>
0012 #include <linux/phy/phy-mipi-dphy.h>
0013 #include <linux/platform_device.h>
0014
0015 #define DPHY_PMA_CMN(reg)       (reg)
0016 #define DPHY_PCS(reg)           (0xb00 + (reg))
0017 #define DPHY_ISO(reg)           (0xc00 + (reg))
0018
0019 #define DPHY_CMN_SSM            DPHY_PMA_CMN(0x20)
0020 #define DPHY_CMN_RX_MODE_EN     BIT(10)
0021 #define DPHY_CMN_RX_BANDGAP_TIMER_MASK  GENMASK(8, 1)
0022 #define DPHY_CMN_SSM_EN         BIT(0)
0023
0024 #define DPHY_CMN_RX_BANDGAP_TIMER   0x14
0025
0026 #define DPHY_BAND_CFG           DPHY_PCS(0x0)
0027 #define DPHY_BAND_CFG_RIGHT_BAND    GENMASK(9, 5)
0028 #define DPHY_BAND_CFG_LEFT_BAND     GENMASK(4, 0)
0029
0030 #define DPHY_POWER_ISLAND_EN_DATA   DPHY_PCS(0x8)
0031 #define DPHY_POWER_ISLAND_EN_DATA_VAL   0xaaaaaaaa
0032
0033 #define DPHY_POWER_ISLAND_EN_CLK    DPHY_PCS(0xc)
0034 #define DPHY_POWER_ISLAND_EN_CLK_VAL    0xaa
0035
0036 #define DPHY_ISO_CL_CTRL_L      DPHY_ISO(0x10)
0037 #define DPHY_ISO_DL_CTRL_L0     DPHY_ISO(0x14)
0038 #define DPHY_ISO_DL_CTRL_L1     DPHY_ISO(0x20)
0039 #define DPHY_ISO_DL_CTRL_L2     DPHY_ISO(0x30)
0040 #define DPHY_ISO_DL_CTRL_L3     DPHY_ISO(0x3c)
0041
0042 #define DPHY_ISO_LANE_READY_BIT     0
0043 #define DPHY_ISO_LANE_READY_TIMEOUT_MS  100UL
0044
0045 #define DPHY_LANES_MIN          1
0046 #define DPHY_LANES_MAX          4
0047
0048 struct cdns_dphy_rx {
0049     void __iomem *regs;
0050     struct device *dev;
0051     struct phy *phy;
0052 };
0053
0054 struct cdns_dphy_rx_band {
0055     /* Rates are in Mbps. */
0056     unsigned int min_rate;
0057     unsigned int max_rate;
0058 };
0059
0060 /* Order of bands is important since the index is the band number. */
0061 static const struct cdns_dphy_rx_band bands[] = {
0062     { 80, 100 }, { 100, 120 }, { 120, 160 }, { 160, 200 }, { 200, 240 },
0063     { 240, 280 }, { 280, 320 }, { 320, 360 }, { 360, 400 }, { 400, 480 },
0064     { 480, 560 }, { 560, 640 }, { 640, 720 }, { 720, 800 }, { 800, 880 },
0065     { 880, 1040 }, { 1040, 1200 }, { 1200, 1350 }, { 1350, 1500 },
0066     { 1500, 1750 }, { 1750, 2000 }, { 2000, 2250 }, { 2250, 2500 }
0067 };
0068
0069 static int cdns_dphy_rx_power_on(struct phy *phy)
0070 {
0071     struct cdns_dphy_rx *dphy = phy_get_drvdata(phy);
0072
0073     /* Start RX state machine. */
0074     writel(DPHY_CMN_SSM_EN | DPHY_CMN_RX_MODE_EN |
0075            FIELD_PREP(DPHY_CMN_RX_BANDGAP_TIMER_MASK,
0076               DPHY_CMN_RX_BANDGAP_TIMER),
0077            dphy->regs + DPHY_CMN_SSM);
0078
0079     return 0;
0080 }
0081
0082 static int cdns_dphy_rx_power_off(struct phy *phy)
0083 {
0084     struct cdns_dphy_rx *dphy = phy_get_drvdata(phy);
0085
0086     writel(0, dphy->regs + DPHY_CMN_SSM);
0087
0088     return 0;
0089 }
0090
0091 static int cdns_dphy_rx_get_band_ctrl(unsigned long hs_clk_rate)
0092 {
0093     unsigned int rate, i;
0094
0095     rate = hs_clk_rate / 1000000UL;
0096     /* Since CSI-2 clock is DDR, the bit rate is twice the clock rate. */
0097     rate *= 2;
0098
0099     if (rate < bands[0].min_rate)
0100         return -EOPNOTSUPP;
0101
0102     for (i = 0; i < ARRAY_SIZE(bands); i++)
0103         if (rate < bands[i].max_rate)
0104             return i;
0105
0106     return -EOPNOTSUPP;
0107 }
0108
0109 static inline int cdns_dphy_rx_wait_for_bit(void __iomem *addr,
0110                         unsigned int bit)
0111 {
0112     u32 val;
0113
0114     return readl_relaxed_poll_timeout(addr, val, val & BIT(bit), 10,
0115                       DPHY_ISO_LANE_READY_TIMEOUT_MS * 1000);
0116 }
0117
0118 static int cdns_dphy_rx_wait_lane_ready(struct cdns_dphy_rx *dphy,
0119                     unsigned int lanes)
0120 {
0121     static const u32 data_lane_ctrl[] = {DPHY_ISO_DL_CTRL_L0,
0122                          DPHY_ISO_DL_CTRL_L1,
0123                          DPHY_ISO_DL_CTRL_L2,
0124                          DPHY_ISO_DL_CTRL_L3};
0125     void __iomem *reg = dphy->regs;
0126     unsigned int i;
0127     int ret;
0128
0129     /* Clock lane */
0130     ret = cdns_dphy_rx_wait_for_bit(reg + DPHY_ISO_CL_CTRL_L,
0131                     DPHY_ISO_LANE_READY_BIT);
0132     if (ret)
0133         return ret;
0134
0135     for (i = 0; i < lanes; i++) {
0136         ret = cdns_dphy_rx_wait_for_bit(reg + data_lane_ctrl[i],
0137                         DPHY_ISO_LANE_READY_BIT);
0138         if (ret)
0139             return ret;
0140     }
0141
0142     return 0;
0143 }
0144
0145 static int cdns_dphy_rx_configure(struct phy *phy,
0146                   union phy_configure_opts *opts)
0147 {
0148     struct cdns_dphy_rx *dphy = phy_get_drvdata(phy);
0149     unsigned int reg, lanes = opts->mipi_dphy.lanes;
0150     int band_ctrl, ret;
0151
0152     /* Data lanes. Minimum one lane is mandatory. */
0153     if (lanes < DPHY_LANES_MIN || lanes > DPHY_LANES_MAX)
0154         return -EINVAL;
0155
0156     band_ctrl = cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate);
0157     if (band_ctrl < 0)
0158         return band_ctrl;
0159
0160     reg = FIELD_PREP(DPHY_BAND_CFG_LEFT_BAND, band_ctrl) |
0161           FIELD_PREP(DPHY_BAND_CFG_RIGHT_BAND, band_ctrl);
0162     writel(reg, dphy->regs + DPHY_BAND_CFG);
0163
0164     /*
0165      * Set the required power island phase 2 time. This is mandated by DPHY
0166      * specs.
0167      */
0168     reg = DPHY_POWER_ISLAND_EN_DATA_VAL;
0169     writel(reg, dphy->regs + DPHY_POWER_ISLAND_EN_DATA);
0170     reg = DPHY_POWER_ISLAND_EN_CLK_VAL;
0171     writel(reg, dphy->regs + DPHY_POWER_ISLAND_EN_CLK);
0172
0173     ret = cdns_dphy_rx_wait_lane_ready(dphy, lanes);
0174     if (ret) {
0175         dev_err(dphy->dev, "DPHY wait for lane ready timeout\n");
0176         return ret;
0177     }
0178
0179     return 0;
0180 }
0181
0182 static int cdns_dphy_rx_validate(struct phy *phy, enum phy_mode mode,
0183                  int submode, union phy_configure_opts *opts)
0184 {
0185     int ret;
0186
0187     if (mode != PHY_MODE_MIPI_DPHY)
0188         return -EINVAL;
0189
0190     ret = cdns_dphy_rx_get_band_ctrl(opts->mipi_dphy.hs_clk_rate);
0191     if (ret < 0)
0192         return ret;
0193
0194     return phy_mipi_dphy_config_validate(&opts->mipi_dphy);
0195 }
0196
0197 static const struct phy_ops cdns_dphy_rx_ops = {
0198     .power_on = cdns_dphy_rx_power_on,
0199     .power_off = cdns_dphy_rx_power_off,
0200     .configure = cdns_dphy_rx_configure,
0201     .validate = cdns_dphy_rx_validate,
0202 };
0203
0204 static int cdns_dphy_rx_probe(struct platform_device *pdev)
0205 {
0206     struct device *dev = &pdev->dev;
0207     struct phy_provider *provider;
0208     struct cdns_dphy_rx *dphy;
0209
0210     dphy = devm_kzalloc(dev, sizeof(*dphy), GFP_KERNEL);
0211     if (!dphy)
0212         return -ENOMEM;
0213
0214     dev_set_drvdata(dev, dphy);
0215     dphy->dev = dev;
0216
0217     dphy->regs = devm_platform_ioremap_resource(pdev, 0);
0218     if (IS_ERR(dphy->regs))
0219         return PTR_ERR(dphy->regs);
0220
0221     dphy->phy = devm_phy_create(dev, NULL, &cdns_dphy_rx_ops);
0222     if (IS_ERR(dphy->phy)) {
0223         dev_err(dev, "Failed to create PHY: %ld\n", PTR_ERR(dphy->phy));
0224         return PTR_ERR(dphy->phy);
0225     }
0226
0227     phy_set_drvdata(dphy->phy, dphy);
0228     provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0229     if (IS_ERR(provider)) {
0230         dev_err(dev, "Failed to register PHY provider: %ld\n",
0231             PTR_ERR(provider));
0232         return PTR_ERR(provider);
0233     }
0234
0235     return 0;
0236 }
0237
0238 static const struct of_device_id cdns_dphy_rx_of_match[] = {
0239     { .compatible = "cdns,dphy-rx" },
0240     { /* sentinel */ },
0241 };
0242 MODULE_DEVICE_TABLE(of, cdns_dphy_rx_of_match);
0243
0244 static struct platform_driver cdns_dphy_rx_platform_driver = {
0245     .probe      = cdns_dphy_rx_probe,
0246     .driver     = {
0247         .name       = "cdns-mipi-dphy-rx",
0248         .of_match_table = cdns_dphy_rx_of_match,
0249     },
0250 };
0251 module_platform_driver(cdns_dphy_rx_platform_driver);
0252
0253 MODULE_AUTHOR("Pratyush Yadav <p.yadav@ti.com>");
0254 MODULE_DESCRIPTION("Cadence D-PHY Rx Driver");
0255 MODULE_LICENSE("GPL");