phy/broadcom/phy-bcm-cygnus-pcie.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 // Copyright (C) 2015 Broadcom Corporation
0003
0004 #include <linux/delay.h>
0005 #include <linux/io.h>
0006 #include <linux/module.h>
0007 #include <linux/of.h>
0008 #include <linux/phy/phy.h>
0009 #include <linux/platform_device.h>
0010
0011 #define PCIE_CFG_OFFSET         0x00
0012 #define PCIE1_PHY_IDDQ_SHIFT    10
0013 #define PCIE0_PHY_IDDQ_SHIFT    2
0014
0015 enum cygnus_pcie_phy_id {
0016     CYGNUS_PHY_PCIE0 = 0,
0017     CYGNUS_PHY_PCIE1,
0018     MAX_NUM_PHYS,
0019 };
0020
0021 struct cygnus_pcie_phy_core;
0022
0023 /**
0024  * struct cygnus_pcie_phy - Cygnus PCIe PHY device
0025  * @core: pointer to the Cygnus PCIe PHY core control
0026  * @id: internal ID to identify the Cygnus PCIe PHY
0027  * @phy: pointer to the kernel PHY device
0028  */
0029 struct cygnus_pcie_phy {
0030     struct cygnus_pcie_phy_core *core;
0031     enum cygnus_pcie_phy_id id;
0032     struct phy *phy;
0033 };
0034
0035 /**
0036  * struct cygnus_pcie_phy_core - Cygnus PCIe PHY core control
0037  * @dev: pointer to device
0038  * @base: base register
0039  * @lock: mutex to protect access to individual PHYs
0040  * @phys: pointer to Cygnus PHY device
0041  */
0042 struct cygnus_pcie_phy_core {
0043     struct device *dev;
0044     void __iomem *base;
0045     struct mutex lock;
0046     struct cygnus_pcie_phy phys[MAX_NUM_PHYS];
0047 };
0048
0049 static int cygnus_pcie_power_config(struct cygnus_pcie_phy *phy, bool enable)
0050 {
0051     struct cygnus_pcie_phy_core *core = phy->core;
0052     unsigned shift;
0053     u32 val;
0054
0055     mutex_lock(&core->lock);
0056
0057     switch (phy->id) {
0058     case CYGNUS_PHY_PCIE0:
0059         shift = PCIE0_PHY_IDDQ_SHIFT;
0060         break;
0061
0062     case CYGNUS_PHY_PCIE1:
0063         shift = PCIE1_PHY_IDDQ_SHIFT;
0064         break;
0065
0066     default:
0067         mutex_unlock(&core->lock);
0068         dev_err(core->dev, "PCIe PHY %d invalid\n", phy->id);
0069         return -EINVAL;
0070     }
0071
0072     if (enable) {
0073         val = readl(core->base + PCIE_CFG_OFFSET);
0074         val &= ~BIT(shift);
0075         writel(val, core->base + PCIE_CFG_OFFSET);
0076         /*
0077          * Wait 50 ms for the PCIe Serdes to stabilize after the analog
0078          * front end is brought up
0079          */
0080         msleep(50);
0081     } else {
0082         val = readl(core->base + PCIE_CFG_OFFSET);
0083         val |= BIT(shift);
0084         writel(val, core->base + PCIE_CFG_OFFSET);
0085     }
0086
0087     mutex_unlock(&core->lock);
0088     dev_dbg(core->dev, "PCIe PHY %d %s\n", phy->id,
0089         enable ? "enabled" : "disabled");
0090     return 0;
0091 }
0092
0093 static int cygnus_pcie_phy_power_on(struct phy *p)
0094 {
0095     struct cygnus_pcie_phy *phy = phy_get_drvdata(p);
0096
0097     return cygnus_pcie_power_config(phy, true);
0098 }
0099
0100 static int cygnus_pcie_phy_power_off(struct phy *p)
0101 {
0102     struct cygnus_pcie_phy *phy = phy_get_drvdata(p);
0103
0104     return cygnus_pcie_power_config(phy, false);
0105 }
0106
0107 static const struct phy_ops cygnus_pcie_phy_ops = {
0108     .power_on = cygnus_pcie_phy_power_on,
0109     .power_off = cygnus_pcie_phy_power_off,
0110     .owner = THIS_MODULE,
0111 };
0112
0113 static int cygnus_pcie_phy_probe(struct platform_device *pdev)
0114 {
0115     struct device *dev = &pdev->dev;
0116     struct device_node *node = dev->of_node, *child;
0117     struct cygnus_pcie_phy_core *core;
0118     struct phy_provider *provider;
0119     unsigned cnt = 0;
0120     int ret;
0121
0122     if (of_get_child_count(node) == 0) {
0123         dev_err(dev, "PHY no child node\n");
0124         return -ENODEV;
0125     }
0126
0127     core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL);
0128     if (!core)
0129         return -ENOMEM;
0130
0131     core->dev = dev;
0132
0133     core->base = devm_platform_ioremap_resource(pdev, 0);
0134     if (IS_ERR(core->base))
0135         return PTR_ERR(core->base);
0136
0137     mutex_init(&core->lock);
0138
0139     for_each_available_child_of_node(node, child) {
0140         unsigned int id;
0141         struct cygnus_pcie_phy *p;
0142
0143         if (of_property_read_u32(child, "reg", &id)) {
0144             dev_err(dev, "missing reg property for %pOFn\n",
0145                 child);
0146             ret = -EINVAL;
0147             goto put_child;
0148         }
0149
0150         if (id >= MAX_NUM_PHYS) {
0151             dev_err(dev, "invalid PHY id: %u\n", id);
0152             ret = -EINVAL;
0153             goto put_child;
0154         }
0155
0156         if (core->phys[id].phy) {
0157             dev_err(dev, "duplicated PHY id: %u\n", id);
0158             ret = -EINVAL;
0159             goto put_child;
0160         }
0161
0162         p = &core->phys[id];
0163         p->phy = devm_phy_create(dev, child, &cygnus_pcie_phy_ops);
0164         if (IS_ERR(p->phy)) {
0165             dev_err(dev, "failed to create PHY\n");
0166             ret = PTR_ERR(p->phy);
0167             goto put_child;
0168         }
0169
0170         p->core = core;
0171         p->id = id;
0172         phy_set_drvdata(p->phy, p);
0173         cnt++;
0174     }
0175
0176     dev_set_drvdata(dev, core);
0177
0178     provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0179     if (IS_ERR(provider)) {
0180         dev_err(dev, "failed to register PHY provider\n");
0181         return PTR_ERR(provider);
0182     }
0183
0184     dev_dbg(dev, "registered %u PCIe PHY(s)\n", cnt);
0185
0186     return 0;
0187 put_child:
0188     of_node_put(child);
0189     return ret;
0190 }
0191
0192 static const struct of_device_id cygnus_pcie_phy_match_table[] = {
0193     { .compatible = "brcm,cygnus-pcie-phy" },
0194     { /* sentinel */ }
0195 };
0196 MODULE_DEVICE_TABLE(of, cygnus_pcie_phy_match_table);
0197
0198 static struct platform_driver cygnus_pcie_phy_driver = {
0199     .driver = {
0200         .name = "cygnus-pcie-phy",
0201         .of_match_table = cygnus_pcie_phy_match_table,
0202     },
0203     .probe = cygnus_pcie_phy_probe,
0204 };
0205 module_platform_driver(cygnus_pcie_phy_driver);
0206
0207 MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
0208 MODULE_DESCRIPTION("Broadcom Cygnus PCIe PHY driver");
0209 MODULE_LICENSE("GPL v2");