phy/amlogic/phy-meson8-hdmi-tx.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Meson8, Meson8b and Meson8m2 HDMI TX PHY.
0004  *
0005  * Copyright (C) 2021 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
0006  */
0007
0008 #include <linux/bitfield.h>
0009 #include <linux/bits.h>
0010 #include <linux/clk.h>
0011 #include <linux/mfd/syscon.h>
0012 #include <linux/module.h>
0013 #include <linux/of_device.h>
0014 #include <linux/phy/phy.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/property.h>
0017 #include <linux/regmap.h>
0018
0019 /*
0020  * Unfortunately there is no detailed documentation available for the
0021  * HHI_HDMI_PHY_CNTL0 register. CTL0 and CTL1 is all we know about.
0022  * Magic register values in the driver below are taken from the vendor
0023  * BSP / kernel.
0024  */
0025 #define HHI_HDMI_PHY_CNTL0              0x3a0
0026     #define HHI_HDMI_PHY_CNTL0_HDMI_CTL1        GENMASK(31, 16)
0027     #define HHI_HDMI_PHY_CNTL0_HDMI_CTL0        GENMASK(15, 0)
0028
0029 #define HHI_HDMI_PHY_CNTL1              0x3a4
0030     #define HHI_HDMI_PHY_CNTL1_CLOCK_ENABLE     BIT(1)
0031     #define HHI_HDMI_PHY_CNTL1_SOFT_RESET       BIT(0)
0032
0033 #define HHI_HDMI_PHY_CNTL2              0x3a8
0034
0035 struct phy_meson8_hdmi_tx_priv {
0036     struct regmap       *hhi;
0037     struct clk      *tmds_clk;
0038 };
0039
0040 static int phy_meson8_hdmi_tx_init(struct phy *phy)
0041 {
0042     struct phy_meson8_hdmi_tx_priv *priv = phy_get_drvdata(phy);
0043
0044     return clk_prepare_enable(priv->tmds_clk);
0045 }
0046
0047 static int phy_meson8_hdmi_tx_exit(struct phy *phy)
0048 {
0049     struct phy_meson8_hdmi_tx_priv *priv = phy_get_drvdata(phy);
0050
0051     clk_disable_unprepare(priv->tmds_clk);
0052
0053     return 0;
0054 }
0055
0056 static int phy_meson8_hdmi_tx_power_on(struct phy *phy)
0057 {
0058     struct phy_meson8_hdmi_tx_priv *priv = phy_get_drvdata(phy);
0059     unsigned int i;
0060     u16 hdmi_ctl0;
0061
0062     if (clk_get_rate(priv->tmds_clk) >= 2970UL * 1000 * 1000)
0063         hdmi_ctl0 = 0x1e8b;
0064     else
0065         hdmi_ctl0 = 0x4d0b;
0066
0067     regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0,
0068              FIELD_PREP(HHI_HDMI_PHY_CNTL0_HDMI_CTL1, 0x08c3) |
0069              FIELD_PREP(HHI_HDMI_PHY_CNTL0_HDMI_CTL0, hdmi_ctl0));
0070
0071     regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, 0x0);
0072
0073     /* Reset three times, just like the vendor driver does */
0074     for (i = 0; i < 3; i++) {
0075         regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1,
0076                  HHI_HDMI_PHY_CNTL1_CLOCK_ENABLE |
0077                  HHI_HDMI_PHY_CNTL1_SOFT_RESET);
0078         usleep_range(1000, 2000);
0079
0080         regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1,
0081                  HHI_HDMI_PHY_CNTL1_CLOCK_ENABLE);
0082         usleep_range(1000, 2000);
0083     }
0084
0085     return 0;
0086 }
0087
0088 static int phy_meson8_hdmi_tx_power_off(struct phy *phy)
0089 {
0090     struct phy_meson8_hdmi_tx_priv *priv = phy_get_drvdata(phy);
0091
0092     regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0,
0093              FIELD_PREP(HHI_HDMI_PHY_CNTL0_HDMI_CTL1, 0x0841) |
0094              FIELD_PREP(HHI_HDMI_PHY_CNTL0_HDMI_CTL0, 0x8d00));
0095
0096     return 0;
0097 }
0098
0099 static const struct phy_ops phy_meson8_hdmi_tx_ops = {
0100     .init       = phy_meson8_hdmi_tx_init,
0101     .exit       = phy_meson8_hdmi_tx_exit,
0102     .power_on   = phy_meson8_hdmi_tx_power_on,
0103     .power_off  = phy_meson8_hdmi_tx_power_off,
0104     .owner      = THIS_MODULE,
0105 };
0106
0107 static int phy_meson8_hdmi_tx_probe(struct platform_device *pdev)
0108 {
0109     struct device_node *np = pdev->dev.of_node;
0110     struct phy_meson8_hdmi_tx_priv *priv;
0111     struct phy_provider *phy_provider;
0112     struct resource *res;
0113     struct phy *phy;
0114
0115     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0116     if (!res)
0117         return -EINVAL;
0118
0119     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
0120     if (!priv)
0121         return -ENOMEM;
0122
0123     priv->hhi = syscon_node_to_regmap(np->parent);
0124     if (IS_ERR(priv->hhi))
0125         return PTR_ERR(priv->hhi);
0126
0127     priv->tmds_clk = devm_clk_get(&pdev->dev, NULL);
0128     if (IS_ERR(priv->tmds_clk))
0129         return PTR_ERR(priv->tmds_clk);
0130
0131     phy = devm_phy_create(&pdev->dev, np, &phy_meson8_hdmi_tx_ops);
0132     if (IS_ERR(phy))
0133         return PTR_ERR(phy);
0134
0135     phy_set_drvdata(phy, priv);
0136
0137     phy_provider = devm_of_phy_provider_register(&pdev->dev,
0138                              of_phy_simple_xlate);
0139
0140     return PTR_ERR_OR_ZERO(phy_provider);
0141 }
0142
0143 static const struct of_device_id phy_meson8_hdmi_tx_of_match[] = {
0144     { .compatible = "amlogic,meson8-hdmi-tx-phy" },
0145     { /* sentinel */ }
0146 };
0147 MODULE_DEVICE_TABLE(of, phy_meson8_hdmi_tx_of_match);
0148
0149 static struct platform_driver phy_meson8_hdmi_tx_driver = {
0150     .probe  = phy_meson8_hdmi_tx_probe,
0151     .driver = {
0152         .name       = "phy-meson8-hdmi-tx",
0153         .of_match_table = phy_meson8_hdmi_tx_of_match,
0154     },
0155 };
0156 module_platform_driver(phy_meson8_hdmi_tx_driver);
0157
0158 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
0159 MODULE_DESCRIPTION("Meson8, Meson8b and Meson8m2 HDMI TX PHY driver");
0160 MODULE_LICENSE("GPL v2");