phy/amlogic/phy-meson-g12a-usb3-pcie.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Amlogic G12A USB3 + PCIE Combo PHY driver
0004  *
0005  * Copyright (C) 2017 Amlogic, Inc. All rights reserved
0006  * Copyright (C) 2019 BayLibre, SAS
0007  * Author: Neil Armstrong <narmstrong@baylibre.com>
0008  */
0009
0010 #include <linux/bitfield.h>
0011 #include <linux/bitops.h>
0012 #include <linux/clk.h>
0013 #include <linux/module.h>
0014 #include <linux/of_device.h>
0015 #include <linux/phy/phy.h>
0016 #include <linux/regmap.h>
0017 #include <linux/reset.h>
0018 #include <linux/platform_device.h>
0019 #include <dt-bindings/phy/phy.h>
0020
0021 #define PHY_R0                          0x00
0022     #define PHY_R0_PCIE_POWER_STATE             GENMASK(4, 0)
0023     #define PHY_R0_PCIE_USB3_SWITCH             GENMASK(6, 5)
0024
0025 #define PHY_R1                          0x04
0026     #define PHY_R1_PHY_TX1_TERM_OFFSET          GENMASK(4, 0)
0027     #define PHY_R1_PHY_TX0_TERM_OFFSET          GENMASK(9, 5)
0028     #define PHY_R1_PHY_RX1_EQ               GENMASK(12, 10)
0029     #define PHY_R1_PHY_RX0_EQ               GENMASK(15, 13)
0030     #define PHY_R1_PHY_LOS_LEVEL                GENMASK(20, 16)
0031     #define PHY_R1_PHY_LOS_BIAS             GENMASK(23, 21)
0032     #define PHY_R1_PHY_REF_CLKDIV2              BIT(24)
0033     #define PHY_R1_PHY_MPLL_MULTIPLIER          GENMASK(31, 25)
0034
0035 #define PHY_R2                          0x08
0036     #define PHY_R2_PCS_TX_DEEMPH_GEN2_6DB           GENMASK(5, 0)
0037     #define PHY_R2_PCS_TX_DEEMPH_GEN2_3P5DB         GENMASK(11, 6)
0038     #define PHY_R2_PCS_TX_DEEMPH_GEN1           GENMASK(17, 12)
0039     #define PHY_R2_PHY_TX_VBOOST_LVL            GENMASK(20, 18)
0040
0041 #define PHY_R4                          0x10
0042     #define PHY_R4_PHY_CR_WRITE             BIT(0)
0043     #define PHY_R4_PHY_CR_READ              BIT(1)
0044     #define PHY_R4_PHY_CR_DATA_IN               GENMASK(17, 2)
0045     #define PHY_R4_PHY_CR_CAP_DATA              BIT(18)
0046     #define PHY_R4_PHY_CR_CAP_ADDR              BIT(19)
0047
0048 #define PHY_R5                          0x14
0049     #define PHY_R5_PHY_CR_DATA_OUT              GENMASK(15, 0)
0050     #define PHY_R5_PHY_CR_ACK               BIT(16)
0051     #define PHY_R5_PHY_BS_OUT               BIT(17)
0052
0053 #define PCIE_RESET_DELAY                    500
0054
0055 struct phy_g12a_usb3_pcie_priv {
0056     struct regmap       *regmap;
0057     struct regmap       *regmap_cr;
0058     struct clk      *clk_ref;
0059     struct reset_control    *reset;
0060     struct phy      *phy;
0061     unsigned int        mode;
0062 };
0063
0064 static const struct regmap_config phy_g12a_usb3_pcie_regmap_conf = {
0065     .reg_bits = 8,
0066     .val_bits = 32,
0067     .reg_stride = 4,
0068     .max_register = PHY_R5,
0069 };
0070
0071 static int phy_g12a_usb3_pcie_cr_bus_addr(struct phy_g12a_usb3_pcie_priv *priv,
0072                       unsigned int addr)
0073 {
0074     unsigned int val, reg;
0075     int ret;
0076
0077     reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, addr);
0078
0079     regmap_write(priv->regmap, PHY_R4, reg);
0080     regmap_write(priv->regmap, PHY_R4, reg);
0081
0082     regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_ADDR);
0083
0084     ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
0085                        (val & PHY_R5_PHY_CR_ACK),
0086                        5, 1000);
0087     if (ret)
0088         return ret;
0089
0090     regmap_write(priv->regmap, PHY_R4, reg);
0091
0092     ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
0093                        !(val & PHY_R5_PHY_CR_ACK),
0094                        5, 1000);
0095     if (ret)
0096         return ret;
0097
0098     return 0;
0099 }
0100
0101 static int phy_g12a_usb3_pcie_cr_bus_read(void *context, unsigned int addr,
0102                       unsigned int *data)
0103 {
0104     struct phy_g12a_usb3_pcie_priv *priv = context;
0105     unsigned int val;
0106     int ret;
0107
0108     ret = phy_g12a_usb3_pcie_cr_bus_addr(priv, addr);
0109     if (ret)
0110         return ret;
0111
0112     regmap_write(priv->regmap, PHY_R4, 0);
0113     regmap_write(priv->regmap, PHY_R4, PHY_R4_PHY_CR_READ);
0114
0115     ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
0116                        (val & PHY_R5_PHY_CR_ACK),
0117                        5, 1000);
0118     if (ret)
0119         return ret;
0120
0121     *data = FIELD_GET(PHY_R5_PHY_CR_DATA_OUT, val);
0122
0123     regmap_write(priv->regmap, PHY_R4, 0);
0124
0125     ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
0126                        !(val & PHY_R5_PHY_CR_ACK),
0127                        5, 1000);
0128     if (ret)
0129         return ret;
0130
0131     return 0;
0132 }
0133
0134 static int phy_g12a_usb3_pcie_cr_bus_write(void *context, unsigned int addr,
0135                        unsigned int data)
0136 {
0137     struct phy_g12a_usb3_pcie_priv *priv = context;
0138     unsigned int val, reg;
0139     int ret;
0140
0141     ret = phy_g12a_usb3_pcie_cr_bus_addr(priv, addr);
0142     if (ret)
0143         return ret;
0144
0145     reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, data);
0146
0147     regmap_write(priv->regmap, PHY_R4, reg);
0148     regmap_write(priv->regmap, PHY_R4, reg);
0149
0150     regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_DATA);
0151
0152     ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
0153                        (val & PHY_R5_PHY_CR_ACK),
0154                        5, 1000);
0155     if (ret)
0156         return ret;
0157
0158     regmap_write(priv->regmap, PHY_R4, reg);
0159
0160     ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
0161                        (val & PHY_R5_PHY_CR_ACK) == 0,
0162                        5, 1000);
0163     if (ret)
0164         return ret;
0165
0166     regmap_write(priv->regmap, PHY_R4, reg);
0167
0168     regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_WRITE);
0169
0170     ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
0171                        (val & PHY_R5_PHY_CR_ACK),
0172                        5, 1000);
0173     if (ret)
0174         return ret;
0175
0176     regmap_write(priv->regmap, PHY_R4, reg);
0177
0178     ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
0179                        (val & PHY_R5_PHY_CR_ACK) == 0,
0180                        5, 1000);
0181     if (ret)
0182         return ret;
0183
0184     return 0;
0185 }
0186
0187 static const struct regmap_config phy_g12a_usb3_pcie_cr_regmap_conf = {
0188     .reg_bits = 16,
0189     .val_bits = 16,
0190     .reg_read = phy_g12a_usb3_pcie_cr_bus_read,
0191     .reg_write = phy_g12a_usb3_pcie_cr_bus_write,
0192     .max_register = 0xffff,
0193     .disable_locking = true,
0194 };
0195
0196 static int phy_g12a_usb3_init(struct phy *phy)
0197 {
0198     struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
0199     int data, ret;
0200
0201     ret = reset_control_reset(priv->reset);
0202     if (ret)
0203         return ret;
0204
0205     /* Switch PHY to USB3 */
0206     /* TODO figure out how to handle when PCIe was set in the bootloader */
0207     regmap_update_bits(priv->regmap, PHY_R0,
0208                PHY_R0_PCIE_USB3_SWITCH,
0209                PHY_R0_PCIE_USB3_SWITCH);
0210
0211     /*
0212      * WORKAROUND: There is SSPHY suspend bug due to
0213      * which USB enumerates
0214      * in HS mode instead of SS mode. Workaround it by asserting
0215      * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus
0216      * mode
0217      */
0218     ret = regmap_update_bits(priv->regmap_cr, 0x102d, BIT(7), BIT(7));
0219     if (ret)
0220         return ret;
0221
0222     ret = regmap_update_bits(priv->regmap_cr, 0x1010, 0xff0, 20);
0223     if (ret)
0224         return ret;
0225
0226     /*
0227      * Fix RX Equalization setting as follows
0228      * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
0229      * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
0230      * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3
0231      * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
0232      */
0233     ret = regmap_read(priv->regmap_cr, 0x1006, &data);
0234     if (ret)
0235         return ret;
0236
0237     data &= ~BIT(6);
0238     data |= BIT(7);
0239     data &= ~(0x7 << 8);
0240     data |= (0x3 << 8);
0241     data |= (1 << 11);
0242     ret = regmap_write(priv->regmap_cr, 0x1006, data);
0243     if (ret)
0244         return ret;
0245
0246     /*
0247      * Set EQ and TX launch amplitudes as follows
0248      * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22
0249      * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127
0250      * LANE0.TX_OVRD_DRV_LO.EN set to 1.
0251      */
0252     ret = regmap_read(priv->regmap_cr, 0x1002, &data);
0253     if (ret)
0254         return ret;
0255
0256     data &= ~0x3f80;
0257     data |= (0x16 << 7);
0258     data &= ~0x7f;
0259     data |= (0x7f | BIT(14));
0260     ret = regmap_write(priv->regmap_cr, 0x1002, data);
0261     if (ret)
0262         return ret;
0263
0264     /* MPLL_LOOP_CTL.PROP_CNTRL = 8 */
0265     ret = regmap_update_bits(priv->regmap_cr, 0x30, 0xf << 4, 8 << 4);
0266     if (ret)
0267         return ret;
0268
0269     regmap_update_bits(priv->regmap, PHY_R2,
0270             PHY_R2_PHY_TX_VBOOST_LVL,
0271             FIELD_PREP(PHY_R2_PHY_TX_VBOOST_LVL, 0x4));
0272
0273     regmap_update_bits(priv->regmap, PHY_R1,
0274             PHY_R1_PHY_LOS_BIAS | PHY_R1_PHY_LOS_LEVEL,
0275             FIELD_PREP(PHY_R1_PHY_LOS_BIAS, 4) |
0276             FIELD_PREP(PHY_R1_PHY_LOS_LEVEL, 9));
0277
0278     return 0;
0279 }
0280
0281 static int phy_g12a_usb3_pcie_power_on(struct phy *phy)
0282 {
0283     struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
0284
0285     if (priv->mode == PHY_TYPE_USB3)
0286         return 0;
0287
0288     regmap_update_bits(priv->regmap, PHY_R0,
0289                PHY_R0_PCIE_POWER_STATE,
0290                FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1c));
0291
0292     return 0;
0293 }
0294
0295 static int phy_g12a_usb3_pcie_power_off(struct phy *phy)
0296 {
0297     struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
0298
0299     if (priv->mode == PHY_TYPE_USB3)
0300         return 0;
0301
0302     regmap_update_bits(priv->regmap, PHY_R0,
0303                PHY_R0_PCIE_POWER_STATE,
0304                FIELD_PREP(PHY_R0_PCIE_POWER_STATE, 0x1d));
0305
0306     return 0;
0307 }
0308
0309 static int phy_g12a_usb3_pcie_reset(struct phy *phy)
0310 {
0311     struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
0312     int ret;
0313
0314     if (priv->mode == PHY_TYPE_USB3)
0315         return 0;
0316
0317     ret = reset_control_assert(priv->reset);
0318     if (ret)
0319         return ret;
0320
0321     udelay(PCIE_RESET_DELAY);
0322
0323     ret = reset_control_deassert(priv->reset);
0324     if (ret)
0325         return ret;
0326
0327     udelay(PCIE_RESET_DELAY);
0328
0329     return 0;
0330 }
0331
0332 static int phy_g12a_usb3_pcie_init(struct phy *phy)
0333 {
0334     struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
0335
0336     if (priv->mode == PHY_TYPE_USB3)
0337         return phy_g12a_usb3_init(phy);
0338
0339     return 0;
0340 }
0341
0342 static int phy_g12a_usb3_pcie_exit(struct phy *phy)
0343 {
0344     struct phy_g12a_usb3_pcie_priv *priv = phy_get_drvdata(phy);
0345
0346     if (priv->mode == PHY_TYPE_USB3)
0347         return reset_control_reset(priv->reset);
0348
0349     return 0;
0350 }
0351
0352 static struct phy *phy_g12a_usb3_pcie_xlate(struct device *dev,
0353                         struct of_phandle_args *args)
0354 {
0355     struct phy_g12a_usb3_pcie_priv *priv = dev_get_drvdata(dev);
0356     unsigned int mode;
0357
0358     if (args->args_count < 1) {
0359         dev_err(dev, "invalid number of arguments\n");
0360         return ERR_PTR(-EINVAL);
0361     }
0362
0363     mode = args->args[0];
0364
0365     if (mode != PHY_TYPE_USB3 && mode != PHY_TYPE_PCIE) {
0366         dev_err(dev, "invalid phy mode select argument\n");
0367         return ERR_PTR(-EINVAL);
0368     }
0369
0370     priv->mode = mode;
0371
0372     return priv->phy;
0373 }
0374
0375 static const struct phy_ops phy_g12a_usb3_pcie_ops = {
0376     .init       = phy_g12a_usb3_pcie_init,
0377     .exit       = phy_g12a_usb3_pcie_exit,
0378     .power_on   = phy_g12a_usb3_pcie_power_on,
0379     .power_off  = phy_g12a_usb3_pcie_power_off,
0380     .reset      = phy_g12a_usb3_pcie_reset,
0381     .owner      = THIS_MODULE,
0382 };
0383
0384 static int phy_g12a_usb3_pcie_probe(struct platform_device *pdev)
0385 {
0386     struct device *dev = &pdev->dev;
0387     struct device_node *np = dev->of_node;
0388     struct phy_g12a_usb3_pcie_priv *priv;
0389     struct phy_provider *phy_provider;
0390     void __iomem *base;
0391     int ret;
0392
0393     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0394     if (!priv)
0395         return -ENOMEM;
0396
0397     base = devm_platform_ioremap_resource(pdev, 0);
0398     if (IS_ERR(base))
0399         return PTR_ERR(base);
0400
0401     priv->regmap = devm_regmap_init_mmio(dev, base,
0402                          &phy_g12a_usb3_pcie_regmap_conf);
0403     if (IS_ERR(priv->regmap))
0404         return PTR_ERR(priv->regmap);
0405
0406     priv->regmap_cr = devm_regmap_init(dev, NULL, priv,
0407                        &phy_g12a_usb3_pcie_cr_regmap_conf);
0408     if (IS_ERR(priv->regmap_cr))
0409         return PTR_ERR(priv->regmap_cr);
0410
0411     priv->clk_ref = devm_clk_get(dev, "ref_clk");
0412     if (IS_ERR(priv->clk_ref))
0413         return PTR_ERR(priv->clk_ref);
0414
0415     ret = clk_prepare_enable(priv->clk_ref);
0416     if (ret)
0417         return ret;
0418
0419     priv->reset = devm_reset_control_array_get_exclusive(dev);
0420     if (IS_ERR(priv->reset)) {
0421         ret = PTR_ERR(priv->reset);
0422         goto err_disable_clk_ref;
0423     }
0424
0425     priv->phy = devm_phy_create(dev, np, &phy_g12a_usb3_pcie_ops);
0426     if (IS_ERR(priv->phy)) {
0427         ret = PTR_ERR(priv->phy);
0428         dev_err_probe(dev, ret, "failed to create PHY\n");
0429         goto err_disable_clk_ref;
0430     }
0431
0432     phy_set_drvdata(priv->phy, priv);
0433     dev_set_drvdata(dev, priv);
0434
0435     phy_provider = devm_of_phy_provider_register(dev,
0436                              phy_g12a_usb3_pcie_xlate);
0437     if (IS_ERR(phy_provider)) {
0438         ret = PTR_ERR(phy_provider);
0439         goto err_disable_clk_ref;
0440     }
0441
0442     return 0;
0443
0444 err_disable_clk_ref:
0445     clk_disable_unprepare(priv->clk_ref);
0446
0447     return ret;
0448 }
0449
0450 static const struct of_device_id phy_g12a_usb3_pcie_of_match[] = {
0451     { .compatible = "amlogic,g12a-usb3-pcie-phy", },
0452     { },
0453 };
0454 MODULE_DEVICE_TABLE(of, phy_g12a_usb3_pcie_of_match);
0455
0456 static struct platform_driver phy_g12a_usb3_pcie_driver = {
0457     .probe  = phy_g12a_usb3_pcie_probe,
0458     .driver = {
0459         .name       = "phy-g12a-usb3-pcie",
0460         .of_match_table = phy_g12a_usb3_pcie_of_match,
0461     },
0462 };
0463 module_platform_driver(phy_g12a_usb3_pcie_driver);
0464
0465 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
0466 MODULE_DESCRIPTION("Amlogic G12A USB3 + PCIE Combo PHY driver");
0467 MODULE_LICENSE("GPL v2");