phy/amlogic/phy-meson-g12a-usb2.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Meson G12A USB2 PHY driver
0004  *
0005  * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
0006  * Copyright (C) 2017 Amlogic, Inc. All rights reserved
0007  * Copyright (C) 2019 BayLibre, SAS
0008  * Author: Neil Armstrong <narmstrong@baylibre.com>
0009  */
0010
0011 #include <linux/bitfield.h>
0012 #include <linux/bitops.h>
0013 #include <linux/clk.h>
0014 #include <linux/delay.h>
0015 #include <linux/io.h>
0016 #include <linux/module.h>
0017 #include <linux/of_device.h>
0018 #include <linux/regmap.h>
0019 #include <linux/reset.h>
0020 #include <linux/phy/phy.h>
0021 #include <linux/platform_device.h>
0022
0023 #define PHY_CTRL_R0                     0x0
0024 #define PHY_CTRL_R1                     0x4
0025 #define PHY_CTRL_R2                     0x8
0026 #define PHY_CTRL_R3                     0xc
0027     #define PHY_CTRL_R3_SQUELCH_REF             GENMASK(1, 0)
0028     #define PHY_CTRL_R3_HSDIC_REF               GENMASK(3, 2)
0029     #define PHY_CTRL_R3_DISC_THRESH             GENMASK(7, 4)
0030
0031 #define PHY_CTRL_R4                     0x10
0032     #define PHY_CTRL_R4_CALIB_CODE_7_0          GENMASK(7, 0)
0033     #define PHY_CTRL_R4_CALIB_CODE_15_8         GENMASK(15, 8)
0034     #define PHY_CTRL_R4_CALIB_CODE_23_16            GENMASK(23, 16)
0035     #define PHY_CTRL_R4_I_C2L_CAL_EN            BIT(24)
0036     #define PHY_CTRL_R4_I_C2L_CAL_RESET_N           BIT(25)
0037     #define PHY_CTRL_R4_I_C2L_CAL_DONE          BIT(26)
0038     #define PHY_CTRL_R4_TEST_BYPASS_MODE_EN         BIT(27)
0039     #define PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0         GENMASK(29, 28)
0040     #define PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2         GENMASK(31, 30)
0041
0042 #define PHY_CTRL_R5                     0x14
0043 #define PHY_CTRL_R6                     0x18
0044 #define PHY_CTRL_R7                     0x1c
0045 #define PHY_CTRL_R8                     0x20
0046 #define PHY_CTRL_R9                     0x24
0047 #define PHY_CTRL_R10                        0x28
0048 #define PHY_CTRL_R11                        0x2c
0049 #define PHY_CTRL_R12                        0x30
0050 #define PHY_CTRL_R13                        0x34
0051     #define PHY_CTRL_R13_CUSTOM_PATTERN_19          GENMASK(7, 0)
0052     #define PHY_CTRL_R13_LOAD_STAT              BIT(14)
0053     #define PHY_CTRL_R13_UPDATE_PMA_SIGNALS         BIT(15)
0054     #define PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET     GENMASK(20, 16)
0055     #define PHY_CTRL_R13_CLEAR_HOLD_HS_DISCONNECT       BIT(21)
0056     #define PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_VAL     BIT(22)
0057     #define PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_EN      BIT(23)
0058     #define PHY_CTRL_R13_I_C2L_HS_EN            BIT(24)
0059     #define PHY_CTRL_R13_I_C2L_FS_EN            BIT(25)
0060     #define PHY_CTRL_R13_I_C2L_LS_EN            BIT(26)
0061     #define PHY_CTRL_R13_I_C2L_HS_OE            BIT(27)
0062     #define PHY_CTRL_R13_I_C2L_FS_OE            BIT(28)
0063     #define PHY_CTRL_R13_I_C2L_HS_RX_EN         BIT(29)
0064     #define PHY_CTRL_R13_I_C2L_FSLS_RX_EN           BIT(30)
0065
0066 #define PHY_CTRL_R14                        0x38
0067     #define PHY_CTRL_R14_I_RDP_EN               BIT(0)
0068     #define PHY_CTRL_R14_I_RPU_SW1_EN           BIT(1)
0069     #define PHY_CTRL_R14_I_RPU_SW2_EN           GENMASK(3, 2)
0070     #define PHY_CTRL_R14_PG_RSTN                BIT(4)
0071     #define PHY_CTRL_R14_I_C2L_DATA_16_8            BIT(5)
0072     #define PHY_CTRL_R14_I_C2L_ASSERT_SINGLE_EN_ZERO    BIT(6)
0073     #define PHY_CTRL_R14_BYPASS_CTRL_7_0            GENMASK(15, 8)
0074     #define PHY_CTRL_R14_BYPASS_CTRL_15_8           GENMASK(23, 16)
0075
0076 #define PHY_CTRL_R15                        0x3c
0077 #define PHY_CTRL_R16                        0x40
0078     #define PHY_CTRL_R16_MPLL_M             GENMASK(8, 0)
0079     #define PHY_CTRL_R16_MPLL_N             GENMASK(14, 10)
0080     #define PHY_CTRL_R16_MPLL_TDC_MODE          BIT(20)
0081     #define PHY_CTRL_R16_MPLL_SDM_EN            BIT(21)
0082     #define PHY_CTRL_R16_MPLL_LOAD              BIT(22)
0083     #define PHY_CTRL_R16_MPLL_DCO_SDM_EN            BIT(23)
0084     #define PHY_CTRL_R16_MPLL_LOCK_LONG         GENMASK(25, 24)
0085     #define PHY_CTRL_R16_MPLL_LOCK_F            BIT(26)
0086     #define PHY_CTRL_R16_MPLL_FAST_LOCK         BIT(27)
0087     #define PHY_CTRL_R16_MPLL_EN                BIT(28)
0088     #define PHY_CTRL_R16_MPLL_RESET             BIT(29)
0089     #define PHY_CTRL_R16_MPLL_LOCK              BIT(30)
0090     #define PHY_CTRL_R16_MPLL_LOCK_DIG          BIT(31)
0091
0092 #define PHY_CTRL_R17                        0x44
0093     #define PHY_CTRL_R17_MPLL_FRAC_IN           GENMASK(13, 0)
0094     #define PHY_CTRL_R17_MPLL_FIX_EN            BIT(16)
0095     #define PHY_CTRL_R17_MPLL_LAMBDA1           GENMASK(19, 17)
0096     #define PHY_CTRL_R17_MPLL_LAMBDA0           GENMASK(22, 20)
0097     #define PHY_CTRL_R17_MPLL_FILTER_MODE           BIT(23)
0098     #define PHY_CTRL_R17_MPLL_FILTER_PVT2           GENMASK(27, 24)
0099     #define PHY_CTRL_R17_MPLL_FILTER_PVT1           GENMASK(31, 28)
0100
0101 #define PHY_CTRL_R18                        0x48
0102     #define PHY_CTRL_R18_MPLL_LKW_SEL           GENMASK(1, 0)
0103     #define PHY_CTRL_R18_MPLL_LK_W              GENMASK(5, 2)
0104     #define PHY_CTRL_R18_MPLL_LK_S              GENMASK(11, 6)
0105     #define PHY_CTRL_R18_MPLL_DCO_M_EN          BIT(12)
0106     #define PHY_CTRL_R18_MPLL_DCO_CLK_SEL           BIT(13)
0107     #define PHY_CTRL_R18_MPLL_PFD_GAIN          GENMASK(15, 14)
0108     #define PHY_CTRL_R18_MPLL_ROU               GENMASK(18, 16)
0109     #define PHY_CTRL_R18_MPLL_DATA_SEL          GENMASK(21, 19)
0110     #define PHY_CTRL_R18_MPLL_BIAS_ADJ          GENMASK(23, 22)
0111     #define PHY_CTRL_R18_MPLL_BB_MODE           GENMASK(25, 24)
0112     #define PHY_CTRL_R18_MPLL_ALPHA             GENMASK(28, 26)
0113     #define PHY_CTRL_R18_MPLL_ADJ_LDO           GENMASK(30, 29)
0114     #define PHY_CTRL_R18_MPLL_ACG_RANGE         BIT(31)
0115
0116 #define PHY_CTRL_R19                        0x4c
0117 #define PHY_CTRL_R20                        0x50
0118     #define PHY_CTRL_R20_USB2_IDDET_EN          BIT(0)
0119     #define PHY_CTRL_R20_USB2_OTG_VBUS_TRIM_2_0     GENMASK(3, 1)
0120     #define PHY_CTRL_R20_USB2_OTG_VBUSDET_EN        BIT(4)
0121     #define PHY_CTRL_R20_USB2_AMON_EN           BIT(5)
0122     #define PHY_CTRL_R20_USB2_CAL_CODE_R5           BIT(6)
0123     #define PHY_CTRL_R20_BYPASS_OTG_DET         BIT(7)
0124     #define PHY_CTRL_R20_USB2_DMON_EN           BIT(8)
0125     #define PHY_CTRL_R20_USB2_DMON_SEL_3_0          GENMASK(12, 9)
0126     #define PHY_CTRL_R20_USB2_EDGE_DRV_EN           BIT(13)
0127     #define PHY_CTRL_R20_USB2_EDGE_DRV_TRIM_1_0     GENMASK(15, 14)
0128     #define PHY_CTRL_R20_USB2_BGR_ADJ_4_0           GENMASK(20, 16)
0129     #define PHY_CTRL_R20_USB2_BGR_START         BIT(21)
0130     #define PHY_CTRL_R20_USB2_BGR_VREF_4_0          GENMASK(28, 24)
0131     #define PHY_CTRL_R20_USB2_BGR_DBG_1_0           GENMASK(30, 29)
0132     #define PHY_CTRL_R20_BYPASS_CAL_DONE_R5         BIT(31)
0133
0134 #define PHY_CTRL_R21                        0x54
0135     #define PHY_CTRL_R21_USB2_BGR_FORCE         BIT(0)
0136     #define PHY_CTRL_R21_USB2_CAL_ACK_EN            BIT(1)
0137     #define PHY_CTRL_R21_USB2_OTG_ACA_EN            BIT(2)
0138     #define PHY_CTRL_R21_USB2_TX_STRG_PD            BIT(3)
0139     #define PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0      GENMASK(5, 4)
0140     #define PHY_CTRL_R21_BYPASS_UTMI_CNTR           GENMASK(15, 6)
0141     #define PHY_CTRL_R21_BYPASS_UTMI_REG            GENMASK(25, 20)
0142
0143 #define PHY_CTRL_R22                        0x58
0144 #define PHY_CTRL_R23                        0x5c
0145
0146 #define RESET_COMPLETE_TIME                 1000
0147 #define PLL_RESET_COMPLETE_TIME                 100
0148
0149 enum meson_soc_id {
0150     MESON_SOC_G12A  = 0,
0151     MESON_SOC_A1,
0152 };
0153
0154 struct phy_meson_g12a_usb2_priv {
0155     struct device       *dev;
0156     struct regmap       *regmap;
0157     struct clk      *clk;
0158     struct reset_control    *reset;
0159     int                     soc_id;
0160 };
0161
0162 static const struct regmap_config phy_meson_g12a_usb2_regmap_conf = {
0163     .reg_bits = 8,
0164     .val_bits = 32,
0165     .reg_stride = 4,
0166     .max_register = PHY_CTRL_R23,
0167 };
0168
0169 static int phy_meson_g12a_usb2_init(struct phy *phy)
0170 {
0171     struct phy_meson_g12a_usb2_priv *priv = phy_get_drvdata(phy);
0172     int ret;
0173     unsigned int value;
0174
0175     ret = reset_control_reset(priv->reset);
0176     if (ret)
0177         return ret;
0178
0179     udelay(RESET_COMPLETE_TIME);
0180
0181     /* usb2_otg_aca_en == 0 */
0182     regmap_update_bits(priv->regmap, PHY_CTRL_R21,
0183                PHY_CTRL_R21_USB2_OTG_ACA_EN, 0);
0184
0185     /* PLL Setup : 24MHz * 20 / 1 = 480MHz */
0186     regmap_write(priv->regmap, PHY_CTRL_R16,
0187              FIELD_PREP(PHY_CTRL_R16_MPLL_M, 20) |
0188              FIELD_PREP(PHY_CTRL_R16_MPLL_N, 1) |
0189              PHY_CTRL_R16_MPLL_LOAD |
0190              FIELD_PREP(PHY_CTRL_R16_MPLL_LOCK_LONG, 1) |
0191              PHY_CTRL_R16_MPLL_FAST_LOCK |
0192              PHY_CTRL_R16_MPLL_EN |
0193              PHY_CTRL_R16_MPLL_RESET);
0194
0195     regmap_write(priv->regmap, PHY_CTRL_R17,
0196              FIELD_PREP(PHY_CTRL_R17_MPLL_FRAC_IN, 0) |
0197              FIELD_PREP(PHY_CTRL_R17_MPLL_LAMBDA1, 7) |
0198              FIELD_PREP(PHY_CTRL_R17_MPLL_LAMBDA0, 7) |
0199              FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT2, 2) |
0200              FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT1, 9));
0201
0202     value = FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) |
0203         FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) |
0204         FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) |
0205         FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) |
0206         FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) |
0207         FIELD_PREP(PHY_CTRL_R18_MPLL_DATA_SEL, 3) |
0208         FIELD_PREP(PHY_CTRL_R18_MPLL_BIAS_ADJ, 1) |
0209         FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) |
0210         FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) |
0211         FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) |
0212         PHY_CTRL_R18_MPLL_ACG_RANGE;
0213
0214     if (priv->soc_id == MESON_SOC_A1)
0215         value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL;
0216
0217     regmap_write(priv->regmap, PHY_CTRL_R18, value);
0218
0219     udelay(PLL_RESET_COMPLETE_TIME);
0220
0221     /* UnReset PLL */
0222     regmap_write(priv->regmap, PHY_CTRL_R16,
0223              FIELD_PREP(PHY_CTRL_R16_MPLL_M, 20) |
0224              FIELD_PREP(PHY_CTRL_R16_MPLL_N, 1) |
0225              PHY_CTRL_R16_MPLL_LOAD |
0226              FIELD_PREP(PHY_CTRL_R16_MPLL_LOCK_LONG, 1) |
0227              PHY_CTRL_R16_MPLL_FAST_LOCK |
0228              PHY_CTRL_R16_MPLL_EN);
0229
0230     /* PHY Tuning */
0231     regmap_write(priv->regmap, PHY_CTRL_R20,
0232              FIELD_PREP(PHY_CTRL_R20_USB2_OTG_VBUS_TRIM_2_0, 4) |
0233              PHY_CTRL_R20_USB2_OTG_VBUSDET_EN |
0234              FIELD_PREP(PHY_CTRL_R20_USB2_DMON_SEL_3_0, 15) |
0235              PHY_CTRL_R20_USB2_EDGE_DRV_EN |
0236              FIELD_PREP(PHY_CTRL_R20_USB2_EDGE_DRV_TRIM_1_0, 3) |
0237              FIELD_PREP(PHY_CTRL_R20_USB2_BGR_ADJ_4_0, 0) |
0238              FIELD_PREP(PHY_CTRL_R20_USB2_BGR_VREF_4_0, 0) |
0239              FIELD_PREP(PHY_CTRL_R20_USB2_BGR_DBG_1_0, 0));
0240
0241     if (priv->soc_id == MESON_SOC_G12A)
0242         regmap_write(priv->regmap, PHY_CTRL_R4,
0243                  FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) |
0244                  FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) |
0245                  FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) |
0246                  PHY_CTRL_R4_TEST_BYPASS_MODE_EN |
0247                  FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) |
0248                  FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0));
0249     else if (priv->soc_id == MESON_SOC_A1) {
0250         regmap_write(priv->regmap, PHY_CTRL_R21,
0251                  PHY_CTRL_R21_USB2_CAL_ACK_EN |
0252                  PHY_CTRL_R21_USB2_TX_STRG_PD |
0253                  FIELD_PREP(PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0, 2));
0254
0255         /* Analog Settings */
0256         regmap_write(priv->regmap, PHY_CTRL_R13,
0257                  FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
0258     }
0259
0260     /* Tuning Disconnect Threshold */
0261     regmap_write(priv->regmap, PHY_CTRL_R3,
0262              FIELD_PREP(PHY_CTRL_R3_SQUELCH_REF, 0) |
0263              FIELD_PREP(PHY_CTRL_R3_HSDIC_REF, 1) |
0264              FIELD_PREP(PHY_CTRL_R3_DISC_THRESH, 3));
0265
0266     if (priv->soc_id == MESON_SOC_G12A) {
0267         /* Analog Settings */
0268         regmap_write(priv->regmap, PHY_CTRL_R14, 0);
0269         regmap_write(priv->regmap, PHY_CTRL_R13,
0270                  PHY_CTRL_R13_UPDATE_PMA_SIGNALS |
0271                  FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
0272     }
0273
0274     return 0;
0275 }
0276
0277 static int phy_meson_g12a_usb2_exit(struct phy *phy)
0278 {
0279     struct phy_meson_g12a_usb2_priv *priv = phy_get_drvdata(phy);
0280
0281     return reset_control_reset(priv->reset);
0282 }
0283
0284 /* set_mode is not needed, mode setting is handled via the UTMI bus */
0285 static const struct phy_ops phy_meson_g12a_usb2_ops = {
0286     .init       = phy_meson_g12a_usb2_init,
0287     .exit       = phy_meson_g12a_usb2_exit,
0288     .owner      = THIS_MODULE,
0289 };
0290
0291 static int phy_meson_g12a_usb2_probe(struct platform_device *pdev)
0292 {
0293     struct device *dev = &pdev->dev;
0294     struct phy_provider *phy_provider;
0295     struct phy_meson_g12a_usb2_priv *priv;
0296     struct phy *phy;
0297     void __iomem *base;
0298     int ret;
0299
0300     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0301     if (!priv)
0302         return -ENOMEM;
0303
0304     priv->dev = dev;
0305     platform_set_drvdata(pdev, priv);
0306
0307     base = devm_platform_ioremap_resource(pdev, 0);
0308     if (IS_ERR(base))
0309         return PTR_ERR(base);
0310
0311     priv->soc_id = (enum meson_soc_id)of_device_get_match_data(&pdev->dev);
0312
0313     priv->regmap = devm_regmap_init_mmio(dev, base,
0314                          &phy_meson_g12a_usb2_regmap_conf);
0315     if (IS_ERR(priv->regmap))
0316         return PTR_ERR(priv->regmap);
0317
0318     priv->clk = devm_clk_get(dev, "xtal");
0319     if (IS_ERR(priv->clk))
0320         return PTR_ERR(priv->clk);
0321
0322     priv->reset = devm_reset_control_get(dev, "phy");
0323     if (IS_ERR(priv->reset))
0324         return PTR_ERR(priv->reset);
0325
0326     ret = reset_control_deassert(priv->reset);
0327     if (ret)
0328         return ret;
0329
0330     phy = devm_phy_create(dev, NULL, &phy_meson_g12a_usb2_ops);
0331     if (IS_ERR(phy)) {
0332         ret = PTR_ERR(phy);
0333         if (ret != -EPROBE_DEFER)
0334             dev_err(dev, "failed to create PHY\n");
0335
0336         return ret;
0337     }
0338
0339     phy_set_bus_width(phy, 8);
0340     phy_set_drvdata(phy, priv);
0341
0342     phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0343
0344     return PTR_ERR_OR_ZERO(phy_provider);
0345 }
0346
0347 static const struct of_device_id phy_meson_g12a_usb2_of_match[] = {
0348     {
0349         .compatible = "amlogic,g12a-usb2-phy",
0350         .data = (void *)MESON_SOC_G12A,
0351     },
0352     {
0353         .compatible = "amlogic,a1-usb2-phy",
0354         .data = (void *)MESON_SOC_A1,
0355     },
0356     { /* Sentinel */ }
0357 };
0358 MODULE_DEVICE_TABLE(of, phy_meson_g12a_usb2_of_match);
0359
0360 static struct platform_driver phy_meson_g12a_usb2_driver = {
0361     .probe  = phy_meson_g12a_usb2_probe,
0362     .driver = {
0363         .name       = "phy-meson-g12a-usb2",
0364         .of_match_table = phy_meson_g12a_usb2_of_match,
0365     },
0366 };
0367 module_platform_driver(phy_meson_g12a_usb2_driver);
0368
0369 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
0370 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
0371 MODULE_DESCRIPTION("Meson G12A USB2 PHY driver");
0372 MODULE_LICENSE("GPL v2");