phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Meson G12A MIPI DSI Analog PHY
0004  *
0005  * Copyright (C) 2018 Amlogic, Inc. All rights reserved
0006  * Copyright (C) 2022 BayLibre, SAS
0007  * Author: Neil Armstrong <narmstrong@baylibre.com>
0008  */
0009 #include <linux/bitfield.h>
0010 #include <linux/bitops.h>
0011 #include <linux/module.h>
0012 #include <linux/phy/phy.h>
0013 #include <linux/regmap.h>
0014 #include <linux/delay.h>
0015 #include <linux/mfd/syscon.h>
0016 #include <linux/platform_device.h>
0017 #include <dt-bindings/phy/phy.h>
0018
0019 #define HHI_MIPI_CNTL0 0x00
0020 #define     HHI_MIPI_CNTL0_DIF_REF_CTL1 GENMASK(31, 16)
0021 #define     HHI_MIPI_CNTL0_DIF_REF_CTL0 GENMASK(15, 0)
0022
0023 #define HHI_MIPI_CNTL1 0x04
0024 #define     HHI_MIPI_CNTL1_BANDGAP      BIT(16)
0025 #define     HHI_MIPI_CNTL2_DIF_REF_CTL2 GENMASK(15, 0)
0026
0027 #define HHI_MIPI_CNTL2 0x08
0028 #define     HHI_MIPI_CNTL2_DIF_TX_CTL1  GENMASK(31, 16)
0029 #define     HHI_MIPI_CNTL2_CH_EN        GENMASK(15, 11)
0030 #define     HHI_MIPI_CNTL2_DIF_TX_CTL0  GENMASK(10, 0)
0031
0032 #define DSI_LANE_0              BIT(4)
0033 #define DSI_LANE_1              BIT(3)
0034 #define DSI_LANE_CLK                BIT(2)
0035 #define DSI_LANE_2              BIT(1)
0036 #define DSI_LANE_3              BIT(0)
0037
0038 struct phy_g12a_mipi_dphy_analog_priv {
0039     struct phy *phy;
0040     struct regmap *regmap;
0041     struct phy_configure_opts_mipi_dphy config;
0042 };
0043
0044 static int phy_g12a_mipi_dphy_analog_configure(struct phy *phy,
0045                            union phy_configure_opts *opts)
0046 {
0047     struct phy_g12a_mipi_dphy_analog_priv *priv = phy_get_drvdata(phy);
0048     int ret;
0049
0050     ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);
0051     if (ret)
0052         return ret;
0053
0054     memcpy(&priv->config, opts, sizeof(priv->config));
0055
0056     return 0;
0057 }
0058
0059 static int phy_g12a_mipi_dphy_analog_power_on(struct phy *phy)
0060 {
0061     struct phy_g12a_mipi_dphy_analog_priv *priv = phy_get_drvdata(phy);
0062     unsigned int reg;
0063
0064     regmap_write(priv->regmap, HHI_MIPI_CNTL0,
0065              FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL0, 0x8) |
0066              FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL1, 0xa487));
0067
0068     regmap_write(priv->regmap, HHI_MIPI_CNTL1,
0069              FIELD_PREP(HHI_MIPI_CNTL2_DIF_REF_CTL2, 0x2e) |
0070              HHI_MIPI_CNTL1_BANDGAP);
0071
0072     regmap_write(priv->regmap, HHI_MIPI_CNTL2,
0073              FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL0, 0x459) |
0074              FIELD_PREP(HHI_MIPI_CNTL2_DIF_TX_CTL1, 0x2680));
0075
0076     reg = DSI_LANE_CLK;
0077     switch (priv->config.lanes) {
0078     case 4:
0079         reg |= DSI_LANE_3;
0080         fallthrough;
0081     case 3:
0082         reg |= DSI_LANE_2;
0083         fallthrough;
0084     case 2:
0085         reg |= DSI_LANE_1;
0086         fallthrough;
0087     case 1:
0088         reg |= DSI_LANE_0;
0089         break;
0090     default:
0091         reg = 0;
0092     }
0093
0094     regmap_update_bits(priv->regmap, HHI_MIPI_CNTL2,
0095                HHI_MIPI_CNTL2_CH_EN,
0096                FIELD_PREP(HHI_MIPI_CNTL2_CH_EN, reg));
0097
0098     return 0;
0099 }
0100
0101 static int phy_g12a_mipi_dphy_analog_power_off(struct phy *phy)
0102 {
0103     struct phy_g12a_mipi_dphy_analog_priv *priv = phy_get_drvdata(phy);
0104
0105     regmap_write(priv->regmap, HHI_MIPI_CNTL0, 0);
0106     regmap_write(priv->regmap, HHI_MIPI_CNTL1, 0);
0107     regmap_write(priv->regmap, HHI_MIPI_CNTL2, 0);
0108
0109     return 0;
0110 }
0111
0112 static const struct phy_ops phy_g12a_mipi_dphy_analog_ops = {
0113     .configure = phy_g12a_mipi_dphy_analog_configure,
0114     .power_on = phy_g12a_mipi_dphy_analog_power_on,
0115     .power_off = phy_g12a_mipi_dphy_analog_power_off,
0116     .owner = THIS_MODULE,
0117 };
0118
0119 static int phy_g12a_mipi_dphy_analog_probe(struct platform_device *pdev)
0120 {
0121     struct phy_provider *phy;
0122     struct device *dev = &pdev->dev;
0123     struct phy_g12a_mipi_dphy_analog_priv *priv;
0124     struct device_node *np = dev->of_node, *parent_np;
0125     struct regmap *map;
0126
0127     priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL);
0128     if (!priv)
0129         return -ENOMEM;
0130
0131     /* Get the hhi system controller node */
0132     parent_np = of_get_parent(np);
0133     map = syscon_node_to_regmap(parent_np);
0134     of_node_put(parent_np);
0135     if (IS_ERR(map))
0136         return dev_err_probe(dev, PTR_ERR(map), "failed to get HHI regmap\n");
0137
0138     priv->regmap = map;
0139
0140     priv->phy = devm_phy_create(dev, np, &phy_g12a_mipi_dphy_analog_ops);
0141     if (IS_ERR(priv->phy))
0142         return dev_err_probe(dev, PTR_ERR(priv->phy), "failed to create PHY\n");
0143
0144     phy_set_drvdata(priv->phy, priv);
0145     dev_set_drvdata(dev, priv);
0146
0147     phy = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0148
0149     return PTR_ERR_OR_ZERO(phy);
0150 }
0151
0152 static const struct of_device_id phy_g12a_mipi_dphy_analog_of_match[] = {
0153     {
0154         .compatible = "amlogic,g12a-mipi-dphy-analog",
0155     },
0156     { /* sentinel */ }
0157 };
0158 MODULE_DEVICE_TABLE(of, phy_g12a_mipi_dphy_analog_of_match);
0159
0160 static struct platform_driver phy_g12a_mipi_dphy_analog_driver = {
0161     .probe = phy_g12a_mipi_dphy_analog_probe,
0162     .driver = {
0163         .name = "phy-meson-g12a-mipi-dphy-analog",
0164         .of_match_table = phy_g12a_mipi_dphy_analog_of_match,
0165     },
0166 };
0167 module_platform_driver(phy_g12a_mipi_dphy_analog_driver);
0168
0169 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
0170 MODULE_DESCRIPTION("Meson G12A MIPI Analog D-PHY driver");
0171 MODULE_LICENSE("GPL v2");