phy/amlogic/phy-meson-axg-pcie.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Amlogic AXG PCIE PHY driver
0004  *
0005  * Copyright (C) 2020 Remi Pommarel <repk@triplefau.lt>
0006  */
0007 #include <linux/module.h>
0008 #include <linux/phy/phy.h>
0009 #include <linux/regmap.h>
0010 #include <linux/reset.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/bitfield.h>
0013 #include <dt-bindings/phy/phy.h>
0014
0015 #define MESON_PCIE_REG0 0x00
0016 #define     MESON_PCIE_COMMON_CLK   BIT(4)
0017 #define     MESON_PCIE_PORT_SEL GENMASK(3, 2)
0018 #define     MESON_PCIE_CLK      BIT(1)
0019 #define     MESON_PCIE_POWERDOWN    BIT(0)
0020
0021 #define MESON_PCIE_TWO_X1       FIELD_PREP(MESON_PCIE_PORT_SEL, 0x3)
0022 #define MESON_PCIE_COMMON_REF_CLK   FIELD_PREP(MESON_PCIE_COMMON_CLK, 0x1)
0023 #define MESON_PCIE_PHY_INIT     (MESON_PCIE_TWO_X1 |        \
0024                      MESON_PCIE_COMMON_REF_CLK)
0025 #define MESON_PCIE_RESET_DELAY      500
0026
0027 struct phy_axg_pcie_priv {
0028     struct phy *phy;
0029     struct phy *analog;
0030     struct regmap *regmap;
0031     struct reset_control *reset;
0032 };
0033
0034 static const struct regmap_config phy_axg_pcie_regmap_conf = {
0035     .reg_bits = 8,
0036     .val_bits = 32,
0037     .reg_stride = 4,
0038     .max_register = MESON_PCIE_REG0,
0039 };
0040
0041 static int phy_axg_pcie_power_on(struct phy *phy)
0042 {
0043     struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy);
0044     int ret;
0045
0046     ret = phy_power_on(priv->analog);
0047     if (ret != 0)
0048         return ret;
0049
0050     regmap_update_bits(priv->regmap, MESON_PCIE_REG0,
0051                MESON_PCIE_POWERDOWN, 0);
0052     return 0;
0053 }
0054
0055 static int phy_axg_pcie_power_off(struct phy *phy)
0056 {
0057     struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy);
0058     int ret;
0059
0060     ret = phy_power_off(priv->analog);
0061     if (ret != 0)
0062         return ret;
0063
0064     regmap_update_bits(priv->regmap, MESON_PCIE_REG0,
0065                MESON_PCIE_POWERDOWN, 1);
0066     return 0;
0067 }
0068
0069 static int phy_axg_pcie_init(struct phy *phy)
0070 {
0071     struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy);
0072     int ret;
0073
0074     ret = phy_init(priv->analog);
0075     if (ret != 0)
0076         return ret;
0077
0078     regmap_write(priv->regmap, MESON_PCIE_REG0, MESON_PCIE_PHY_INIT);
0079     return reset_control_reset(priv->reset);
0080 }
0081
0082 static int phy_axg_pcie_exit(struct phy *phy)
0083 {
0084     struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy);
0085     int ret;
0086
0087     ret = phy_exit(priv->analog);
0088     if (ret != 0)
0089         return ret;
0090
0091     return reset_control_reset(priv->reset);
0092 }
0093
0094 static int phy_axg_pcie_reset(struct phy *phy)
0095 {
0096     struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy);
0097     int ret = 0;
0098
0099     ret = phy_reset(priv->analog);
0100     if (ret != 0)
0101         goto out;
0102
0103     ret = reset_control_assert(priv->reset);
0104     if (ret != 0)
0105         goto out;
0106     udelay(MESON_PCIE_RESET_DELAY);
0107
0108     ret = reset_control_deassert(priv->reset);
0109     if (ret != 0)
0110         goto out;
0111     udelay(MESON_PCIE_RESET_DELAY);
0112
0113 out:
0114     return ret;
0115 }
0116
0117 static const struct phy_ops phy_axg_pcie_ops = {
0118     .init = phy_axg_pcie_init,
0119     .exit = phy_axg_pcie_exit,
0120     .power_on = phy_axg_pcie_power_on,
0121     .power_off = phy_axg_pcie_power_off,
0122     .reset = phy_axg_pcie_reset,
0123     .owner = THIS_MODULE,
0124 };
0125
0126 static int phy_axg_pcie_probe(struct platform_device *pdev)
0127 {
0128     struct phy_provider *pphy;
0129     struct device *dev = &pdev->dev;
0130     struct phy_axg_pcie_priv *priv;
0131     struct device_node *np = dev->of_node;
0132     void __iomem *base;
0133     int ret;
0134
0135     priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL);
0136     if (!priv)
0137         return -ENOMEM;
0138
0139     priv->phy = devm_phy_create(dev, np, &phy_axg_pcie_ops);
0140     if (IS_ERR(priv->phy)) {
0141         ret = PTR_ERR(priv->phy);
0142         if (ret != -EPROBE_DEFER)
0143             dev_err(dev, "failed to create PHY\n");
0144         return ret;
0145     }
0146
0147     base = devm_platform_ioremap_resource(pdev, 0);
0148     if (IS_ERR(base))
0149         return PTR_ERR(base);
0150
0151     priv->regmap = devm_regmap_init_mmio(dev, base,
0152                          &phy_axg_pcie_regmap_conf);
0153     if (IS_ERR(priv->regmap))
0154         return PTR_ERR(priv->regmap);
0155
0156     priv->reset = devm_reset_control_array_get_exclusive(dev);
0157     if (IS_ERR(priv->reset))
0158         return PTR_ERR(priv->reset);
0159
0160     priv->analog = devm_phy_get(dev, "analog");
0161     if (IS_ERR(priv->analog))
0162         return PTR_ERR(priv->analog);
0163
0164     phy_set_drvdata(priv->phy, priv);
0165     dev_set_drvdata(dev, priv);
0166     pphy = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0167
0168     return PTR_ERR_OR_ZERO(pphy);
0169 }
0170
0171 static const struct of_device_id phy_axg_pcie_of_match[] = {
0172     {
0173         .compatible = "amlogic,axg-pcie-phy",
0174     },
0175     { },
0176 };
0177 MODULE_DEVICE_TABLE(of, phy_axg_pcie_of_match);
0178
0179 static struct platform_driver phy_axg_pcie_driver = {
0180     .probe = phy_axg_pcie_probe,
0181     .driver = {
0182         .name = "phy-axg-pcie",
0183         .of_match_table = phy_axg_pcie_of_match,
0184     },
0185 };
0186 module_platform_driver(phy_axg_pcie_driver);
0187
0188 MODULE_AUTHOR("Remi Pommarel <repk@triplefau.lt>");
0189 MODULE_DESCRIPTION("Amlogic AXG PCIE PHY driver");
0190 MODULE_LICENSE("GPL v2");