phy/amlogic/phy-meson-axg-mipi-pcie-analog.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Amlogic AXG MIPI + PCIE analog PHY driver
0004  *
0005  * Copyright (C) 2019 Remi Pommarel <repk@triplefau.lt>
0006  */
0007 #include <linux/bitfield.h>
0008 #include <linux/bitops.h>
0009 #include <linux/module.h>
0010 #include <linux/phy/phy.h>
0011 #include <linux/regmap.h>
0012 #include <linux/delay.h>
0013 #include <linux/mfd/syscon.h>
0014 #include <linux/platform_device.h>
0015 #include <dt-bindings/phy/phy.h>
0016
0017 #define HHI_MIPI_CNTL0 0x00
0018 #define     HHI_MIPI_CNTL0_COMMON_BLOCK GENMASK(31, 28)
0019 #define     HHI_MIPI_CNTL0_ENABLE       BIT(29)
0020 #define     HHI_MIPI_CNTL0_BANDGAP      BIT(26)
0021 #define     HHI_MIPI_CNTL0_DIF_REF_CTL1 GENMASK(25, 16)
0022 #define     HHI_MIPI_CNTL0_DIF_REF_CTL0 GENMASK(15, 0)
0023
0024 #define HHI_MIPI_CNTL1 0x04
0025 #define     HHI_MIPI_CNTL1_CH0_CML_PDR_EN   BIT(12)
0026 #define     HHI_MIPI_CNTL1_LP_ABILITY   GENMASK(5, 4)
0027 #define     HHI_MIPI_CNTL1_LP_RESISTER  BIT(3)
0028 #define     HHI_MIPI_CNTL1_INPUT_SETTING    BIT(2)
0029 #define     HHI_MIPI_CNTL1_INPUT_SEL    BIT(1)
0030 #define     HHI_MIPI_CNTL1_PRBS7_EN     BIT(0)
0031
0032 #define HHI_MIPI_CNTL2 0x08
0033 #define     HHI_MIPI_CNTL2_CH_PU        GENMASK(31, 25)
0034 #define     HHI_MIPI_CNTL2_CH_CTL       GENMASK(24, 19)
0035 #define     HHI_MIPI_CNTL2_CH0_DIGDR_EN BIT(18)
0036 #define     HHI_MIPI_CNTL2_CH_DIGDR_EN  BIT(17)
0037 #define     HHI_MIPI_CNTL2_LPULPS_EN    BIT(16)
0038 #define     HHI_MIPI_CNTL2_CH_EN        GENMASK(15, 11)
0039 #define     HHI_MIPI_CNTL2_CH0_LP_CTL   GENMASK(10, 1)
0040
0041 #define DSI_LANE_0              BIT(4)
0042 #define DSI_LANE_1              BIT(3)
0043 #define DSI_LANE_CLK            BIT(2)
0044 #define DSI_LANE_2              BIT(1)
0045 #define DSI_LANE_3              BIT(0)
0046
0047 struct phy_axg_mipi_pcie_analog_priv {
0048     struct phy *phy;
0049     struct regmap *regmap;
0050     bool dsi_configured;
0051     bool dsi_enabled;
0052     bool powered;
0053     struct phy_configure_opts_mipi_dphy config;
0054 };
0055
0056 static void phy_bandgap_enable(struct phy_axg_mipi_pcie_analog_priv *priv)
0057 {
0058     regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
0059             HHI_MIPI_CNTL0_BANDGAP, HHI_MIPI_CNTL0_BANDGAP);
0060
0061     regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
0062             HHI_MIPI_CNTL0_ENABLE, HHI_MIPI_CNTL0_ENABLE);
0063 }
0064
0065 static void phy_bandgap_disable(struct phy_axg_mipi_pcie_analog_priv *priv)
0066 {
0067     regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
0068             HHI_MIPI_CNTL0_BANDGAP, 0);
0069     regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
0070             HHI_MIPI_CNTL0_ENABLE, 0);
0071 }
0072
0073 static void phy_dsi_analog_enable(struct phy_axg_mipi_pcie_analog_priv *priv)
0074 {
0075     u32 reg;
0076
0077     regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
0078                HHI_MIPI_CNTL0_DIF_REF_CTL1,
0079                FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL1, 0x1b8));
0080     regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
0081                BIT(31), BIT(31));
0082     regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
0083                HHI_MIPI_CNTL0_DIF_REF_CTL0,
0084                FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL0, 0x8));
0085
0086     regmap_write(priv->regmap, HHI_MIPI_CNTL1, 0x001e);
0087
0088     regmap_write(priv->regmap, HHI_MIPI_CNTL2,
0089              (0x26e0 << 16) | (0x459 << 0));
0090
0091     reg = DSI_LANE_CLK;
0092     switch (priv->config.lanes) {
0093     case 4:
0094         reg |= DSI_LANE_3;
0095         fallthrough;
0096     case 3:
0097         reg |= DSI_LANE_2;
0098         fallthrough;
0099     case 2:
0100         reg |= DSI_LANE_1;
0101         fallthrough;
0102     case 1:
0103         reg |= DSI_LANE_0;
0104         break;
0105     default:
0106         reg = 0;
0107     }
0108
0109     regmap_update_bits(priv->regmap, HHI_MIPI_CNTL2,
0110                HHI_MIPI_CNTL2_CH_EN,
0111                FIELD_PREP(HHI_MIPI_CNTL2_CH_EN, reg));
0112
0113     priv->dsi_enabled = true;
0114 }
0115
0116 static void phy_dsi_analog_disable(struct phy_axg_mipi_pcie_analog_priv *priv)
0117 {
0118     regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
0119             HHI_MIPI_CNTL0_DIF_REF_CTL1,
0120             FIELD_PREP(HHI_MIPI_CNTL0_DIF_REF_CTL1, 0));
0121     regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0, BIT(31), 0);
0122     regmap_update_bits(priv->regmap, HHI_MIPI_CNTL0,
0123             HHI_MIPI_CNTL0_DIF_REF_CTL1, 0);
0124
0125     regmap_write(priv->regmap, HHI_MIPI_CNTL1, 0x6);
0126
0127     regmap_write(priv->regmap, HHI_MIPI_CNTL2, 0x00200000);
0128
0129     priv->dsi_enabled = false;
0130 }
0131
0132 static int phy_axg_mipi_pcie_analog_configure(struct phy *phy,
0133                           union phy_configure_opts *opts)
0134 {
0135     struct phy_axg_mipi_pcie_analog_priv *priv = phy_get_drvdata(phy);
0136     int ret;
0137
0138     ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);
0139     if (ret)
0140         return ret;
0141
0142     memcpy(&priv->config, opts, sizeof(priv->config));
0143
0144     priv->dsi_configured = true;
0145
0146     /* If PHY was already powered on, setup the DSI analog part */
0147     if (priv->powered) {
0148         /* If reconfiguring, disable & reconfigure */
0149         if (priv->dsi_enabled)
0150             phy_dsi_analog_disable(priv);
0151
0152         usleep_range(100, 200);
0153
0154         phy_dsi_analog_enable(priv);
0155     }
0156
0157     return 0;
0158 }
0159
0160 static int phy_axg_mipi_pcie_analog_power_on(struct phy *phy)
0161 {
0162     struct phy_axg_mipi_pcie_analog_priv *priv = phy_get_drvdata(phy);
0163
0164     phy_bandgap_enable(priv);
0165
0166     if (priv->dsi_configured)
0167         phy_dsi_analog_enable(priv);
0168
0169     priv->powered = true;
0170
0171     return 0;
0172 }
0173
0174 static int phy_axg_mipi_pcie_analog_power_off(struct phy *phy)
0175 {
0176     struct phy_axg_mipi_pcie_analog_priv *priv = phy_get_drvdata(phy);
0177
0178     phy_bandgap_disable(priv);
0179
0180     if (priv->dsi_enabled)
0181         phy_dsi_analog_disable(priv);
0182
0183     priv->powered = false;
0184
0185     return 0;
0186 }
0187
0188 static const struct phy_ops phy_axg_mipi_pcie_analog_ops = {
0189     .configure = phy_axg_mipi_pcie_analog_configure,
0190     .power_on = phy_axg_mipi_pcie_analog_power_on,
0191     .power_off = phy_axg_mipi_pcie_analog_power_off,
0192     .owner = THIS_MODULE,
0193 };
0194
0195 static int phy_axg_mipi_pcie_analog_probe(struct platform_device *pdev)
0196 {
0197     struct phy_provider *phy;
0198     struct device *dev = &pdev->dev;
0199     struct phy_axg_mipi_pcie_analog_priv *priv;
0200     struct device_node *np = dev->of_node;
0201     struct regmap *map;
0202     int ret;
0203
0204     priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL);
0205     if (!priv)
0206         return -ENOMEM;
0207
0208     /* Get the hhi system controller node */
0209     map = syscon_node_to_regmap(of_get_parent(dev->of_node));
0210     if (IS_ERR(map)) {
0211         dev_err(dev,
0212             "failed to get HHI regmap\n");
0213         return PTR_ERR(map);
0214     }
0215
0216     priv->regmap = map;
0217
0218     priv->phy = devm_phy_create(dev, np, &phy_axg_mipi_pcie_analog_ops);
0219     if (IS_ERR(priv->phy)) {
0220         ret = PTR_ERR(priv->phy);
0221         if (ret != -EPROBE_DEFER)
0222             dev_err(dev, "failed to create PHY\n");
0223         return ret;
0224     }
0225
0226     phy_set_drvdata(priv->phy, priv);
0227     dev_set_drvdata(dev, priv);
0228
0229     phy = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0230
0231     return PTR_ERR_OR_ZERO(phy);
0232 }
0233
0234 static const struct of_device_id phy_axg_mipi_pcie_analog_of_match[] = {
0235     {
0236         .compatible = "amlogic,axg-mipi-pcie-analog-phy",
0237     },
0238     { },
0239 };
0240 MODULE_DEVICE_TABLE(of, phy_axg_mipi_pcie_analog_of_match);
0241
0242 static struct platform_driver phy_axg_mipi_pcie_analog_driver = {
0243     .probe = phy_axg_mipi_pcie_analog_probe,
0244     .driver = {
0245         .name = "phy-axg-mipi-pcie-analog",
0246         .of_match_table = phy_axg_mipi_pcie_analog_of_match,
0247     },
0248 };
0249 module_platform_driver(phy_axg_mipi_pcie_analog_driver);
0250
0251 MODULE_AUTHOR("Remi Pommarel <repk@triplefau.lt>");
0252 MODULE_DESCRIPTION("Amlogic AXG MIPI + PCIE analog PHY driver");
0253 MODULE_LICENSE("GPL v2");