phy/amlogic/phy-meson-axg-mipi-dphy.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Meson AXG MIPI DPHY driver
0004  *
0005  * Copyright (C) 2018 Amlogic, Inc. All rights reserved
0006  * Copyright (C) 2020 BayLibre, SAS
0007  * Author: Neil Armstrong <narmstrong@baylibre.com>
0008  */
0009
0010 #include <linux/bitfield.h>
0011 #include <linux/bitops.h>
0012 #include <linux/bits.h>
0013 #include <linux/clk.h>
0014 #include <linux/delay.h>
0015 #include <linux/io.h>
0016 #include <linux/module.h>
0017 #include <linux/of_device.h>
0018 #include <linux/regmap.h>
0019 #include <linux/reset.h>
0020 #include <linux/phy/phy.h>
0021 #include <linux/platform_device.h>
0022
0023 /* [31] soft reset for the phy.
0024  *      1: reset. 0: dessert the reset.
0025  * [30] clock lane soft reset.
0026  * [29] data byte lane 3 soft reset.
0027  * [28] data byte lane 2 soft reset.
0028  * [27] data byte lane 1 soft reset.
0029  * [26] data byte lane 0 soft reset.
0030  * [25] mipi dsi pll clock selection.
0031  *      1:  clock from fixed 850Mhz clock source. 0: from VID2 PLL.
0032  * [12] mipi HSbyteclk enable.
0033  * [11] mipi divider clk selection.
0034  *      1: select the mipi DDRCLKHS from clock divider.
0035  *      0: from PLL clock.
0036  * [10] mipi clock divider control.
0037  *      1: /4. 0: /2.
0038  * [9]  mipi divider output enable.
0039  * [8]  mipi divider counter enable.
0040  * [7]  PLL clock enable.
0041  * [5]  LPDT data endian.
0042  *      1 = transfer the high bit first. 0 : transfer the low bit first.
0043  * [4]  HS data endian.
0044  * [3]  force data byte lane in stop mode.
0045  * [2]  force data byte lane 0 in receiver mode.
0046  * [1]  write 1 to sync the txclkesc input. the internal logic have to
0047  *  use txclkesc to decide Txvalid and Txready.
0048  * [0]  enalbe the MIPI DPHY TxDDRClk.
0049  */
0050 #define MIPI_DSI_PHY_CTRL               0x0
0051
0052 /* [31] clk lane tx_hs_en control selection.
0053  *      1: from register. 0: use clk lane state machine.
0054  * [30] register bit for clock lane tx_hs_en.
0055  * [29] clk lane tx_lp_en contrl selection.
0056  *      1: from register. 0: from clk lane state machine.
0057  * [28] register bit for clock lane tx_lp_en.
0058  * [27] chan0 tx_hs_en control selection.
0059  *      1: from register. 0: from chan0 state machine.
0060  * [26] register bit for chan0 tx_hs_en.
0061  * [25] chan0 tx_lp_en control selection.
0062  *      1: from register. 0: from chan0 state machine.
0063  * [24] register bit from chan0 tx_lp_en.
0064  * [23] chan0 rx_lp_en control selection.
0065  *      1: from register. 0: from chan0 state machine.
0066  * [22] register bit from chan0 rx_lp_en.
0067  * [21] chan0 contention detection enable control selection.
0068  *      1: from register. 0: from chan0 state machine.
0069  * [20] register bit from chan0 contention dectection enable.
0070  * [19] chan1 tx_hs_en control selection.
0071  *      1: from register. 0: from chan0 state machine.
0072  * [18] register bit for chan1 tx_hs_en.
0073  * [17] chan1 tx_lp_en control selection.
0074  *      1: from register. 0: from chan0 state machine.
0075  * [16] register bit from chan1 tx_lp_en.
0076  * [15] chan2 tx_hs_en control selection.
0077  *      1: from register. 0: from chan0 state machine.
0078  * [14] register bit for chan2 tx_hs_en.
0079  * [13] chan2 tx_lp_en control selection.
0080  *      1: from register. 0: from chan0 state machine.
0081  * [12] register bit from chan2 tx_lp_en.
0082  * [11] chan3 tx_hs_en control selection.
0083  *      1: from register. 0: from chan0 state machine.
0084  * [10] register bit for chan3 tx_hs_en.
0085  * [9]  chan3 tx_lp_en control selection.
0086  *      1: from register. 0: from chan0 state machine.
0087  * [8]  register bit from chan3 tx_lp_en.
0088  * [4]  clk chan power down. this bit is also used as the power down
0089  *  of the whole MIPI_DSI_PHY.
0090  * [3]  chan3 power down.
0091  * [2]  chan2 power down.
0092  * [1]  chan1 power down.
0093  * [0]  chan0 power down.
0094  */
0095 #define MIPI_DSI_CHAN_CTRL              0x4
0096
0097 /* [24]   rx turn watch dog triggered.
0098  * [23]   rx esc watchdog  triggered.
0099  * [22]   mbias ready.
0100  * [21]   txclkesc  synced and ready.
0101  * [20:17] clk lane state. {mbias_ready, tx_stop, tx_ulps, tx_hs_active}
0102  * [16:13] chan3 state{0, tx_stop, tx_ulps, tx_hs_active}
0103  * [12:9]  chan2 state.{0, tx_stop, tx_ulps, tx_hs_active}
0104  * [8:5]   chan1 state. {0, tx_stop, tx_ulps, tx_hs_active}
0105  * [4:0]   chan0 state. {TX_STOP, tx_ULPS, hs_active, direction, rxulpsesc}
0106  */
0107 #define MIPI_DSI_CHAN_STS               0x8
0108
0109 /* [31:24] TCLK_PREPARE.
0110  * [23:16] TCLK_ZERO.
0111  * [15:8]  TCLK_POST.
0112  * [7:0]   TCLK_TRAIL.
0113  */
0114 #define MIPI_DSI_CLK_TIM                0xc
0115
0116 /* [31:24] THS_PREPARE.
0117  * [23:16] THS_ZERO.
0118  * [15:8]  THS_TRAIL.
0119  * [7:0]   THS_EXIT.
0120  */
0121 #define MIPI_DSI_HS_TIM                 0x10
0122
0123 /* [31:24] tTA_GET.
0124  * [23:16] tTA_GO.
0125  * [15:8]  tTA_SURE.
0126  * [7:0]   tLPX.
0127  */
0128 #define MIPI_DSI_LP_TIM                 0x14
0129
0130 /* wait time to  MIPI DIS analog ready. */
0131 #define MIPI_DSI_ANA_UP_TIM             0x18
0132
0133 /* TINIT. */
0134 #define MIPI_DSI_INIT_TIM               0x1c
0135
0136 /* TWAKEUP. */
0137 #define MIPI_DSI_WAKEUP_TIM             0x20
0138
0139 /* when in RxULPS check state, after the logic enable the analog,
0140  *  how long we should wait to check the lP state .
0141  */
0142 #define MIPI_DSI_LPOK_TIM               0x24
0143
0144 /* Watchdog for RX low power state no finished. */
0145 #define MIPI_DSI_LP_WCHDOG              0x28
0146
0147 /* tMBIAS,  after send power up signals to analog,
0148  *  how long we should wait for analog powered up.
0149  */
0150 #define MIPI_DSI_ANA_CTRL               0x2c
0151
0152 /* [31:8]  reserved for future.
0153  * [7:0]   tCLK_PRE.
0154  */
0155 #define MIPI_DSI_CLK_TIM1               0x30
0156
0157 /* watchdog for turn around waiting time. */
0158 #define MIPI_DSI_TURN_WCHDOG                0x34
0159
0160 /* When in RxULPS state, how frequency we should to check
0161  *  if the TX side out of ULPS state.
0162  */
0163 #define MIPI_DSI_ULPS_CHECK             0x38
0164 #define MIPI_DSI_TEST_CTRL0             0x3c
0165 #define MIPI_DSI_TEST_CTRL1             0x40
0166
0167 struct phy_meson_axg_mipi_dphy_priv {
0168     struct device               *dev;
0169     struct regmap               *regmap;
0170     struct clk              *clk;
0171     struct reset_control            *reset;
0172     struct phy              *analog;
0173     struct phy_configure_opts_mipi_dphy config;
0174 };
0175
0176 static const struct regmap_config phy_meson_axg_mipi_dphy_regmap_conf = {
0177     .reg_bits = 8,
0178     .val_bits = 32,
0179     .reg_stride = 4,
0180     .max_register = MIPI_DSI_TEST_CTRL1,
0181 };
0182
0183 static int phy_meson_axg_mipi_dphy_init(struct phy *phy)
0184 {
0185     struct phy_meson_axg_mipi_dphy_priv *priv = phy_get_drvdata(phy);
0186     int ret;
0187
0188     ret = phy_init(priv->analog);
0189     if (ret)
0190         return ret;
0191
0192     ret = reset_control_reset(priv->reset);
0193     if (ret)
0194         return ret;
0195
0196     return 0;
0197 }
0198
0199 static int phy_meson_axg_mipi_dphy_configure(struct phy *phy,
0200                           union phy_configure_opts *opts)
0201 {
0202     struct phy_meson_axg_mipi_dphy_priv *priv = phy_get_drvdata(phy);
0203     int ret;
0204
0205     ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);
0206     if (ret)
0207         return ret;
0208
0209     ret = phy_configure(priv->analog, opts);
0210     if (ret)
0211         return ret;
0212
0213     memcpy(&priv->config, opts, sizeof(priv->config));
0214
0215     return 0;
0216 }
0217
0218 static int phy_meson_axg_mipi_dphy_power_on(struct phy *phy)
0219 {
0220     struct phy_meson_axg_mipi_dphy_priv *priv = phy_get_drvdata(phy);
0221     int ret;
0222     unsigned long temp;
0223
0224     ret = phy_power_on(priv->analog);
0225     if (ret)
0226         return ret;
0227
0228     /* enable phy clock */
0229     regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL,  0x1);
0230     regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL,
0231              BIT(0) | /* enable the DSI PLL clock . */
0232              BIT(7) | /* enable pll clock which connected to DDR clock path */
0233              BIT(8)); /* enable the clock divider counter */
0234
0235     /* enable the divider clock out */
0236     regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(9), BIT(9));
0237
0238     /* enable the byte clock generation. */
0239     regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(12), BIT(12));
0240     regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31), BIT(31));
0241     regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31), 0);
0242
0243     /* Calculate lanebyteclk period in ps */
0244     temp = (1000000 * 100) / (priv->config.hs_clk_rate / 1000);
0245     temp = temp * 8 * 10;
0246
0247     regmap_write(priv->regmap, MIPI_DSI_CLK_TIM,
0248              DIV_ROUND_UP(priv->config.clk_trail, temp) |
0249              (DIV_ROUND_UP(priv->config.clk_post +
0250                    priv->config.hs_trail, temp) << 8) |
0251              (DIV_ROUND_UP(priv->config.clk_zero, temp) << 16) |
0252              (DIV_ROUND_UP(priv->config.clk_prepare, temp) << 24));
0253     regmap_write(priv->regmap, MIPI_DSI_CLK_TIM1,
0254              DIV_ROUND_UP(priv->config.clk_pre, BITS_PER_BYTE));
0255
0256     regmap_write(priv->regmap, MIPI_DSI_HS_TIM,
0257              DIV_ROUND_UP(priv->config.hs_exit, temp) |
0258              (DIV_ROUND_UP(priv->config.hs_trail, temp) << 8) |
0259              (DIV_ROUND_UP(priv->config.hs_zero, temp) << 16) |
0260              (DIV_ROUND_UP(priv->config.hs_prepare, temp) << 24));
0261
0262     regmap_write(priv->regmap, MIPI_DSI_LP_TIM,
0263              DIV_ROUND_UP(priv->config.lpx, temp) |
0264              (DIV_ROUND_UP(priv->config.ta_sure, temp) << 8) |
0265              (DIV_ROUND_UP(priv->config.ta_go, temp) << 16) |
0266              (DIV_ROUND_UP(priv->config.ta_get, temp) << 24));
0267
0268     regmap_write(priv->regmap, MIPI_DSI_ANA_UP_TIM, 0x0100);
0269     regmap_write(priv->regmap, MIPI_DSI_INIT_TIM,
0270              DIV_ROUND_UP(priv->config.init * NSEC_PER_MSEC, temp));
0271     regmap_write(priv->regmap, MIPI_DSI_WAKEUP_TIM,
0272              DIV_ROUND_UP(priv->config.wakeup * NSEC_PER_MSEC, temp));
0273     regmap_write(priv->regmap, MIPI_DSI_LPOK_TIM, 0x7C);
0274     regmap_write(priv->regmap, MIPI_DSI_ULPS_CHECK, 0x927C);
0275     regmap_write(priv->regmap, MIPI_DSI_LP_WCHDOG, 0x1000);
0276     regmap_write(priv->regmap, MIPI_DSI_TURN_WCHDOG, 0x1000);
0277
0278     /* Powerup the analog circuit */
0279     switch (priv->config.lanes) {
0280     case 1:
0281         regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xe);
0282         break;
0283     case 2:
0284         regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xc);
0285         break;
0286     case 3:
0287         regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0x8);
0288         break;
0289     case 4:
0290     default:
0291         regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0);
0292         break;
0293     }
0294
0295     /* Trigger a sync active for esc_clk */
0296     regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(1), BIT(1));
0297
0298     return 0;
0299 }
0300
0301 static int phy_meson_axg_mipi_dphy_power_off(struct phy *phy)
0302 {
0303     struct phy_meson_axg_mipi_dphy_priv *priv = phy_get_drvdata(phy);
0304
0305     regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xf);
0306     regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31));
0307
0308     phy_power_off(priv->analog);
0309
0310     return 0;
0311 }
0312
0313 static int phy_meson_axg_mipi_dphy_exit(struct phy *phy)
0314 {
0315     struct phy_meson_axg_mipi_dphy_priv *priv = phy_get_drvdata(phy);
0316     int ret;
0317
0318     ret = phy_exit(priv->analog);
0319     if (ret)
0320         return ret;
0321
0322     return reset_control_reset(priv->reset);
0323 }
0324
0325 static const struct phy_ops phy_meson_axg_mipi_dphy_ops = {
0326     .configure  = phy_meson_axg_mipi_dphy_configure,
0327     .init       = phy_meson_axg_mipi_dphy_init,
0328     .exit       = phy_meson_axg_mipi_dphy_exit,
0329     .power_on   = phy_meson_axg_mipi_dphy_power_on,
0330     .power_off  = phy_meson_axg_mipi_dphy_power_off,
0331     .owner      = THIS_MODULE,
0332 };
0333
0334 static int phy_meson_axg_mipi_dphy_probe(struct platform_device *pdev)
0335 {
0336     struct device *dev = &pdev->dev;
0337     struct phy_provider *phy_provider;
0338     struct resource *res;
0339     struct phy_meson_axg_mipi_dphy_priv *priv;
0340     struct phy *phy;
0341     void __iomem *base;
0342     int ret;
0343
0344     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0345     if (!priv)
0346         return -ENOMEM;
0347
0348     priv->dev = dev;
0349     platform_set_drvdata(pdev, priv);
0350
0351     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0352     base = devm_ioremap_resource(dev, res);
0353     if (IS_ERR(base))
0354         return PTR_ERR(base);
0355
0356     priv->regmap = devm_regmap_init_mmio(dev, base,
0357                     &phy_meson_axg_mipi_dphy_regmap_conf);
0358     if (IS_ERR(priv->regmap))
0359         return PTR_ERR(priv->regmap);
0360
0361     priv->clk = devm_clk_get(dev, "pclk");
0362     if (IS_ERR(priv->clk))
0363         return PTR_ERR(priv->clk);
0364
0365     priv->reset = devm_reset_control_get(dev, "phy");
0366     if (IS_ERR(priv->reset))
0367         return PTR_ERR(priv->reset);
0368
0369     priv->analog = devm_phy_get(dev, "analog");
0370     if (IS_ERR(priv->analog))
0371         return PTR_ERR(priv->analog);
0372
0373     ret = clk_prepare_enable(priv->clk);
0374     if (ret)
0375         return ret;
0376
0377     ret = reset_control_deassert(priv->reset);
0378     if (ret)
0379         return ret;
0380
0381     phy = devm_phy_create(dev, NULL, &phy_meson_axg_mipi_dphy_ops);
0382     if (IS_ERR(phy)) {
0383         ret = PTR_ERR(phy);
0384         if (ret != -EPROBE_DEFER)
0385             dev_err(dev, "failed to create PHY\n");
0386
0387         return ret;
0388     }
0389
0390     phy_set_drvdata(phy, priv);
0391
0392     phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0393
0394     return PTR_ERR_OR_ZERO(phy_provider);
0395 }
0396
0397 static const struct of_device_id phy_meson_axg_mipi_dphy_of_match[] = {
0398     { .compatible = "amlogic,axg-mipi-dphy", },
0399     { },
0400 };
0401 MODULE_DEVICE_TABLE(of, phy_meson_axg_mipi_dphy_of_match);
0402
0403 static struct platform_driver phy_meson_axg_mipi_dphy_driver = {
0404     .probe  = phy_meson_axg_mipi_dphy_probe,
0405     .driver = {
0406         .name       = "phy-meson-axg-mipi-dphy",
0407         .of_match_table = phy_meson_axg_mipi_dphy_of_match,
0408     },
0409 };
0410 module_platform_driver(phy_meson_axg_mipi_dphy_driver);
0411
0412 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
0413 MODULE_DESCRIPTION("Meson AXG MIPI DPHY driver");
0414 MODULE_LICENSE("GPL v2");