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0014 #include <linux/clk.h>
0015 #include <linux/err.h>
0016 #include <linux/io.h>
0017 #include <linux/module.h>
0018 #include <linux/phy/phy.h>
0019 #include <linux/usb/of.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/reset.h>
0022
0023 #define SUNXI_AHB_INCR16_BURST_EN BIT(11)
0024 #define SUNXI_AHB_INCR8_BURST_EN BIT(10)
0025 #define SUNXI_AHB_INCR4_BURST_EN BIT(9)
0026 #define SUNXI_AHB_INCRX_ALIGN_EN BIT(8)
0027 #define SUNXI_ULPI_BYPASS_EN BIT(0)
0028
0029
0030 #define SUNXI_EHCI_HS_FORCE BIT(20)
0031 #define SUNXI_HSIC_CONNECT_DET BIT(17)
0032 #define SUNXI_HSIC_CONNECT_INT BIT(16)
0033 #define SUNXI_HSIC BIT(1)
0034
0035 struct sun9i_usb_phy {
0036 struct phy *phy;
0037 void __iomem *pmu;
0038 struct reset_control *reset;
0039 struct clk *clk;
0040 struct clk *hsic_clk;
0041 enum usb_phy_interface type;
0042 };
0043
0044 static void sun9i_usb_phy_passby(struct sun9i_usb_phy *phy, int enable)
0045 {
0046 u32 bits, reg_value;
0047
0048 bits = SUNXI_AHB_INCR16_BURST_EN | SUNXI_AHB_INCR8_BURST_EN |
0049 SUNXI_AHB_INCR4_BURST_EN | SUNXI_AHB_INCRX_ALIGN_EN |
0050 SUNXI_ULPI_BYPASS_EN;
0051
0052 if (phy->type == USBPHY_INTERFACE_MODE_HSIC)
0053 bits |= SUNXI_HSIC | SUNXI_EHCI_HS_FORCE |
0054 SUNXI_HSIC_CONNECT_DET | SUNXI_HSIC_CONNECT_INT;
0055
0056 reg_value = readl(phy->pmu);
0057
0058 if (enable)
0059 reg_value |= bits;
0060 else
0061 reg_value &= ~bits;
0062
0063 writel(reg_value, phy->pmu);
0064 }
0065
0066 static int sun9i_usb_phy_init(struct phy *_phy)
0067 {
0068 struct sun9i_usb_phy *phy = phy_get_drvdata(_phy);
0069 int ret;
0070
0071 ret = clk_prepare_enable(phy->clk);
0072 if (ret)
0073 goto err_clk;
0074
0075 ret = clk_prepare_enable(phy->hsic_clk);
0076 if (ret)
0077 goto err_hsic_clk;
0078
0079 ret = reset_control_deassert(phy->reset);
0080 if (ret)
0081 goto err_reset;
0082
0083 sun9i_usb_phy_passby(phy, 1);
0084 return 0;
0085
0086 err_reset:
0087 clk_disable_unprepare(phy->hsic_clk);
0088
0089 err_hsic_clk:
0090 clk_disable_unprepare(phy->clk);
0091
0092 err_clk:
0093 return ret;
0094 }
0095
0096 static int sun9i_usb_phy_exit(struct phy *_phy)
0097 {
0098 struct sun9i_usb_phy *phy = phy_get_drvdata(_phy);
0099
0100 sun9i_usb_phy_passby(phy, 0);
0101 reset_control_assert(phy->reset);
0102 clk_disable_unprepare(phy->hsic_clk);
0103 clk_disable_unprepare(phy->clk);
0104
0105 return 0;
0106 }
0107
0108 static const struct phy_ops sun9i_usb_phy_ops = {
0109 .init = sun9i_usb_phy_init,
0110 .exit = sun9i_usb_phy_exit,
0111 .owner = THIS_MODULE,
0112 };
0113
0114 static int sun9i_usb_phy_probe(struct platform_device *pdev)
0115 {
0116 struct sun9i_usb_phy *phy;
0117 struct device *dev = &pdev->dev;
0118 struct device_node *np = dev->of_node;
0119 struct phy_provider *phy_provider;
0120
0121 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
0122 if (!phy)
0123 return -ENOMEM;
0124
0125 phy->type = of_usb_get_phy_mode(np);
0126 if (phy->type == USBPHY_INTERFACE_MODE_HSIC) {
0127 phy->clk = devm_clk_get(dev, "hsic_480M");
0128 if (IS_ERR(phy->clk)) {
0129 dev_err(dev, "failed to get hsic_480M clock\n");
0130 return PTR_ERR(phy->clk);
0131 }
0132
0133 phy->hsic_clk = devm_clk_get(dev, "hsic_12M");
0134 if (IS_ERR(phy->hsic_clk)) {
0135 dev_err(dev, "failed to get hsic_12M clock\n");
0136 return PTR_ERR(phy->hsic_clk);
0137 }
0138
0139 phy->reset = devm_reset_control_get(dev, "hsic");
0140 if (IS_ERR(phy->reset)) {
0141 dev_err(dev, "failed to get reset control\n");
0142 return PTR_ERR(phy->reset);
0143 }
0144 } else {
0145 phy->clk = devm_clk_get(dev, "phy");
0146 if (IS_ERR(phy->clk)) {
0147 dev_err(dev, "failed to get phy clock\n");
0148 return PTR_ERR(phy->clk);
0149 }
0150
0151 phy->reset = devm_reset_control_get(dev, "phy");
0152 if (IS_ERR(phy->reset)) {
0153 dev_err(dev, "failed to get reset control\n");
0154 return PTR_ERR(phy->reset);
0155 }
0156 }
0157
0158 phy->pmu = devm_platform_ioremap_resource(pdev, 0);
0159 if (IS_ERR(phy->pmu))
0160 return PTR_ERR(phy->pmu);
0161
0162 phy->phy = devm_phy_create(dev, NULL, &sun9i_usb_phy_ops);
0163 if (IS_ERR(phy->phy)) {
0164 dev_err(dev, "failed to create PHY\n");
0165 return PTR_ERR(phy->phy);
0166 }
0167
0168 phy_set_drvdata(phy->phy, phy);
0169 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
0170
0171 return PTR_ERR_OR_ZERO(phy_provider);
0172 }
0173
0174 static const struct of_device_id sun9i_usb_phy_of_match[] = {
0175 { .compatible = "allwinner,sun9i-a80-usb-phy" },
0176 { },
0177 };
0178 MODULE_DEVICE_TABLE(of, sun9i_usb_phy_of_match);
0179
0180 static struct platform_driver sun9i_usb_phy_driver = {
0181 .probe = sun9i_usb_phy_probe,
0182 .driver = {
0183 .of_match_table = sun9i_usb_phy_of_match,
0184 .name = "sun9i-usb-phy",
0185 }
0186 };
0187 module_platform_driver(sun9i_usb_phy_driver);
0188
0189 MODULE_DESCRIPTION("Allwinner sun9i USB phy driver");
0190 MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
0191 MODULE_LICENSE("GPL");