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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Allwinner sun4i USB phy driver
0004  *
0005  * Copyright (C) 2014-2015 Hans de Goede <hdegoede@redhat.com>
0006  *
0007  * Based on code from
0008  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
0009  *
0010  * Modelled after: Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY driver
0011  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
0012  * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
0013  */
0014 
0015 #include <linux/clk.h>
0016 #include <linux/delay.h>
0017 #include <linux/err.h>
0018 #include <linux/extcon-provider.h>
0019 #include <linux/gpio/consumer.h>
0020 #include <linux/io.h>
0021 #include <linux/interrupt.h>
0022 #include <linux/kernel.h>
0023 #include <linux/module.h>
0024 #include <linux/mutex.h>
0025 #include <linux/of.h>
0026 #include <linux/of_address.h>
0027 #include <linux/of_device.h>
0028 #include <linux/of_gpio.h>
0029 #include <linux/phy/phy.h>
0030 #include <linux/phy/phy-sun4i-usb.h>
0031 #include <linux/platform_device.h>
0032 #include <linux/power_supply.h>
0033 #include <linux/regulator/consumer.h>
0034 #include <linux/reset.h>
0035 #include <linux/spinlock.h>
0036 #include <linux/usb/of.h>
0037 #include <linux/workqueue.h>
0038 
0039 #define REG_ISCR            0x00
0040 #define REG_PHYCTL_A10          0x04
0041 #define REG_PHYBIST         0x08
0042 #define REG_PHYTUNE         0x0c
0043 #define REG_PHYCTL_A33          0x10
0044 #define REG_PHY_OTGCTL          0x20
0045 
0046 #define REG_HCI_PHY_CTL         0x10
0047 
0048 #define PHYCTL_DATA         BIT(7)
0049 
0050 #define OTGCTL_ROUTE_MUSB       BIT(0)
0051 
0052 #define SUNXI_AHB_ICHR8_EN      BIT(10)
0053 #define SUNXI_AHB_INCR4_BURST_EN    BIT(9)
0054 #define SUNXI_AHB_INCRX_ALIGN_EN    BIT(8)
0055 #define SUNXI_ULPI_BYPASS_EN        BIT(0)
0056 
0057 /* ISCR, Interface Status and Control bits */
0058 #define ISCR_ID_PULLUP_EN       (1 << 17)
0059 #define ISCR_DPDM_PULLUP_EN (1 << 16)
0060 /* sunxi has the phy id/vbus pins not connected, so we use the force bits */
0061 #define ISCR_FORCE_ID_MASK  (3 << 14)
0062 #define ISCR_FORCE_ID_LOW       (2 << 14)
0063 #define ISCR_FORCE_ID_HIGH  (3 << 14)
0064 #define ISCR_FORCE_VBUS_MASK    (3 << 12)
0065 #define ISCR_FORCE_VBUS_LOW (2 << 12)
0066 #define ISCR_FORCE_VBUS_HIGH    (3 << 12)
0067 
0068 /* Common Control Bits for Both PHYs */
0069 #define PHY_PLL_BW          0x03
0070 #define PHY_RES45_CAL_EN        0x0c
0071 
0072 /* Private Control Bits for Each PHY */
0073 #define PHY_TX_AMPLITUDE_TUNE       0x20
0074 #define PHY_TX_SLEWRATE_TUNE        0x22
0075 #define PHY_VBUSVALID_TH_SEL        0x25
0076 #define PHY_PULLUP_RES_SEL      0x27
0077 #define PHY_OTG_FUNC_EN         0x28
0078 #define PHY_VBUS_DET_EN         0x29
0079 #define PHY_DISCON_TH_SEL       0x2a
0080 #define PHY_SQUELCH_DETECT      0x3c
0081 
0082 /* A83T specific control bits for PHY0 */
0083 #define PHY_CTL_VBUSVLDEXT      BIT(5)
0084 #define PHY_CTL_SIDDQ           BIT(3)
0085 #define PHY_CTL_H3_SIDDQ        BIT(1)
0086 
0087 /* A83T specific control bits for PHY2 HSIC */
0088 #define SUNXI_EHCI_HS_FORCE     BIT(20)
0089 #define SUNXI_HSIC_CONNECT_DET      BIT(17)
0090 #define SUNXI_HSIC_CONNECT_INT      BIT(16)
0091 #define SUNXI_HSIC          BIT(1)
0092 
0093 #define MAX_PHYS            4
0094 
0095 /*
0096  * Note do not raise the debounce time, we must report Vusb high within 100ms
0097  * otherwise we get Vbus errors
0098  */
0099 #define DEBOUNCE_TIME           msecs_to_jiffies(50)
0100 #define POLL_TIME           msecs_to_jiffies(250)
0101 
0102 enum sun4i_usb_phy_type {
0103     sun4i_a10_phy,
0104     sun6i_a31_phy,
0105     sun8i_a33_phy,
0106     sun8i_a83t_phy,
0107     sun8i_h3_phy,
0108     sun8i_r40_phy,
0109     sun8i_v3s_phy,
0110     sun50i_a64_phy,
0111     sun50i_h6_phy,
0112 };
0113 
0114 struct sun4i_usb_phy_cfg {
0115     int num_phys;
0116     int hsic_index;
0117     enum sun4i_usb_phy_type type;
0118     u32 disc_thresh;
0119     u32 hci_phy_ctl_clear;
0120     u8 phyctl_offset;
0121     bool dedicated_clocks;
0122     bool phy0_dual_route;
0123     int missing_phys;
0124 };
0125 
0126 struct sun4i_usb_phy_data {
0127     void __iomem *base;
0128     const struct sun4i_usb_phy_cfg *cfg;
0129     enum usb_dr_mode dr_mode;
0130     spinlock_t reg_lock; /* guard access to phyctl reg */
0131     struct sun4i_usb_phy {
0132         struct phy *phy;
0133         void __iomem *pmu;
0134         struct regulator *vbus;
0135         struct reset_control *reset;
0136         struct clk *clk;
0137         struct clk *clk2;
0138         bool regulator_on;
0139         int index;
0140     } phys[MAX_PHYS];
0141     /* phy0 / otg related variables */
0142     struct extcon_dev *extcon;
0143     bool phy0_init;
0144     struct gpio_desc *id_det_gpio;
0145     struct gpio_desc *vbus_det_gpio;
0146     struct power_supply *vbus_power_supply;
0147     struct notifier_block vbus_power_nb;
0148     bool vbus_power_nb_registered;
0149     bool force_session_end;
0150     int id_det_irq;
0151     int vbus_det_irq;
0152     int id_det;
0153     int vbus_det;
0154     struct delayed_work detect;
0155 };
0156 
0157 #define to_sun4i_usb_phy_data(phy) \
0158     container_of((phy), struct sun4i_usb_phy_data, phys[(phy)->index])
0159 
0160 static void sun4i_usb_phy0_update_iscr(struct phy *_phy, u32 clr, u32 set)
0161 {
0162     struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
0163     struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
0164     u32 iscr;
0165 
0166     iscr = readl(data->base + REG_ISCR);
0167     iscr &= ~clr;
0168     iscr |= set;
0169     writel(iscr, data->base + REG_ISCR);
0170 }
0171 
0172 static void sun4i_usb_phy0_set_id_detect(struct phy *phy, u32 val)
0173 {
0174     if (val)
0175         val = ISCR_FORCE_ID_HIGH;
0176     else
0177         val = ISCR_FORCE_ID_LOW;
0178 
0179     sun4i_usb_phy0_update_iscr(phy, ISCR_FORCE_ID_MASK, val);
0180 }
0181 
0182 static void sun4i_usb_phy0_set_vbus_detect(struct phy *phy, u32 val)
0183 {
0184     if (val)
0185         val = ISCR_FORCE_VBUS_HIGH;
0186     else
0187         val = ISCR_FORCE_VBUS_LOW;
0188 
0189     sun4i_usb_phy0_update_iscr(phy, ISCR_FORCE_VBUS_MASK, val);
0190 }
0191 
0192 static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
0193                 int len)
0194 {
0195     struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
0196     u32 temp, usbc_bit = BIT(phy->index * 2);
0197     void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;
0198     unsigned long flags;
0199     int i;
0200 
0201     spin_lock_irqsave(&phy_data->reg_lock, flags);
0202 
0203     if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
0204         /* SoCs newer than A33 need us to set phyctl to 0 explicitly */
0205         writel(0, phyctl);
0206     }
0207 
0208     for (i = 0; i < len; i++) {
0209         temp = readl(phyctl);
0210 
0211         /* clear the address portion */
0212         temp &= ~(0xff << 8);
0213 
0214         /* set the address */
0215         temp |= ((addr + i) << 8);
0216         writel(temp, phyctl);
0217 
0218         /* set the data bit and clear usbc bit*/
0219         temp = readb(phyctl);
0220         if (data & 0x1)
0221             temp |= PHYCTL_DATA;
0222         else
0223             temp &= ~PHYCTL_DATA;
0224         temp &= ~usbc_bit;
0225         writeb(temp, phyctl);
0226 
0227         /* pulse usbc_bit */
0228         temp = readb(phyctl);
0229         temp |= usbc_bit;
0230         writeb(temp, phyctl);
0231 
0232         temp = readb(phyctl);
0233         temp &= ~usbc_bit;
0234         writeb(temp, phyctl);
0235 
0236         data >>= 1;
0237     }
0238 
0239     spin_unlock_irqrestore(&phy_data->reg_lock, flags);
0240 }
0241 
0242 static void sun4i_usb_phy_passby(struct sun4i_usb_phy *phy, int enable)
0243 {
0244     struct sun4i_usb_phy_data *phy_data = to_sun4i_usb_phy_data(phy);
0245     u32 bits, reg_value;
0246 
0247     if (!phy->pmu)
0248         return;
0249 
0250     bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
0251         SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
0252 
0253     /* A83T USB2 is HSIC */
0254     if (phy_data->cfg->type == sun8i_a83t_phy && phy->index == 2)
0255         bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
0256             SUNXI_HSIC;
0257 
0258     reg_value = readl(phy->pmu);
0259 
0260     if (enable)
0261         reg_value |= bits;
0262     else
0263         reg_value &= ~bits;
0264 
0265     writel(reg_value, phy->pmu);
0266 }
0267 
0268 static int sun4i_usb_phy_init(struct phy *_phy)
0269 {
0270     struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
0271     struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
0272     int ret;
0273     u32 val;
0274 
0275     ret = clk_prepare_enable(phy->clk);
0276     if (ret)
0277         return ret;
0278 
0279     ret = clk_prepare_enable(phy->clk2);
0280     if (ret) {
0281         clk_disable_unprepare(phy->clk);
0282         return ret;
0283     }
0284 
0285     ret = reset_control_deassert(phy->reset);
0286     if (ret) {
0287         clk_disable_unprepare(phy->clk2);
0288         clk_disable_unprepare(phy->clk);
0289         return ret;
0290     }
0291 
0292     if (phy->pmu && data->cfg->hci_phy_ctl_clear) {
0293         val = readl(phy->pmu + REG_HCI_PHY_CTL);
0294         val &= ~data->cfg->hci_phy_ctl_clear;
0295         writel(val, phy->pmu + REG_HCI_PHY_CTL);
0296     }
0297 
0298     if (data->cfg->type == sun8i_a83t_phy ||
0299         data->cfg->type == sun50i_h6_phy) {
0300         if (phy->index == 0) {
0301             val = readl(data->base + data->cfg->phyctl_offset);
0302             val |= PHY_CTL_VBUSVLDEXT;
0303             val &= ~PHY_CTL_SIDDQ;
0304             writel(val, data->base + data->cfg->phyctl_offset);
0305         }
0306     } else {
0307         /* Enable USB 45 Ohm resistor calibration */
0308         if (phy->index == 0)
0309             sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
0310 
0311         /* Adjust PHY's magnitude and rate */
0312         sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
0313 
0314         /* Disconnect threshold adjustment */
0315         sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
0316                     data->cfg->disc_thresh, 2);
0317     }
0318 
0319     sun4i_usb_phy_passby(phy, 1);
0320 
0321     if (phy->index == 0) {
0322         data->phy0_init = true;
0323 
0324         /* Enable pull-ups */
0325         sun4i_usb_phy0_update_iscr(_phy, 0, ISCR_DPDM_PULLUP_EN);
0326         sun4i_usb_phy0_update_iscr(_phy, 0, ISCR_ID_PULLUP_EN);
0327 
0328         /* Force ISCR and cable state updates */
0329         data->id_det = -1;
0330         data->vbus_det = -1;
0331         queue_delayed_work(system_wq, &data->detect, 0);
0332     }
0333 
0334     return 0;
0335 }
0336 
0337 static int sun4i_usb_phy_exit(struct phy *_phy)
0338 {
0339     struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
0340     struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
0341 
0342     if (phy->index == 0) {
0343         if (data->cfg->type == sun8i_a83t_phy ||
0344             data->cfg->type == sun50i_h6_phy) {
0345             void __iomem *phyctl = data->base +
0346                 data->cfg->phyctl_offset;
0347 
0348             writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
0349         }
0350 
0351         /* Disable pull-ups */
0352         sun4i_usb_phy0_update_iscr(_phy, ISCR_DPDM_PULLUP_EN, 0);
0353         sun4i_usb_phy0_update_iscr(_phy, ISCR_ID_PULLUP_EN, 0);
0354         data->phy0_init = false;
0355     }
0356 
0357     sun4i_usb_phy_passby(phy, 0);
0358     reset_control_assert(phy->reset);
0359     clk_disable_unprepare(phy->clk2);
0360     clk_disable_unprepare(phy->clk);
0361 
0362     return 0;
0363 }
0364 
0365 static int sun4i_usb_phy0_get_id_det(struct sun4i_usb_phy_data *data)
0366 {
0367     switch (data->dr_mode) {
0368     case USB_DR_MODE_OTG:
0369         if (data->id_det_gpio)
0370             return gpiod_get_value_cansleep(data->id_det_gpio);
0371         else
0372             return 1; /* Fallback to peripheral mode */
0373     case USB_DR_MODE_HOST:
0374         return 0;
0375     case USB_DR_MODE_PERIPHERAL:
0376     default:
0377         return 1;
0378     }
0379 }
0380 
0381 static int sun4i_usb_phy0_get_vbus_det(struct sun4i_usb_phy_data *data)
0382 {
0383     if (data->vbus_det_gpio)
0384         return gpiod_get_value_cansleep(data->vbus_det_gpio);
0385 
0386     if (data->vbus_power_supply) {
0387         union power_supply_propval val;
0388         int r;
0389 
0390         r = power_supply_get_property(data->vbus_power_supply,
0391                           POWER_SUPPLY_PROP_PRESENT, &val);
0392         if (r == 0)
0393             return val.intval;
0394     }
0395 
0396     /* Fallback: report vbus as high */
0397     return 1;
0398 }
0399 
0400 static bool sun4i_usb_phy0_have_vbus_det(struct sun4i_usb_phy_data *data)
0401 {
0402     return data->vbus_det_gpio || data->vbus_power_supply;
0403 }
0404 
0405 static bool sun4i_usb_phy0_poll(struct sun4i_usb_phy_data *data)
0406 {
0407     if ((data->id_det_gpio && data->id_det_irq <= 0) ||
0408         (data->vbus_det_gpio && data->vbus_det_irq <= 0))
0409         return true;
0410 
0411     /*
0412      * The A31/A23/A33 companion pmics (AXP221/AXP223) do not
0413      * generate vbus change interrupts when the board is driving
0414      * vbus using the N_VBUSEN pin on the pmic, so we must poll
0415      * when using the pmic for vbus-det _and_ we're driving vbus.
0416      */
0417     if ((data->cfg->type == sun6i_a31_phy ||
0418          data->cfg->type == sun8i_a33_phy) &&
0419         data->vbus_power_supply && data->phys[0].regulator_on)
0420         return true;
0421 
0422     return false;
0423 }
0424 
0425 static int sun4i_usb_phy_power_on(struct phy *_phy)
0426 {
0427     struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
0428     struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
0429     int ret;
0430 
0431     if (!phy->vbus || phy->regulator_on)
0432         return 0;
0433 
0434     /* For phy0 only turn on Vbus if we don't have an ext. Vbus */
0435     if (phy->index == 0 && sun4i_usb_phy0_have_vbus_det(data) &&
0436                 data->vbus_det) {
0437         dev_warn(&_phy->dev, "External vbus detected, not enabling our own vbus\n");
0438         return 0;
0439     }
0440 
0441     ret = regulator_enable(phy->vbus);
0442     if (ret)
0443         return ret;
0444 
0445     phy->regulator_on = true;
0446 
0447     /* We must report Vbus high within OTG_TIME_A_WAIT_VRISE msec. */
0448     if (phy->index == 0 && sun4i_usb_phy0_poll(data))
0449         mod_delayed_work(system_wq, &data->detect, DEBOUNCE_TIME);
0450 
0451     return 0;
0452 }
0453 
0454 static int sun4i_usb_phy_power_off(struct phy *_phy)
0455 {
0456     struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
0457     struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
0458 
0459     if (!phy->vbus || !phy->regulator_on)
0460         return 0;
0461 
0462     regulator_disable(phy->vbus);
0463     phy->regulator_on = false;
0464 
0465     /*
0466      * phy0 vbus typically slowly discharges, sometimes this causes the
0467      * Vbus gpio to not trigger an edge irq on Vbus off, so force a rescan.
0468      */
0469     if (phy->index == 0 && !sun4i_usb_phy0_poll(data))
0470         mod_delayed_work(system_wq, &data->detect, POLL_TIME);
0471 
0472     return 0;
0473 }
0474 
0475 static int sun4i_usb_phy_set_mode(struct phy *_phy,
0476                   enum phy_mode mode, int submode)
0477 {
0478     struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
0479     struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
0480     int new_mode;
0481 
0482     if (phy->index != 0) {
0483         if (mode == PHY_MODE_USB_HOST)
0484             return 0;
0485         return -EINVAL;
0486     }
0487 
0488     switch (mode) {
0489     case PHY_MODE_USB_HOST:
0490         new_mode = USB_DR_MODE_HOST;
0491         break;
0492     case PHY_MODE_USB_DEVICE:
0493         new_mode = USB_DR_MODE_PERIPHERAL;
0494         break;
0495     case PHY_MODE_USB_OTG:
0496         new_mode = USB_DR_MODE_OTG;
0497         break;
0498     default:
0499         return -EINVAL;
0500     }
0501 
0502     if (new_mode != data->dr_mode) {
0503         dev_info(&_phy->dev, "Changing dr_mode to %d\n", new_mode);
0504         data->dr_mode = new_mode;
0505     }
0506 
0507     data->id_det = -1; /* Force reprocessing of id */
0508     data->force_session_end = true;
0509     queue_delayed_work(system_wq, &data->detect, 0);
0510 
0511     return 0;
0512 }
0513 
0514 void sun4i_usb_phy_set_squelch_detect(struct phy *_phy, bool enabled)
0515 {
0516     struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
0517 
0518     sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2);
0519 }
0520 EXPORT_SYMBOL_GPL(sun4i_usb_phy_set_squelch_detect);
0521 
0522 static const struct phy_ops sun4i_usb_phy_ops = {
0523     .init       = sun4i_usb_phy_init,
0524     .exit       = sun4i_usb_phy_exit,
0525     .power_on   = sun4i_usb_phy_power_on,
0526     .power_off  = sun4i_usb_phy_power_off,
0527     .set_mode   = sun4i_usb_phy_set_mode,
0528     .owner      = THIS_MODULE,
0529 };
0530 
0531 static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, int id_det)
0532 {
0533     u32 regval;
0534 
0535     regval = readl(data->base + REG_PHY_OTGCTL);
0536     if (id_det == 0) {
0537         /* Host mode. Route phy0 to EHCI/OHCI */
0538         regval &= ~OTGCTL_ROUTE_MUSB;
0539     } else {
0540         /* Peripheral mode. Route phy0 to MUSB */
0541         regval |= OTGCTL_ROUTE_MUSB;
0542     }
0543     writel(regval, data->base + REG_PHY_OTGCTL);
0544 }
0545 
0546 static void sun4i_usb_phy0_id_vbus_det_scan(struct work_struct *work)
0547 {
0548     struct sun4i_usb_phy_data *data =
0549         container_of(work, struct sun4i_usb_phy_data, detect.work);
0550     struct phy *phy0 = data->phys[0].phy;
0551     struct sun4i_usb_phy *phy;
0552     bool force_session_end, id_notify = false, vbus_notify = false;
0553     int id_det, vbus_det;
0554 
0555     if (!phy0)
0556         return;
0557 
0558     phy = phy_get_drvdata(phy0);
0559     id_det = sun4i_usb_phy0_get_id_det(data);
0560     vbus_det = sun4i_usb_phy0_get_vbus_det(data);
0561 
0562     mutex_lock(&phy0->mutex);
0563 
0564     if (!data->phy0_init) {
0565         mutex_unlock(&phy0->mutex);
0566         return;
0567     }
0568 
0569     force_session_end = data->force_session_end;
0570     data->force_session_end = false;
0571 
0572     if (id_det != data->id_det) {
0573         /* id-change, force session end if we've no vbus detection */
0574         if (data->dr_mode == USB_DR_MODE_OTG &&
0575             !sun4i_usb_phy0_have_vbus_det(data))
0576             force_session_end = true;
0577 
0578         /* When entering host mode (id = 0) force end the session now */
0579         if (force_session_end && id_det == 0) {
0580             sun4i_usb_phy0_set_vbus_detect(phy0, 0);
0581             msleep(200);
0582             sun4i_usb_phy0_set_vbus_detect(phy0, 1);
0583         }
0584         sun4i_usb_phy0_set_id_detect(phy0, id_det);
0585         data->id_det = id_det;
0586         id_notify = true;
0587     }
0588 
0589     if (vbus_det != data->vbus_det) {
0590         sun4i_usb_phy0_set_vbus_detect(phy0, vbus_det);
0591         data->vbus_det = vbus_det;
0592         vbus_notify = true;
0593     }
0594 
0595     mutex_unlock(&phy0->mutex);
0596 
0597     if (id_notify) {
0598         extcon_set_state_sync(data->extcon, EXTCON_USB_HOST,
0599                     !id_det);
0600         /* When leaving host mode force end the session here */
0601         if (force_session_end && id_det == 1) {
0602             mutex_lock(&phy0->mutex);
0603             sun4i_usb_phy0_set_vbus_detect(phy0, 0);
0604             msleep(1000);
0605             sun4i_usb_phy0_set_vbus_detect(phy0, 1);
0606             mutex_unlock(&phy0->mutex);
0607         }
0608 
0609         /* Enable PHY0 passby for host mode only. */
0610         sun4i_usb_phy_passby(phy, !id_det);
0611 
0612         /* Re-route PHY0 if necessary */
0613         if (data->cfg->phy0_dual_route)
0614             sun4i_usb_phy0_reroute(data, id_det);
0615     }
0616 
0617     if (vbus_notify)
0618         extcon_set_state_sync(data->extcon, EXTCON_USB, vbus_det);
0619 
0620     if (sun4i_usb_phy0_poll(data))
0621         queue_delayed_work(system_wq, &data->detect, POLL_TIME);
0622 }
0623 
0624 static irqreturn_t sun4i_usb_phy0_id_vbus_det_irq(int irq, void *dev_id)
0625 {
0626     struct sun4i_usb_phy_data *data = dev_id;
0627 
0628     /* vbus or id changed, let the pins settle and then scan them */
0629     mod_delayed_work(system_wq, &data->detect, DEBOUNCE_TIME);
0630 
0631     return IRQ_HANDLED;
0632 }
0633 
0634 static int sun4i_usb_phy0_vbus_notify(struct notifier_block *nb,
0635                       unsigned long val, void *v)
0636 {
0637     struct sun4i_usb_phy_data *data =
0638         container_of(nb, struct sun4i_usb_phy_data, vbus_power_nb);
0639     struct power_supply *psy = v;
0640 
0641     /* Properties on the vbus_power_supply changed, scan vbus_det */
0642     if (val == PSY_EVENT_PROP_CHANGED && psy == data->vbus_power_supply)
0643         mod_delayed_work(system_wq, &data->detect, DEBOUNCE_TIME);
0644 
0645     return NOTIFY_OK;
0646 }
0647 
0648 static struct phy *sun4i_usb_phy_xlate(struct device *dev,
0649                     struct of_phandle_args *args)
0650 {
0651     struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
0652 
0653     if (args->args[0] >= data->cfg->num_phys)
0654         return ERR_PTR(-ENODEV);
0655 
0656     if (data->cfg->missing_phys & BIT(args->args[0]))
0657         return ERR_PTR(-ENODEV);
0658 
0659     return data->phys[args->args[0]].phy;
0660 }
0661 
0662 static int sun4i_usb_phy_remove(struct platform_device *pdev)
0663 {
0664     struct device *dev = &pdev->dev;
0665     struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
0666 
0667     if (data->vbus_power_nb_registered)
0668         power_supply_unreg_notifier(&data->vbus_power_nb);
0669     if (data->id_det_irq > 0)
0670         devm_free_irq(dev, data->id_det_irq, data);
0671     if (data->vbus_det_irq > 0)
0672         devm_free_irq(dev, data->vbus_det_irq, data);
0673 
0674     cancel_delayed_work_sync(&data->detect);
0675 
0676     return 0;
0677 }
0678 
0679 static const unsigned int sun4i_usb_phy0_cable[] = {
0680     EXTCON_USB,
0681     EXTCON_USB_HOST,
0682     EXTCON_NONE,
0683 };
0684 
0685 static int sun4i_usb_phy_probe(struct platform_device *pdev)
0686 {
0687     struct sun4i_usb_phy_data *data;
0688     struct device *dev = &pdev->dev;
0689     struct device_node *np = dev->of_node;
0690     struct phy_provider *phy_provider;
0691     int i, ret;
0692 
0693     data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
0694     if (!data)
0695         return -ENOMEM;
0696 
0697     spin_lock_init(&data->reg_lock);
0698     INIT_DELAYED_WORK(&data->detect, sun4i_usb_phy0_id_vbus_det_scan);
0699     dev_set_drvdata(dev, data);
0700     data->cfg = of_device_get_match_data(dev);
0701     if (!data->cfg)
0702         return -EINVAL;
0703 
0704     data->base = devm_platform_ioremap_resource_byname(pdev, "phy_ctrl");
0705     if (IS_ERR(data->base))
0706         return PTR_ERR(data->base);
0707 
0708     data->id_det_gpio = devm_gpiod_get_optional(dev, "usb0_id_det",
0709                             GPIOD_IN);
0710     if (IS_ERR(data->id_det_gpio)) {
0711         dev_err(dev, "Couldn't request ID GPIO\n");
0712         return PTR_ERR(data->id_det_gpio);
0713     }
0714 
0715     data->vbus_det_gpio = devm_gpiod_get_optional(dev, "usb0_vbus_det",
0716                               GPIOD_IN);
0717     if (IS_ERR(data->vbus_det_gpio)) {
0718         dev_err(dev, "Couldn't request VBUS detect GPIO\n");
0719         return PTR_ERR(data->vbus_det_gpio);
0720     }
0721 
0722     if (of_find_property(np, "usb0_vbus_power-supply", NULL)) {
0723         data->vbus_power_supply = devm_power_supply_get_by_phandle(dev,
0724                              "usb0_vbus_power-supply");
0725         if (IS_ERR(data->vbus_power_supply)) {
0726             dev_err(dev, "Couldn't get the VBUS power supply\n");
0727             return PTR_ERR(data->vbus_power_supply);
0728         }
0729 
0730         if (!data->vbus_power_supply)
0731             return -EPROBE_DEFER;
0732     }
0733 
0734     data->dr_mode = of_usb_get_dr_mode_by_phy(np, 0);
0735 
0736     data->extcon = devm_extcon_dev_allocate(dev, sun4i_usb_phy0_cable);
0737     if (IS_ERR(data->extcon)) {
0738         dev_err(dev, "Couldn't allocate our extcon device\n");
0739         return PTR_ERR(data->extcon);
0740     }
0741 
0742     ret = devm_extcon_dev_register(dev, data->extcon);
0743     if (ret) {
0744         dev_err(dev, "failed to register extcon: %d\n", ret);
0745         return ret;
0746     }
0747 
0748     for (i = 0; i < data->cfg->num_phys; i++) {
0749         struct sun4i_usb_phy *phy = data->phys + i;
0750         char name[16];
0751 
0752         if (data->cfg->missing_phys & BIT(i))
0753             continue;
0754 
0755         snprintf(name, sizeof(name), "usb%d_vbus", i);
0756         phy->vbus = devm_regulator_get_optional(dev, name);
0757         if (IS_ERR(phy->vbus)) {
0758             if (PTR_ERR(phy->vbus) == -EPROBE_DEFER) {
0759                 dev_err(dev,
0760                     "Couldn't get regulator %s... Deferring probe\n",
0761                     name);
0762                 return -EPROBE_DEFER;
0763             }
0764 
0765             phy->vbus = NULL;
0766         }
0767 
0768         if (data->cfg->dedicated_clocks)
0769             snprintf(name, sizeof(name), "usb%d_phy", i);
0770         else
0771             strlcpy(name, "usb_phy", sizeof(name));
0772 
0773         phy->clk = devm_clk_get(dev, name);
0774         if (IS_ERR(phy->clk)) {
0775             dev_err(dev, "failed to get clock %s\n", name);
0776             return PTR_ERR(phy->clk);
0777         }
0778 
0779         /* The first PHY is always tied to OTG, and never HSIC */
0780         if (data->cfg->hsic_index && i == data->cfg->hsic_index) {
0781             /* HSIC needs secondary clock */
0782             snprintf(name, sizeof(name), "usb%d_hsic_12M", i);
0783             phy->clk2 = devm_clk_get(dev, name);
0784             if (IS_ERR(phy->clk2)) {
0785                 dev_err(dev, "failed to get clock %s\n", name);
0786                 return PTR_ERR(phy->clk2);
0787             }
0788         }
0789 
0790         snprintf(name, sizeof(name), "usb%d_reset", i);
0791         phy->reset = devm_reset_control_get(dev, name);
0792         if (IS_ERR(phy->reset)) {
0793             dev_err(dev, "failed to get reset %s\n", name);
0794             return PTR_ERR(phy->reset);
0795         }
0796 
0797         if (i || data->cfg->phy0_dual_route) { /* No pmu for musb */
0798             snprintf(name, sizeof(name), "pmu%d", i);
0799             phy->pmu = devm_platform_ioremap_resource_byname(pdev, name);
0800             if (IS_ERR(phy->pmu))
0801                 return PTR_ERR(phy->pmu);
0802         }
0803 
0804         phy->phy = devm_phy_create(dev, NULL, &sun4i_usb_phy_ops);
0805         if (IS_ERR(phy->phy)) {
0806             dev_err(dev, "failed to create PHY %d\n", i);
0807             return PTR_ERR(phy->phy);
0808         }
0809 
0810         phy->index = i;
0811         phy_set_drvdata(phy->phy, &data->phys[i]);
0812     }
0813 
0814     data->id_det_irq = gpiod_to_irq(data->id_det_gpio);
0815     if (data->id_det_irq > 0) {
0816         ret = devm_request_irq(dev, data->id_det_irq,
0817                 sun4i_usb_phy0_id_vbus_det_irq,
0818                 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
0819                 "usb0-id-det", data);
0820         if (ret) {
0821             dev_err(dev, "Err requesting id-det-irq: %d\n", ret);
0822             return ret;
0823         }
0824     }
0825 
0826     data->vbus_det_irq = gpiod_to_irq(data->vbus_det_gpio);
0827     if (data->vbus_det_irq > 0) {
0828         ret = devm_request_irq(dev, data->vbus_det_irq,
0829                 sun4i_usb_phy0_id_vbus_det_irq,
0830                 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
0831                 "usb0-vbus-det", data);
0832         if (ret) {
0833             dev_err(dev, "Err requesting vbus-det-irq: %d\n", ret);
0834             data->vbus_det_irq = -1;
0835             sun4i_usb_phy_remove(pdev); /* Stop detect work */
0836             return ret;
0837         }
0838     }
0839 
0840     if (data->vbus_power_supply) {
0841         data->vbus_power_nb.notifier_call = sun4i_usb_phy0_vbus_notify;
0842         data->vbus_power_nb.priority = 0;
0843         ret = power_supply_reg_notifier(&data->vbus_power_nb);
0844         if (ret) {
0845             sun4i_usb_phy_remove(pdev); /* Stop detect work */
0846             return ret;
0847         }
0848         data->vbus_power_nb_registered = true;
0849     }
0850 
0851     phy_provider = devm_of_phy_provider_register(dev, sun4i_usb_phy_xlate);
0852     if (IS_ERR(phy_provider)) {
0853         sun4i_usb_phy_remove(pdev); /* Stop detect work */
0854         return PTR_ERR(phy_provider);
0855     }
0856 
0857     dev_dbg(dev, "successfully loaded\n");
0858 
0859     return 0;
0860 }
0861 
0862 static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
0863     .num_phys = 3,
0864     .type = sun4i_a10_phy,
0865     .disc_thresh = 3,
0866     .phyctl_offset = REG_PHYCTL_A10,
0867     .dedicated_clocks = false,
0868 };
0869 
0870 static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
0871     .num_phys = 2,
0872     .type = sun4i_a10_phy,
0873     .disc_thresh = 2,
0874     .phyctl_offset = REG_PHYCTL_A10,
0875     .dedicated_clocks = false,
0876 };
0877 
0878 static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
0879     .num_phys = 3,
0880     .type = sun6i_a31_phy,
0881     .disc_thresh = 3,
0882     .phyctl_offset = REG_PHYCTL_A10,
0883     .dedicated_clocks = true,
0884 };
0885 
0886 static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
0887     .num_phys = 3,
0888     .type = sun4i_a10_phy,
0889     .disc_thresh = 2,
0890     .phyctl_offset = REG_PHYCTL_A10,
0891     .dedicated_clocks = false,
0892 };
0893 
0894 static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
0895     .num_phys = 2,
0896     .type = sun6i_a31_phy,
0897     .disc_thresh = 3,
0898     .phyctl_offset = REG_PHYCTL_A10,
0899     .dedicated_clocks = true,
0900 };
0901 
0902 static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
0903     .num_phys = 2,
0904     .type = sun8i_a33_phy,
0905     .disc_thresh = 3,
0906     .phyctl_offset = REG_PHYCTL_A33,
0907     .dedicated_clocks = true,
0908 };
0909 
0910 static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
0911     .num_phys = 3,
0912     .hsic_index = 2,
0913     .type = sun8i_a83t_phy,
0914     .phyctl_offset = REG_PHYCTL_A33,
0915     .dedicated_clocks = true,
0916 };
0917 
0918 static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
0919     .num_phys = 4,
0920     .type = sun8i_h3_phy,
0921     .disc_thresh = 3,
0922     .phyctl_offset = REG_PHYCTL_A33,
0923     .dedicated_clocks = true,
0924     .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
0925     .phy0_dual_route = true,
0926 };
0927 
0928 static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
0929     .num_phys = 3,
0930     .type = sun8i_r40_phy,
0931     .disc_thresh = 3,
0932     .phyctl_offset = REG_PHYCTL_A33,
0933     .dedicated_clocks = true,
0934     .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
0935     .phy0_dual_route = true,
0936 };
0937 
0938 static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
0939     .num_phys = 1,
0940     .type = sun8i_v3s_phy,
0941     .disc_thresh = 3,
0942     .phyctl_offset = REG_PHYCTL_A33,
0943     .dedicated_clocks = true,
0944     .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
0945     .phy0_dual_route = true,
0946 };
0947 
0948 static const struct sun4i_usb_phy_cfg sun20i_d1_cfg = {
0949     .num_phys = 2,
0950     .type = sun50i_h6_phy,
0951     .phyctl_offset = REG_PHYCTL_A33,
0952     .dedicated_clocks = true,
0953     .hci_phy_ctl_clear = PHY_CTL_SIDDQ,
0954     .phy0_dual_route = true,
0955 };
0956 
0957 static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
0958     .num_phys = 2,
0959     .type = sun50i_a64_phy,
0960     .disc_thresh = 3,
0961     .phyctl_offset = REG_PHYCTL_A33,
0962     .dedicated_clocks = true,
0963     .hci_phy_ctl_clear = PHY_CTL_H3_SIDDQ,
0964     .phy0_dual_route = true,
0965 };
0966 
0967 static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
0968     .num_phys = 4,
0969     .type = sun50i_h6_phy,
0970     .phyctl_offset = REG_PHYCTL_A33,
0971     .dedicated_clocks = true,
0972     .phy0_dual_route = true,
0973     .missing_phys = BIT(1) | BIT(2),
0974 };
0975 
0976 static const struct of_device_id sun4i_usb_phy_of_match[] = {
0977     { .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
0978     { .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
0979     { .compatible = "allwinner,sun6i-a31-usb-phy", .data = &sun6i_a31_cfg },
0980     { .compatible = "allwinner,sun7i-a20-usb-phy", .data = &sun7i_a20_cfg },
0981     { .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg },
0982     { .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg },
0983     { .compatible = "allwinner,sun8i-a83t-usb-phy", .data = &sun8i_a83t_cfg },
0984     { .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg },
0985     { .compatible = "allwinner,sun8i-r40-usb-phy", .data = &sun8i_r40_cfg },
0986     { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = &sun8i_v3s_cfg },
0987     { .compatible = "allwinner,sun20i-d1-usb-phy", .data = &sun20i_d1_cfg },
0988     { .compatible = "allwinner,sun50i-a64-usb-phy",
0989       .data = &sun50i_a64_cfg},
0990     { .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
0991     { },
0992 };
0993 MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
0994 
0995 static struct platform_driver sun4i_usb_phy_driver = {
0996     .probe  = sun4i_usb_phy_probe,
0997     .remove = sun4i_usb_phy_remove,
0998     .driver = {
0999         .of_match_table = sun4i_usb_phy_of_match,
1000         .name  = "sun4i-usb-phy",
1001     }
1002 };
1003 module_platform_driver(sun4i_usb_phy_driver);
1004 
1005 MODULE_DESCRIPTION("Allwinner sun4i USB phy driver");
1006 MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
1007 MODULE_LICENSE("GPL v2");
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