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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Perf support for the Statistical Profiling Extension, introduced as
0004  * part of ARMv8.2.
0005  *
0006  * Copyright (C) 2016 ARM Limited
0007  *
0008  * Author: Will Deacon <will.deacon@arm.com>
0009  */
0010 
0011 #define PMUNAME                 "arm_spe"
0012 #define DRVNAME                 PMUNAME "_pmu"
0013 #define pr_fmt(fmt)             DRVNAME ": " fmt
0014 
0015 #include <linux/bitops.h>
0016 #include <linux/bug.h>
0017 #include <linux/capability.h>
0018 #include <linux/cpuhotplug.h>
0019 #include <linux/cpumask.h>
0020 #include <linux/device.h>
0021 #include <linux/errno.h>
0022 #include <linux/interrupt.h>
0023 #include <linux/irq.h>
0024 #include <linux/kernel.h>
0025 #include <linux/list.h>
0026 #include <linux/module.h>
0027 #include <linux/of_address.h>
0028 #include <linux/of_device.h>
0029 #include <linux/perf_event.h>
0030 #include <linux/perf/arm_pmu.h>
0031 #include <linux/platform_device.h>
0032 #include <linux/printk.h>
0033 #include <linux/slab.h>
0034 #include <linux/smp.h>
0035 #include <linux/vmalloc.h>
0036 
0037 #include <asm/barrier.h>
0038 #include <asm/cpufeature.h>
0039 #include <asm/mmu.h>
0040 #include <asm/sysreg.h>
0041 
0042 /*
0043  * Cache if the event is allowed to trace Context information.
0044  * This allows us to perform the check, i.e, perfmon_capable(),
0045  * in the context of the event owner, once, during the event_init().
0046  */
0047 #define SPE_PMU_HW_FLAGS_CX         BIT(0)
0048 
0049 static void set_spe_event_has_cx(struct perf_event *event)
0050 {
0051     if (IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR) && perfmon_capable())
0052         event->hw.flags |= SPE_PMU_HW_FLAGS_CX;
0053 }
0054 
0055 static bool get_spe_event_has_cx(struct perf_event *event)
0056 {
0057     return !!(event->hw.flags & SPE_PMU_HW_FLAGS_CX);
0058 }
0059 
0060 #define ARM_SPE_BUF_PAD_BYTE            0
0061 
0062 struct arm_spe_pmu_buf {
0063     int                 nr_pages;
0064     bool                    snapshot;
0065     void                    *base;
0066 };
0067 
0068 struct arm_spe_pmu {
0069     struct pmu              pmu;
0070     struct platform_device          *pdev;
0071     cpumask_t               supported_cpus;
0072     struct hlist_node           hotplug_node;
0073 
0074     int                 irq; /* PPI */
0075     u16                 pmsver;
0076     u16                 min_period;
0077     u16                 counter_sz;
0078 
0079 #define SPE_PMU_FEAT_FILT_EVT           (1UL << 0)
0080 #define SPE_PMU_FEAT_FILT_TYP           (1UL << 1)
0081 #define SPE_PMU_FEAT_FILT_LAT           (1UL << 2)
0082 #define SPE_PMU_FEAT_ARCH_INST          (1UL << 3)
0083 #define SPE_PMU_FEAT_LDS            (1UL << 4)
0084 #define SPE_PMU_FEAT_ERND           (1UL << 5)
0085 #define SPE_PMU_FEAT_DEV_PROBED         (1UL << 63)
0086     u64                 features;
0087 
0088     u16                 max_record_sz;
0089     u16                 align;
0090     struct perf_output_handle __percpu  *handle;
0091 };
0092 
0093 #define to_spe_pmu(p) (container_of(p, struct arm_spe_pmu, pmu))
0094 
0095 /* Convert a free-running index from perf into an SPE buffer offset */
0096 #define PERF_IDX2OFF(idx, buf)  ((idx) % ((buf)->nr_pages << PAGE_SHIFT))
0097 
0098 /* Keep track of our dynamic hotplug state */
0099 static enum cpuhp_state arm_spe_pmu_online;
0100 
0101 enum arm_spe_pmu_buf_fault_action {
0102     SPE_PMU_BUF_FAULT_ACT_SPURIOUS,
0103     SPE_PMU_BUF_FAULT_ACT_FATAL,
0104     SPE_PMU_BUF_FAULT_ACT_OK,
0105 };
0106 
0107 /* This sysfs gunk was really good fun to write. */
0108 enum arm_spe_pmu_capabilities {
0109     SPE_PMU_CAP_ARCH_INST = 0,
0110     SPE_PMU_CAP_ERND,
0111     SPE_PMU_CAP_FEAT_MAX,
0112     SPE_PMU_CAP_CNT_SZ = SPE_PMU_CAP_FEAT_MAX,
0113     SPE_PMU_CAP_MIN_IVAL,
0114 };
0115 
0116 static int arm_spe_pmu_feat_caps[SPE_PMU_CAP_FEAT_MAX] = {
0117     [SPE_PMU_CAP_ARCH_INST] = SPE_PMU_FEAT_ARCH_INST,
0118     [SPE_PMU_CAP_ERND]  = SPE_PMU_FEAT_ERND,
0119 };
0120 
0121 static u32 arm_spe_pmu_cap_get(struct arm_spe_pmu *spe_pmu, int cap)
0122 {
0123     if (cap < SPE_PMU_CAP_FEAT_MAX)
0124         return !!(spe_pmu->features & arm_spe_pmu_feat_caps[cap]);
0125 
0126     switch (cap) {
0127     case SPE_PMU_CAP_CNT_SZ:
0128         return spe_pmu->counter_sz;
0129     case SPE_PMU_CAP_MIN_IVAL:
0130         return spe_pmu->min_period;
0131     default:
0132         WARN(1, "unknown cap %d\n", cap);
0133     }
0134 
0135     return 0;
0136 }
0137 
0138 static ssize_t arm_spe_pmu_cap_show(struct device *dev,
0139                     struct device_attribute *attr,
0140                     char *buf)
0141 {
0142     struct arm_spe_pmu *spe_pmu = dev_get_drvdata(dev);
0143     struct dev_ext_attribute *ea =
0144         container_of(attr, struct dev_ext_attribute, attr);
0145     int cap = (long)ea->var;
0146 
0147     return sysfs_emit(buf, "%u\n", arm_spe_pmu_cap_get(spe_pmu, cap));
0148 }
0149 
0150 #define SPE_EXT_ATTR_ENTRY(_name, _func, _var)              \
0151     &((struct dev_ext_attribute[]) {                \
0152         { __ATTR(_name, S_IRUGO, _func, NULL), (void *)_var }   \
0153     })[0].attr.attr
0154 
0155 #define SPE_CAP_EXT_ATTR_ENTRY(_name, _var)             \
0156     SPE_EXT_ATTR_ENTRY(_name, arm_spe_pmu_cap_show, _var)
0157 
0158 static struct attribute *arm_spe_pmu_cap_attr[] = {
0159     SPE_CAP_EXT_ATTR_ENTRY(arch_inst, SPE_PMU_CAP_ARCH_INST),
0160     SPE_CAP_EXT_ATTR_ENTRY(ernd, SPE_PMU_CAP_ERND),
0161     SPE_CAP_EXT_ATTR_ENTRY(count_size, SPE_PMU_CAP_CNT_SZ),
0162     SPE_CAP_EXT_ATTR_ENTRY(min_interval, SPE_PMU_CAP_MIN_IVAL),
0163     NULL,
0164 };
0165 
0166 static const struct attribute_group arm_spe_pmu_cap_group = {
0167     .name   = "caps",
0168     .attrs  = arm_spe_pmu_cap_attr,
0169 };
0170 
0171 /* User ABI */
0172 #define ATTR_CFG_FLD_ts_enable_CFG      config  /* PMSCR_EL1.TS */
0173 #define ATTR_CFG_FLD_ts_enable_LO       0
0174 #define ATTR_CFG_FLD_ts_enable_HI       0
0175 #define ATTR_CFG_FLD_pa_enable_CFG      config  /* PMSCR_EL1.PA */
0176 #define ATTR_CFG_FLD_pa_enable_LO       1
0177 #define ATTR_CFG_FLD_pa_enable_HI       1
0178 #define ATTR_CFG_FLD_pct_enable_CFG     config  /* PMSCR_EL1.PCT */
0179 #define ATTR_CFG_FLD_pct_enable_LO      2
0180 #define ATTR_CFG_FLD_pct_enable_HI      2
0181 #define ATTR_CFG_FLD_jitter_CFG         config  /* PMSIRR_EL1.RND */
0182 #define ATTR_CFG_FLD_jitter_LO          16
0183 #define ATTR_CFG_FLD_jitter_HI          16
0184 #define ATTR_CFG_FLD_branch_filter_CFG      config  /* PMSFCR_EL1.B */
0185 #define ATTR_CFG_FLD_branch_filter_LO       32
0186 #define ATTR_CFG_FLD_branch_filter_HI       32
0187 #define ATTR_CFG_FLD_load_filter_CFG        config  /* PMSFCR_EL1.LD */
0188 #define ATTR_CFG_FLD_load_filter_LO     33
0189 #define ATTR_CFG_FLD_load_filter_HI     33
0190 #define ATTR_CFG_FLD_store_filter_CFG       config  /* PMSFCR_EL1.ST */
0191 #define ATTR_CFG_FLD_store_filter_LO        34
0192 #define ATTR_CFG_FLD_store_filter_HI        34
0193 
0194 #define ATTR_CFG_FLD_event_filter_CFG       config1 /* PMSEVFR_EL1 */
0195 #define ATTR_CFG_FLD_event_filter_LO        0
0196 #define ATTR_CFG_FLD_event_filter_HI        63
0197 
0198 #define ATTR_CFG_FLD_min_latency_CFG        config2 /* PMSLATFR_EL1.MINLAT */
0199 #define ATTR_CFG_FLD_min_latency_LO     0
0200 #define ATTR_CFG_FLD_min_latency_HI     11
0201 
0202 /* Why does everything I do descend into this? */
0203 #define __GEN_PMU_FORMAT_ATTR(cfg, lo, hi)              \
0204     (lo) == (hi) ? #cfg ":" #lo "\n" : #cfg ":" #lo "-" #hi
0205 
0206 #define _GEN_PMU_FORMAT_ATTR(cfg, lo, hi)               \
0207     __GEN_PMU_FORMAT_ATTR(cfg, lo, hi)
0208 
0209 #define GEN_PMU_FORMAT_ATTR(name)                   \
0210     PMU_FORMAT_ATTR(name,                       \
0211     _GEN_PMU_FORMAT_ATTR(ATTR_CFG_FLD_##name##_CFG,         \
0212                  ATTR_CFG_FLD_##name##_LO,          \
0213                  ATTR_CFG_FLD_##name##_HI))
0214 
0215 #define _ATTR_CFG_GET_FLD(attr, cfg, lo, hi)                \
0216     ((((attr)->cfg) >> lo) & GENMASK(hi - lo, 0))
0217 
0218 #define ATTR_CFG_GET_FLD(attr, name)                    \
0219     _ATTR_CFG_GET_FLD(attr,                     \
0220               ATTR_CFG_FLD_##name##_CFG,            \
0221               ATTR_CFG_FLD_##name##_LO,         \
0222               ATTR_CFG_FLD_##name##_HI)
0223 
0224 GEN_PMU_FORMAT_ATTR(ts_enable);
0225 GEN_PMU_FORMAT_ATTR(pa_enable);
0226 GEN_PMU_FORMAT_ATTR(pct_enable);
0227 GEN_PMU_FORMAT_ATTR(jitter);
0228 GEN_PMU_FORMAT_ATTR(branch_filter);
0229 GEN_PMU_FORMAT_ATTR(load_filter);
0230 GEN_PMU_FORMAT_ATTR(store_filter);
0231 GEN_PMU_FORMAT_ATTR(event_filter);
0232 GEN_PMU_FORMAT_ATTR(min_latency);
0233 
0234 static struct attribute *arm_spe_pmu_formats_attr[] = {
0235     &format_attr_ts_enable.attr,
0236     &format_attr_pa_enable.attr,
0237     &format_attr_pct_enable.attr,
0238     &format_attr_jitter.attr,
0239     &format_attr_branch_filter.attr,
0240     &format_attr_load_filter.attr,
0241     &format_attr_store_filter.attr,
0242     &format_attr_event_filter.attr,
0243     &format_attr_min_latency.attr,
0244     NULL,
0245 };
0246 
0247 static const struct attribute_group arm_spe_pmu_format_group = {
0248     .name   = "format",
0249     .attrs  = arm_spe_pmu_formats_attr,
0250 };
0251 
0252 static ssize_t cpumask_show(struct device *dev,
0253                 struct device_attribute *attr, char *buf)
0254 {
0255     struct arm_spe_pmu *spe_pmu = dev_get_drvdata(dev);
0256 
0257     return cpumap_print_to_pagebuf(true, buf, &spe_pmu->supported_cpus);
0258 }
0259 static DEVICE_ATTR_RO(cpumask);
0260 
0261 static struct attribute *arm_spe_pmu_attrs[] = {
0262     &dev_attr_cpumask.attr,
0263     NULL,
0264 };
0265 
0266 static const struct attribute_group arm_spe_pmu_group = {
0267     .attrs  = arm_spe_pmu_attrs,
0268 };
0269 
0270 static const struct attribute_group *arm_spe_pmu_attr_groups[] = {
0271     &arm_spe_pmu_group,
0272     &arm_spe_pmu_cap_group,
0273     &arm_spe_pmu_format_group,
0274     NULL,
0275 };
0276 
0277 /* Convert between user ABI and register values */
0278 static u64 arm_spe_event_to_pmscr(struct perf_event *event)
0279 {
0280     struct perf_event_attr *attr = &event->attr;
0281     u64 reg = 0;
0282 
0283     reg |= ATTR_CFG_GET_FLD(attr, ts_enable) << SYS_PMSCR_EL1_TS_SHIFT;
0284     reg |= ATTR_CFG_GET_FLD(attr, pa_enable) << SYS_PMSCR_EL1_PA_SHIFT;
0285     reg |= ATTR_CFG_GET_FLD(attr, pct_enable) << SYS_PMSCR_EL1_PCT_SHIFT;
0286 
0287     if (!attr->exclude_user)
0288         reg |= BIT(SYS_PMSCR_EL1_E0SPE_SHIFT);
0289 
0290     if (!attr->exclude_kernel)
0291         reg |= BIT(SYS_PMSCR_EL1_E1SPE_SHIFT);
0292 
0293     if (get_spe_event_has_cx(event))
0294         reg |= BIT(SYS_PMSCR_EL1_CX_SHIFT);
0295 
0296     return reg;
0297 }
0298 
0299 static void arm_spe_event_sanitise_period(struct perf_event *event)
0300 {
0301     struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
0302     u64 period = event->hw.sample_period;
0303     u64 max_period = SYS_PMSIRR_EL1_INTERVAL_MASK
0304              << SYS_PMSIRR_EL1_INTERVAL_SHIFT;
0305 
0306     if (period < spe_pmu->min_period)
0307         period = spe_pmu->min_period;
0308     else if (period > max_period)
0309         period = max_period;
0310     else
0311         period &= max_period;
0312 
0313     event->hw.sample_period = period;
0314 }
0315 
0316 static u64 arm_spe_event_to_pmsirr(struct perf_event *event)
0317 {
0318     struct perf_event_attr *attr = &event->attr;
0319     u64 reg = 0;
0320 
0321     arm_spe_event_sanitise_period(event);
0322 
0323     reg |= ATTR_CFG_GET_FLD(attr, jitter) << SYS_PMSIRR_EL1_RND_SHIFT;
0324     reg |= event->hw.sample_period;
0325 
0326     return reg;
0327 }
0328 
0329 static u64 arm_spe_event_to_pmsfcr(struct perf_event *event)
0330 {
0331     struct perf_event_attr *attr = &event->attr;
0332     u64 reg = 0;
0333 
0334     reg |= ATTR_CFG_GET_FLD(attr, load_filter) << SYS_PMSFCR_EL1_LD_SHIFT;
0335     reg |= ATTR_CFG_GET_FLD(attr, store_filter) << SYS_PMSFCR_EL1_ST_SHIFT;
0336     reg |= ATTR_CFG_GET_FLD(attr, branch_filter) << SYS_PMSFCR_EL1_B_SHIFT;
0337 
0338     if (reg)
0339         reg |= BIT(SYS_PMSFCR_EL1_FT_SHIFT);
0340 
0341     if (ATTR_CFG_GET_FLD(attr, event_filter))
0342         reg |= BIT(SYS_PMSFCR_EL1_FE_SHIFT);
0343 
0344     if (ATTR_CFG_GET_FLD(attr, min_latency))
0345         reg |= BIT(SYS_PMSFCR_EL1_FL_SHIFT);
0346 
0347     return reg;
0348 }
0349 
0350 static u64 arm_spe_event_to_pmsevfr(struct perf_event *event)
0351 {
0352     struct perf_event_attr *attr = &event->attr;
0353     return ATTR_CFG_GET_FLD(attr, event_filter);
0354 }
0355 
0356 static u64 arm_spe_event_to_pmslatfr(struct perf_event *event)
0357 {
0358     struct perf_event_attr *attr = &event->attr;
0359     return ATTR_CFG_GET_FLD(attr, min_latency)
0360            << SYS_PMSLATFR_EL1_MINLAT_SHIFT;
0361 }
0362 
0363 static void arm_spe_pmu_pad_buf(struct perf_output_handle *handle, int len)
0364 {
0365     struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
0366     u64 head = PERF_IDX2OFF(handle->head, buf);
0367 
0368     memset(buf->base + head, ARM_SPE_BUF_PAD_BYTE, len);
0369     if (!buf->snapshot)
0370         perf_aux_output_skip(handle, len);
0371 }
0372 
0373 static u64 arm_spe_pmu_next_snapshot_off(struct perf_output_handle *handle)
0374 {
0375     struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
0376     struct arm_spe_pmu *spe_pmu = to_spe_pmu(handle->event->pmu);
0377     u64 head = PERF_IDX2OFF(handle->head, buf);
0378     u64 limit = buf->nr_pages * PAGE_SIZE;
0379 
0380     /*
0381      * The trace format isn't parseable in reverse, so clamp
0382      * the limit to half of the buffer size in snapshot mode
0383      * so that the worst case is half a buffer of records, as
0384      * opposed to a single record.
0385      */
0386     if (head < limit >> 1)
0387         limit >>= 1;
0388 
0389     /*
0390      * If we're within max_record_sz of the limit, we must
0391      * pad, move the head index and recompute the limit.
0392      */
0393     if (limit - head < spe_pmu->max_record_sz) {
0394         arm_spe_pmu_pad_buf(handle, limit - head);
0395         handle->head = PERF_IDX2OFF(limit, buf);
0396         limit = ((buf->nr_pages * PAGE_SIZE) >> 1) + handle->head;
0397     }
0398 
0399     return limit;
0400 }
0401 
0402 static u64 __arm_spe_pmu_next_off(struct perf_output_handle *handle)
0403 {
0404     struct arm_spe_pmu *spe_pmu = to_spe_pmu(handle->event->pmu);
0405     struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
0406     const u64 bufsize = buf->nr_pages * PAGE_SIZE;
0407     u64 limit = bufsize;
0408     u64 head, tail, wakeup;
0409 
0410     /*
0411      * The head can be misaligned for two reasons:
0412      *
0413      * 1. The hardware left PMBPTR pointing to the first byte after
0414      *    a record when generating a buffer management event.
0415      *
0416      * 2. We used perf_aux_output_skip to consume handle->size bytes
0417      *    and CIRC_SPACE was used to compute the size, which always
0418      *    leaves one entry free.
0419      *
0420      * Deal with this by padding to the next alignment boundary and
0421      * moving the head index. If we run out of buffer space, we'll
0422      * reduce handle->size to zero and end up reporting truncation.
0423      */
0424     head = PERF_IDX2OFF(handle->head, buf);
0425     if (!IS_ALIGNED(head, spe_pmu->align)) {
0426         unsigned long delta = roundup(head, spe_pmu->align) - head;
0427 
0428         delta = min(delta, handle->size);
0429         arm_spe_pmu_pad_buf(handle, delta);
0430         head = PERF_IDX2OFF(handle->head, buf);
0431     }
0432 
0433     /* If we've run out of free space, then nothing more to do */
0434     if (!handle->size)
0435         goto no_space;
0436 
0437     /* Compute the tail and wakeup indices now that we've aligned head */
0438     tail = PERF_IDX2OFF(handle->head + handle->size, buf);
0439     wakeup = PERF_IDX2OFF(handle->wakeup, buf);
0440 
0441     /*
0442      * Avoid clobbering unconsumed data. We know we have space, so
0443      * if we see head == tail we know that the buffer is empty. If
0444      * head > tail, then there's nothing to clobber prior to
0445      * wrapping.
0446      */
0447     if (head < tail)
0448         limit = round_down(tail, PAGE_SIZE);
0449 
0450     /*
0451      * Wakeup may be arbitrarily far into the future. If it's not in
0452      * the current generation, either we'll wrap before hitting it,
0453      * or it's in the past and has been handled already.
0454      *
0455      * If there's a wakeup before we wrap, arrange to be woken up by
0456      * the page boundary following it. Keep the tail boundary if
0457      * that's lower.
0458      */
0459     if (handle->wakeup < (handle->head + handle->size) && head <= wakeup)
0460         limit = min(limit, round_up(wakeup, PAGE_SIZE));
0461 
0462     if (limit > head)
0463         return limit;
0464 
0465     arm_spe_pmu_pad_buf(handle, handle->size);
0466 no_space:
0467     perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED);
0468     perf_aux_output_end(handle, 0);
0469     return 0;
0470 }
0471 
0472 static u64 arm_spe_pmu_next_off(struct perf_output_handle *handle)
0473 {
0474     struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
0475     struct arm_spe_pmu *spe_pmu = to_spe_pmu(handle->event->pmu);
0476     u64 limit = __arm_spe_pmu_next_off(handle);
0477     u64 head = PERF_IDX2OFF(handle->head, buf);
0478 
0479     /*
0480      * If the head has come too close to the end of the buffer,
0481      * then pad to the end and recompute the limit.
0482      */
0483     if (limit && (limit - head < spe_pmu->max_record_sz)) {
0484         arm_spe_pmu_pad_buf(handle, limit - head);
0485         limit = __arm_spe_pmu_next_off(handle);
0486     }
0487 
0488     return limit;
0489 }
0490 
0491 static void arm_spe_perf_aux_output_begin(struct perf_output_handle *handle,
0492                       struct perf_event *event)
0493 {
0494     u64 base, limit;
0495     struct arm_spe_pmu_buf *buf;
0496 
0497     /* Start a new aux session */
0498     buf = perf_aux_output_begin(handle, event);
0499     if (!buf) {
0500         event->hw.state |= PERF_HES_STOPPED;
0501         /*
0502          * We still need to clear the limit pointer, since the
0503          * profiler might only be disabled by virtue of a fault.
0504          */
0505         limit = 0;
0506         goto out_write_limit;
0507     }
0508 
0509     limit = buf->snapshot ? arm_spe_pmu_next_snapshot_off(handle)
0510                   : arm_spe_pmu_next_off(handle);
0511     if (limit)
0512         limit |= BIT(SYS_PMBLIMITR_EL1_E_SHIFT);
0513 
0514     limit += (u64)buf->base;
0515     base = (u64)buf->base + PERF_IDX2OFF(handle->head, buf);
0516     write_sysreg_s(base, SYS_PMBPTR_EL1);
0517 
0518 out_write_limit:
0519     write_sysreg_s(limit, SYS_PMBLIMITR_EL1);
0520 }
0521 
0522 static void arm_spe_perf_aux_output_end(struct perf_output_handle *handle)
0523 {
0524     struct arm_spe_pmu_buf *buf = perf_get_aux(handle);
0525     u64 offset, size;
0526 
0527     offset = read_sysreg_s(SYS_PMBPTR_EL1) - (u64)buf->base;
0528     size = offset - PERF_IDX2OFF(handle->head, buf);
0529 
0530     if (buf->snapshot)
0531         handle->head = offset;
0532 
0533     perf_aux_output_end(handle, size);
0534 }
0535 
0536 static void arm_spe_pmu_disable_and_drain_local(void)
0537 {
0538     /* Disable profiling at EL0 and EL1 */
0539     write_sysreg_s(0, SYS_PMSCR_EL1);
0540     isb();
0541 
0542     /* Drain any buffered data */
0543     psb_csync();
0544     dsb(nsh);
0545 
0546     /* Disable the profiling buffer */
0547     write_sysreg_s(0, SYS_PMBLIMITR_EL1);
0548     isb();
0549 }
0550 
0551 /* IRQ handling */
0552 static enum arm_spe_pmu_buf_fault_action
0553 arm_spe_pmu_buf_get_fault_act(struct perf_output_handle *handle)
0554 {
0555     const char *err_str;
0556     u64 pmbsr;
0557     enum arm_spe_pmu_buf_fault_action ret;
0558 
0559     /*
0560      * Ensure new profiling data is visible to the CPU and any external
0561      * aborts have been resolved.
0562      */
0563     psb_csync();
0564     dsb(nsh);
0565 
0566     /* Ensure hardware updates to PMBPTR_EL1 are visible */
0567     isb();
0568 
0569     /* Service required? */
0570     pmbsr = read_sysreg_s(SYS_PMBSR_EL1);
0571     if (!(pmbsr & BIT(SYS_PMBSR_EL1_S_SHIFT)))
0572         return SPE_PMU_BUF_FAULT_ACT_SPURIOUS;
0573 
0574     /*
0575      * If we've lost data, disable profiling and also set the PARTIAL
0576      * flag to indicate that the last record is corrupted.
0577      */
0578     if (pmbsr & BIT(SYS_PMBSR_EL1_DL_SHIFT))
0579         perf_aux_output_flag(handle, PERF_AUX_FLAG_TRUNCATED |
0580                          PERF_AUX_FLAG_PARTIAL);
0581 
0582     /* Report collisions to userspace so that it can up the period */
0583     if (pmbsr & BIT(SYS_PMBSR_EL1_COLL_SHIFT))
0584         perf_aux_output_flag(handle, PERF_AUX_FLAG_COLLISION);
0585 
0586     /* We only expect buffer management events */
0587     switch (pmbsr & (SYS_PMBSR_EL1_EC_MASK << SYS_PMBSR_EL1_EC_SHIFT)) {
0588     case SYS_PMBSR_EL1_EC_BUF:
0589         /* Handled below */
0590         break;
0591     case SYS_PMBSR_EL1_EC_FAULT_S1:
0592     case SYS_PMBSR_EL1_EC_FAULT_S2:
0593         err_str = "Unexpected buffer fault";
0594         goto out_err;
0595     default:
0596         err_str = "Unknown error code";
0597         goto out_err;
0598     }
0599 
0600     /* Buffer management event */
0601     switch (pmbsr &
0602         (SYS_PMBSR_EL1_BUF_BSC_MASK << SYS_PMBSR_EL1_BUF_BSC_SHIFT)) {
0603     case SYS_PMBSR_EL1_BUF_BSC_FULL:
0604         ret = SPE_PMU_BUF_FAULT_ACT_OK;
0605         goto out_stop;
0606     default:
0607         err_str = "Unknown buffer status code";
0608     }
0609 
0610 out_err:
0611     pr_err_ratelimited("%s on CPU %d [PMBSR=0x%016llx, PMBPTR=0x%016llx, PMBLIMITR=0x%016llx]\n",
0612                err_str, smp_processor_id(), pmbsr,
0613                read_sysreg_s(SYS_PMBPTR_EL1),
0614                read_sysreg_s(SYS_PMBLIMITR_EL1));
0615     ret = SPE_PMU_BUF_FAULT_ACT_FATAL;
0616 
0617 out_stop:
0618     arm_spe_perf_aux_output_end(handle);
0619     return ret;
0620 }
0621 
0622 static irqreturn_t arm_spe_pmu_irq_handler(int irq, void *dev)
0623 {
0624     struct perf_output_handle *handle = dev;
0625     struct perf_event *event = handle->event;
0626     enum arm_spe_pmu_buf_fault_action act;
0627 
0628     if (!perf_get_aux(handle))
0629         return IRQ_NONE;
0630 
0631     act = arm_spe_pmu_buf_get_fault_act(handle);
0632     if (act == SPE_PMU_BUF_FAULT_ACT_SPURIOUS)
0633         return IRQ_NONE;
0634 
0635     /*
0636      * Ensure perf callbacks have completed, which may disable the
0637      * profiling buffer in response to a TRUNCATION flag.
0638      */
0639     irq_work_run();
0640 
0641     switch (act) {
0642     case SPE_PMU_BUF_FAULT_ACT_FATAL:
0643         /*
0644          * If a fatal exception occurred then leaving the profiling
0645          * buffer enabled is a recipe waiting to happen. Since
0646          * fatal faults don't always imply truncation, make sure
0647          * that the profiling buffer is disabled explicitly before
0648          * clearing the syndrome register.
0649          */
0650         arm_spe_pmu_disable_and_drain_local();
0651         break;
0652     case SPE_PMU_BUF_FAULT_ACT_OK:
0653         /*
0654          * We handled the fault (the buffer was full), so resume
0655          * profiling as long as we didn't detect truncation.
0656          * PMBPTR might be misaligned, but we'll burn that bridge
0657          * when we get to it.
0658          */
0659         if (!(handle->aux_flags & PERF_AUX_FLAG_TRUNCATED)) {
0660             arm_spe_perf_aux_output_begin(handle, event);
0661             isb();
0662         }
0663         break;
0664     case SPE_PMU_BUF_FAULT_ACT_SPURIOUS:
0665         /* We've seen you before, but GCC has the memory of a sieve. */
0666         break;
0667     }
0668 
0669     /* The buffer pointers are now sane, so resume profiling. */
0670     write_sysreg_s(0, SYS_PMBSR_EL1);
0671     return IRQ_HANDLED;
0672 }
0673 
0674 static u64 arm_spe_pmsevfr_res0(u16 pmsver)
0675 {
0676     switch (pmsver) {
0677     case ID_AA64DFR0_PMSVER_8_2:
0678         return SYS_PMSEVFR_EL1_RES0_8_2;
0679     case ID_AA64DFR0_PMSVER_8_3:
0680     /* Return the highest version we support in default */
0681     default:
0682         return SYS_PMSEVFR_EL1_RES0_8_3;
0683     }
0684 }
0685 
0686 /* Perf callbacks */
0687 static int arm_spe_pmu_event_init(struct perf_event *event)
0688 {
0689     u64 reg;
0690     struct perf_event_attr *attr = &event->attr;
0691     struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
0692 
0693     /* This is, of course, deeply driver-specific */
0694     if (attr->type != event->pmu->type)
0695         return -ENOENT;
0696 
0697     if (event->cpu >= 0 &&
0698         !cpumask_test_cpu(event->cpu, &spe_pmu->supported_cpus))
0699         return -ENOENT;
0700 
0701     if (arm_spe_event_to_pmsevfr(event) & arm_spe_pmsevfr_res0(spe_pmu->pmsver))
0702         return -EOPNOTSUPP;
0703 
0704     if (attr->exclude_idle)
0705         return -EOPNOTSUPP;
0706 
0707     /*
0708      * Feedback-directed frequency throttling doesn't work when we
0709      * have a buffer of samples. We'd need to manually count the
0710      * samples in the buffer when it fills up and adjust the event
0711      * count to reflect that. Instead, just force the user to specify
0712      * a sample period.
0713      */
0714     if (attr->freq)
0715         return -EINVAL;
0716 
0717     reg = arm_spe_event_to_pmsfcr(event);
0718     if ((reg & BIT(SYS_PMSFCR_EL1_FE_SHIFT)) &&
0719         !(spe_pmu->features & SPE_PMU_FEAT_FILT_EVT))
0720         return -EOPNOTSUPP;
0721 
0722     if ((reg & BIT(SYS_PMSFCR_EL1_FT_SHIFT)) &&
0723         !(spe_pmu->features & SPE_PMU_FEAT_FILT_TYP))
0724         return -EOPNOTSUPP;
0725 
0726     if ((reg & BIT(SYS_PMSFCR_EL1_FL_SHIFT)) &&
0727         !(spe_pmu->features & SPE_PMU_FEAT_FILT_LAT))
0728         return -EOPNOTSUPP;
0729 
0730     set_spe_event_has_cx(event);
0731     reg = arm_spe_event_to_pmscr(event);
0732     if (!perfmon_capable() &&
0733         (reg & (BIT(SYS_PMSCR_EL1_PA_SHIFT) |
0734             BIT(SYS_PMSCR_EL1_PCT_SHIFT))))
0735         return -EACCES;
0736 
0737     return 0;
0738 }
0739 
0740 static void arm_spe_pmu_start(struct perf_event *event, int flags)
0741 {
0742     u64 reg;
0743     struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
0744     struct hw_perf_event *hwc = &event->hw;
0745     struct perf_output_handle *handle = this_cpu_ptr(spe_pmu->handle);
0746 
0747     hwc->state = 0;
0748     arm_spe_perf_aux_output_begin(handle, event);
0749     if (hwc->state)
0750         return;
0751 
0752     reg = arm_spe_event_to_pmsfcr(event);
0753     write_sysreg_s(reg, SYS_PMSFCR_EL1);
0754 
0755     reg = arm_spe_event_to_pmsevfr(event);
0756     write_sysreg_s(reg, SYS_PMSEVFR_EL1);
0757 
0758     reg = arm_spe_event_to_pmslatfr(event);
0759     write_sysreg_s(reg, SYS_PMSLATFR_EL1);
0760 
0761     if (flags & PERF_EF_RELOAD) {
0762         reg = arm_spe_event_to_pmsirr(event);
0763         write_sysreg_s(reg, SYS_PMSIRR_EL1);
0764         isb();
0765         reg = local64_read(&hwc->period_left);
0766         write_sysreg_s(reg, SYS_PMSICR_EL1);
0767     }
0768 
0769     reg = arm_spe_event_to_pmscr(event);
0770     isb();
0771     write_sysreg_s(reg, SYS_PMSCR_EL1);
0772 }
0773 
0774 static void arm_spe_pmu_stop(struct perf_event *event, int flags)
0775 {
0776     struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
0777     struct hw_perf_event *hwc = &event->hw;
0778     struct perf_output_handle *handle = this_cpu_ptr(spe_pmu->handle);
0779 
0780     /* If we're already stopped, then nothing to do */
0781     if (hwc->state & PERF_HES_STOPPED)
0782         return;
0783 
0784     /* Stop all trace generation */
0785     arm_spe_pmu_disable_and_drain_local();
0786 
0787     if (flags & PERF_EF_UPDATE) {
0788         /*
0789          * If there's a fault pending then ensure we contain it
0790          * to this buffer, since we might be on the context-switch
0791          * path.
0792          */
0793         if (perf_get_aux(handle)) {
0794             enum arm_spe_pmu_buf_fault_action act;
0795 
0796             act = arm_spe_pmu_buf_get_fault_act(handle);
0797             if (act == SPE_PMU_BUF_FAULT_ACT_SPURIOUS)
0798                 arm_spe_perf_aux_output_end(handle);
0799             else
0800                 write_sysreg_s(0, SYS_PMBSR_EL1);
0801         }
0802 
0803         /*
0804          * This may also contain ECOUNT, but nobody else should
0805          * be looking at period_left, since we forbid frequency
0806          * based sampling.
0807          */
0808         local64_set(&hwc->period_left, read_sysreg_s(SYS_PMSICR_EL1));
0809         hwc->state |= PERF_HES_UPTODATE;
0810     }
0811 
0812     hwc->state |= PERF_HES_STOPPED;
0813 }
0814 
0815 static int arm_spe_pmu_add(struct perf_event *event, int flags)
0816 {
0817     int ret = 0;
0818     struct arm_spe_pmu *spe_pmu = to_spe_pmu(event->pmu);
0819     struct hw_perf_event *hwc = &event->hw;
0820     int cpu = event->cpu == -1 ? smp_processor_id() : event->cpu;
0821 
0822     if (!cpumask_test_cpu(cpu, &spe_pmu->supported_cpus))
0823         return -ENOENT;
0824 
0825     hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
0826 
0827     if (flags & PERF_EF_START) {
0828         arm_spe_pmu_start(event, PERF_EF_RELOAD);
0829         if (hwc->state & PERF_HES_STOPPED)
0830             ret = -EINVAL;
0831     }
0832 
0833     return ret;
0834 }
0835 
0836 static void arm_spe_pmu_del(struct perf_event *event, int flags)
0837 {
0838     arm_spe_pmu_stop(event, PERF_EF_UPDATE);
0839 }
0840 
0841 static void arm_spe_pmu_read(struct perf_event *event)
0842 {
0843 }
0844 
0845 static void *arm_spe_pmu_setup_aux(struct perf_event *event, void **pages,
0846                    int nr_pages, bool snapshot)
0847 {
0848     int i, cpu = event->cpu;
0849     struct page **pglist;
0850     struct arm_spe_pmu_buf *buf;
0851 
0852     /* We need at least two pages for this to work. */
0853     if (nr_pages < 2)
0854         return NULL;
0855 
0856     /*
0857      * We require an even number of pages for snapshot mode, so that
0858      * we can effectively treat the buffer as consisting of two equal
0859      * parts and give userspace a fighting chance of getting some
0860      * useful data out of it.
0861      */
0862     if (snapshot && (nr_pages & 1))
0863         return NULL;
0864 
0865     if (cpu == -1)
0866         cpu = raw_smp_processor_id();
0867 
0868     buf = kzalloc_node(sizeof(*buf), GFP_KERNEL, cpu_to_node(cpu));
0869     if (!buf)
0870         return NULL;
0871 
0872     pglist = kcalloc(nr_pages, sizeof(*pglist), GFP_KERNEL);
0873     if (!pglist)
0874         goto out_free_buf;
0875 
0876     for (i = 0; i < nr_pages; ++i)
0877         pglist[i] = virt_to_page(pages[i]);
0878 
0879     buf->base = vmap(pglist, nr_pages, VM_MAP, PAGE_KERNEL);
0880     if (!buf->base)
0881         goto out_free_pglist;
0882 
0883     buf->nr_pages   = nr_pages;
0884     buf->snapshot   = snapshot;
0885 
0886     kfree(pglist);
0887     return buf;
0888 
0889 out_free_pglist:
0890     kfree(pglist);
0891 out_free_buf:
0892     kfree(buf);
0893     return NULL;
0894 }
0895 
0896 static void arm_spe_pmu_free_aux(void *aux)
0897 {
0898     struct arm_spe_pmu_buf *buf = aux;
0899 
0900     vunmap(buf->base);
0901     kfree(buf);
0902 }
0903 
0904 /* Initialisation and teardown functions */
0905 static int arm_spe_pmu_perf_init(struct arm_spe_pmu *spe_pmu)
0906 {
0907     static atomic_t pmu_idx = ATOMIC_INIT(-1);
0908 
0909     int idx;
0910     char *name;
0911     struct device *dev = &spe_pmu->pdev->dev;
0912 
0913     spe_pmu->pmu = (struct pmu) {
0914         .module = THIS_MODULE,
0915         .capabilities   = PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE,
0916         .attr_groups    = arm_spe_pmu_attr_groups,
0917         /*
0918          * We hitch a ride on the software context here, so that
0919          * we can support per-task profiling (which is not possible
0920          * with the invalid context as it doesn't get sched callbacks).
0921          * This requires that userspace either uses a dummy event for
0922          * perf_event_open, since the aux buffer is not setup until
0923          * a subsequent mmap, or creates the profiling event in a
0924          * disabled state and explicitly PERF_EVENT_IOC_ENABLEs it
0925          * once the buffer has been created.
0926          */
0927         .task_ctx_nr    = perf_sw_context,
0928         .event_init = arm_spe_pmu_event_init,
0929         .add        = arm_spe_pmu_add,
0930         .del        = arm_spe_pmu_del,
0931         .start      = arm_spe_pmu_start,
0932         .stop       = arm_spe_pmu_stop,
0933         .read       = arm_spe_pmu_read,
0934         .setup_aux  = arm_spe_pmu_setup_aux,
0935         .free_aux   = arm_spe_pmu_free_aux,
0936     };
0937 
0938     idx = atomic_inc_return(&pmu_idx);
0939     name = devm_kasprintf(dev, GFP_KERNEL, "%s_%d", PMUNAME, idx);
0940     if (!name) {
0941         dev_err(dev, "failed to allocate name for pmu %d\n", idx);
0942         return -ENOMEM;
0943     }
0944 
0945     return perf_pmu_register(&spe_pmu->pmu, name, -1);
0946 }
0947 
0948 static void arm_spe_pmu_perf_destroy(struct arm_spe_pmu *spe_pmu)
0949 {
0950     perf_pmu_unregister(&spe_pmu->pmu);
0951 }
0952 
0953 static void __arm_spe_pmu_dev_probe(void *info)
0954 {
0955     int fld;
0956     u64 reg;
0957     struct arm_spe_pmu *spe_pmu = info;
0958     struct device *dev = &spe_pmu->pdev->dev;
0959 
0960     fld = cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64DFR0_EL1),
0961                            ID_AA64DFR0_PMSVER_SHIFT);
0962     if (!fld) {
0963         dev_err(dev,
0964             "unsupported ID_AA64DFR0_EL1.PMSVer [%d] on CPU %d\n",
0965             fld, smp_processor_id());
0966         return;
0967     }
0968     spe_pmu->pmsver = (u16)fld;
0969 
0970     /* Read PMBIDR first to determine whether or not we have access */
0971     reg = read_sysreg_s(SYS_PMBIDR_EL1);
0972     if (reg & BIT(SYS_PMBIDR_EL1_P_SHIFT)) {
0973         dev_err(dev,
0974             "profiling buffer owned by higher exception level\n");
0975         return;
0976     }
0977 
0978     /* Minimum alignment. If it's out-of-range, then fail the probe */
0979     fld = reg >> SYS_PMBIDR_EL1_ALIGN_SHIFT & SYS_PMBIDR_EL1_ALIGN_MASK;
0980     spe_pmu->align = 1 << fld;
0981     if (spe_pmu->align > SZ_2K) {
0982         dev_err(dev, "unsupported PMBIDR.Align [%d] on CPU %d\n",
0983             fld, smp_processor_id());
0984         return;
0985     }
0986 
0987     /* It's now safe to read PMSIDR and figure out what we've got */
0988     reg = read_sysreg_s(SYS_PMSIDR_EL1);
0989     if (reg & BIT(SYS_PMSIDR_EL1_FE_SHIFT))
0990         spe_pmu->features |= SPE_PMU_FEAT_FILT_EVT;
0991 
0992     if (reg & BIT(SYS_PMSIDR_EL1_FT_SHIFT))
0993         spe_pmu->features |= SPE_PMU_FEAT_FILT_TYP;
0994 
0995     if (reg & BIT(SYS_PMSIDR_EL1_FL_SHIFT))
0996         spe_pmu->features |= SPE_PMU_FEAT_FILT_LAT;
0997 
0998     if (reg & BIT(SYS_PMSIDR_EL1_ARCHINST_SHIFT))
0999         spe_pmu->features |= SPE_PMU_FEAT_ARCH_INST;
1000 
1001     if (reg & BIT(SYS_PMSIDR_EL1_LDS_SHIFT))
1002         spe_pmu->features |= SPE_PMU_FEAT_LDS;
1003 
1004     if (reg & BIT(SYS_PMSIDR_EL1_ERND_SHIFT))
1005         spe_pmu->features |= SPE_PMU_FEAT_ERND;
1006 
1007     /* This field has a spaced out encoding, so just use a look-up */
1008     fld = reg >> SYS_PMSIDR_EL1_INTERVAL_SHIFT & SYS_PMSIDR_EL1_INTERVAL_MASK;
1009     switch (fld) {
1010     case 0:
1011         spe_pmu->min_period = 256;
1012         break;
1013     case 2:
1014         spe_pmu->min_period = 512;
1015         break;
1016     case 3:
1017         spe_pmu->min_period = 768;
1018         break;
1019     case 4:
1020         spe_pmu->min_period = 1024;
1021         break;
1022     case 5:
1023         spe_pmu->min_period = 1536;
1024         break;
1025     case 6:
1026         spe_pmu->min_period = 2048;
1027         break;
1028     case 7:
1029         spe_pmu->min_period = 3072;
1030         break;
1031     default:
1032         dev_warn(dev, "unknown PMSIDR_EL1.Interval [%d]; assuming 8\n",
1033              fld);
1034         fallthrough;
1035     case 8:
1036         spe_pmu->min_period = 4096;
1037     }
1038 
1039     /* Maximum record size. If it's out-of-range, then fail the probe */
1040     fld = reg >> SYS_PMSIDR_EL1_MAXSIZE_SHIFT & SYS_PMSIDR_EL1_MAXSIZE_MASK;
1041     spe_pmu->max_record_sz = 1 << fld;
1042     if (spe_pmu->max_record_sz > SZ_2K || spe_pmu->max_record_sz < 16) {
1043         dev_err(dev, "unsupported PMSIDR_EL1.MaxSize [%d] on CPU %d\n",
1044             fld, smp_processor_id());
1045         return;
1046     }
1047 
1048     fld = reg >> SYS_PMSIDR_EL1_COUNTSIZE_SHIFT & SYS_PMSIDR_EL1_COUNTSIZE_MASK;
1049     switch (fld) {
1050     default:
1051         dev_warn(dev, "unknown PMSIDR_EL1.CountSize [%d]; assuming 2\n",
1052              fld);
1053         fallthrough;
1054     case 2:
1055         spe_pmu->counter_sz = 12;
1056         break;
1057     case 3:
1058         spe_pmu->counter_sz = 16;
1059     }
1060 
1061     dev_info(dev,
1062          "probed for CPUs %*pbl [max_record_sz %u, align %u, features 0x%llx]\n",
1063          cpumask_pr_args(&spe_pmu->supported_cpus),
1064          spe_pmu->max_record_sz, spe_pmu->align, spe_pmu->features);
1065 
1066     spe_pmu->features |= SPE_PMU_FEAT_DEV_PROBED;
1067 }
1068 
1069 static void __arm_spe_pmu_reset_local(void)
1070 {
1071     /*
1072      * This is probably overkill, as we have no idea where we're
1073      * draining any buffered data to...
1074      */
1075     arm_spe_pmu_disable_and_drain_local();
1076 
1077     /* Reset the buffer base pointer */
1078     write_sysreg_s(0, SYS_PMBPTR_EL1);
1079     isb();
1080 
1081     /* Clear any pending management interrupts */
1082     write_sysreg_s(0, SYS_PMBSR_EL1);
1083     isb();
1084 }
1085 
1086 static void __arm_spe_pmu_setup_one(void *info)
1087 {
1088     struct arm_spe_pmu *spe_pmu = info;
1089 
1090     __arm_spe_pmu_reset_local();
1091     enable_percpu_irq(spe_pmu->irq, IRQ_TYPE_NONE);
1092 }
1093 
1094 static void __arm_spe_pmu_stop_one(void *info)
1095 {
1096     struct arm_spe_pmu *spe_pmu = info;
1097 
1098     disable_percpu_irq(spe_pmu->irq);
1099     __arm_spe_pmu_reset_local();
1100 }
1101 
1102 static int arm_spe_pmu_cpu_startup(unsigned int cpu, struct hlist_node *node)
1103 {
1104     struct arm_spe_pmu *spe_pmu;
1105 
1106     spe_pmu = hlist_entry_safe(node, struct arm_spe_pmu, hotplug_node);
1107     if (!cpumask_test_cpu(cpu, &spe_pmu->supported_cpus))
1108         return 0;
1109 
1110     __arm_spe_pmu_setup_one(spe_pmu);
1111     return 0;
1112 }
1113 
1114 static int arm_spe_pmu_cpu_teardown(unsigned int cpu, struct hlist_node *node)
1115 {
1116     struct arm_spe_pmu *spe_pmu;
1117 
1118     spe_pmu = hlist_entry_safe(node, struct arm_spe_pmu, hotplug_node);
1119     if (!cpumask_test_cpu(cpu, &spe_pmu->supported_cpus))
1120         return 0;
1121 
1122     __arm_spe_pmu_stop_one(spe_pmu);
1123     return 0;
1124 }
1125 
1126 static int arm_spe_pmu_dev_init(struct arm_spe_pmu *spe_pmu)
1127 {
1128     int ret;
1129     cpumask_t *mask = &spe_pmu->supported_cpus;
1130 
1131     /* Make sure we probe the hardware on a relevant CPU */
1132     ret = smp_call_function_any(mask,  __arm_spe_pmu_dev_probe, spe_pmu, 1);
1133     if (ret || !(spe_pmu->features & SPE_PMU_FEAT_DEV_PROBED))
1134         return -ENXIO;
1135 
1136     /* Request our PPIs (note that the IRQ is still disabled) */
1137     ret = request_percpu_irq(spe_pmu->irq, arm_spe_pmu_irq_handler, DRVNAME,
1138                  spe_pmu->handle);
1139     if (ret)
1140         return ret;
1141 
1142     /*
1143      * Register our hotplug notifier now so we don't miss any events.
1144      * This will enable the IRQ for any supported CPUs that are already
1145      * up.
1146      */
1147     ret = cpuhp_state_add_instance(arm_spe_pmu_online,
1148                        &spe_pmu->hotplug_node);
1149     if (ret)
1150         free_percpu_irq(spe_pmu->irq, spe_pmu->handle);
1151 
1152     return ret;
1153 }
1154 
1155 static void arm_spe_pmu_dev_teardown(struct arm_spe_pmu *spe_pmu)
1156 {
1157     cpuhp_state_remove_instance(arm_spe_pmu_online, &spe_pmu->hotplug_node);
1158     free_percpu_irq(spe_pmu->irq, spe_pmu->handle);
1159 }
1160 
1161 /* Driver and device probing */
1162 static int arm_spe_pmu_irq_probe(struct arm_spe_pmu *spe_pmu)
1163 {
1164     struct platform_device *pdev = spe_pmu->pdev;
1165     int irq = platform_get_irq(pdev, 0);
1166 
1167     if (irq < 0)
1168         return -ENXIO;
1169 
1170     if (!irq_is_percpu(irq)) {
1171         dev_err(&pdev->dev, "expected PPI but got SPI (%d)\n", irq);
1172         return -EINVAL;
1173     }
1174 
1175     if (irq_get_percpu_devid_partition(irq, &spe_pmu->supported_cpus)) {
1176         dev_err(&pdev->dev, "failed to get PPI partition (%d)\n", irq);
1177         return -EINVAL;
1178     }
1179 
1180     spe_pmu->irq = irq;
1181     return 0;
1182 }
1183 
1184 static const struct of_device_id arm_spe_pmu_of_match[] = {
1185     { .compatible = "arm,statistical-profiling-extension-v1", .data = (void *)1 },
1186     { /* Sentinel */ },
1187 };
1188 MODULE_DEVICE_TABLE(of, arm_spe_pmu_of_match);
1189 
1190 static const struct platform_device_id arm_spe_match[] = {
1191     { ARMV8_SPE_PDEV_NAME, 0},
1192     { }
1193 };
1194 MODULE_DEVICE_TABLE(platform, arm_spe_match);
1195 
1196 static int arm_spe_pmu_device_probe(struct platform_device *pdev)
1197 {
1198     int ret;
1199     struct arm_spe_pmu *spe_pmu;
1200     struct device *dev = &pdev->dev;
1201 
1202     /*
1203      * If kernelspace is unmapped when running at EL0, then the SPE
1204      * buffer will fault and prematurely terminate the AUX session.
1205      */
1206     if (arm64_kernel_unmapped_at_el0()) {
1207         dev_warn_once(dev, "profiling buffer inaccessible. Try passing \"kpti=off\" on the kernel command line\n");
1208         return -EPERM;
1209     }
1210 
1211     spe_pmu = devm_kzalloc(dev, sizeof(*spe_pmu), GFP_KERNEL);
1212     if (!spe_pmu)
1213         return -ENOMEM;
1214 
1215     spe_pmu->handle = alloc_percpu(typeof(*spe_pmu->handle));
1216     if (!spe_pmu->handle)
1217         return -ENOMEM;
1218 
1219     spe_pmu->pdev = pdev;
1220     platform_set_drvdata(pdev, spe_pmu);
1221 
1222     ret = arm_spe_pmu_irq_probe(spe_pmu);
1223     if (ret)
1224         goto out_free_handle;
1225 
1226     ret = arm_spe_pmu_dev_init(spe_pmu);
1227     if (ret)
1228         goto out_free_handle;
1229 
1230     ret = arm_spe_pmu_perf_init(spe_pmu);
1231     if (ret)
1232         goto out_teardown_dev;
1233 
1234     return 0;
1235 
1236 out_teardown_dev:
1237     arm_spe_pmu_dev_teardown(spe_pmu);
1238 out_free_handle:
1239     free_percpu(spe_pmu->handle);
1240     return ret;
1241 }
1242 
1243 static int arm_spe_pmu_device_remove(struct platform_device *pdev)
1244 {
1245     struct arm_spe_pmu *spe_pmu = platform_get_drvdata(pdev);
1246 
1247     arm_spe_pmu_perf_destroy(spe_pmu);
1248     arm_spe_pmu_dev_teardown(spe_pmu);
1249     free_percpu(spe_pmu->handle);
1250     return 0;
1251 }
1252 
1253 static struct platform_driver arm_spe_pmu_driver = {
1254     .id_table = arm_spe_match,
1255     .driver = {
1256         .name       = DRVNAME,
1257         .of_match_table = of_match_ptr(arm_spe_pmu_of_match),
1258         .suppress_bind_attrs = true,
1259     },
1260     .probe  = arm_spe_pmu_device_probe,
1261     .remove = arm_spe_pmu_device_remove,
1262 };
1263 
1264 static int __init arm_spe_pmu_init(void)
1265 {
1266     int ret;
1267 
1268     ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DRVNAME,
1269                       arm_spe_pmu_cpu_startup,
1270                       arm_spe_pmu_cpu_teardown);
1271     if (ret < 0)
1272         return ret;
1273     arm_spe_pmu_online = ret;
1274 
1275     ret = platform_driver_register(&arm_spe_pmu_driver);
1276     if (ret)
1277         cpuhp_remove_multi_state(arm_spe_pmu_online);
1278 
1279     return ret;
1280 }
1281 
1282 static void __exit arm_spe_pmu_exit(void)
1283 {
1284     platform_driver_unregister(&arm_spe_pmu_driver);
1285     cpuhp_remove_multi_state(arm_spe_pmu_online);
1286 }
1287 
1288 module_init(arm_spe_pmu_init);
1289 module_exit(arm_spe_pmu_exit);
1290 
1291 MODULE_DESCRIPTION("Perf driver for the ARMv8.2 Statistical Profiling Extension");
1292 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
1293 MODULE_LICENSE("GPL v2");
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