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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *
0004  * Copyright (C) 2014 ARM Limited
0005  */
0006 
0007 #include <linux/ctype.h>
0008 #include <linux/hrtimer.h>
0009 #include <linux/idr.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/io.h>
0012 #include <linux/module.h>
0013 #include <linux/mod_devicetable.h>
0014 #include <linux/perf_event.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/slab.h>
0017 
0018 #define CCN_NUM_XP_PORTS 2
0019 #define CCN_NUM_VCS 4
0020 #define CCN_NUM_REGIONS 256
0021 #define CCN_REGION_SIZE 0x10000
0022 
0023 #define CCN_ALL_OLY_ID          0xff00
0024 #define CCN_ALL_OLY_ID__OLY_ID__SHIFT           0
0025 #define CCN_ALL_OLY_ID__OLY_ID__MASK            0x1f
0026 #define CCN_ALL_OLY_ID__NODE_ID__SHIFT          8
0027 #define CCN_ALL_OLY_ID__NODE_ID__MASK           0x3f
0028 
0029 #define CCN_MN_ERRINT_STATUS        0x0008
0030 #define CCN_MN_ERRINT_STATUS__INTREQ__DESSERT       0x11
0031 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__ENABLE    0x02
0032 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLED  0x20
0033 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE   0x22
0034 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_ENABLE   0x04
0035 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLED 0x40
0036 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLE  0x44
0037 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE    0x08
0038 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED  0x80
0039 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE   0x88
0040 #define CCN_MN_OLY_COMP_LIST_63_0   0x01e0
0041 #define CCN_MN_ERR_SIG_VAL_63_0     0x0300
0042 #define CCN_MN_ERR_SIG_VAL_63_0__DT         (1 << 1)
0043 
0044 #define CCN_DT_ACTIVE_DSM       0x0000
0045 #define CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(n)     ((n) * 8)
0046 #define CCN_DT_ACTIVE_DSM__DSM_ID__MASK         0xff
0047 #define CCN_DT_CTL          0x0028
0048 #define CCN_DT_CTL__DT_EN               (1 << 0)
0049 #define CCN_DT_PMEVCNT(n)       (0x0100 + (n) * 0x8)
0050 #define CCN_DT_PMCCNTR          0x0140
0051 #define CCN_DT_PMCCNTRSR        0x0190
0052 #define CCN_DT_PMOVSR           0x0198
0053 #define CCN_DT_PMOVSR_CLR       0x01a0
0054 #define CCN_DT_PMOVSR_CLR__MASK             0x1f
0055 #define CCN_DT_PMCR         0x01a8
0056 #define CCN_DT_PMCR__OVFL_INTR_EN           (1 << 6)
0057 #define CCN_DT_PMCR__PMU_EN             (1 << 0)
0058 #define CCN_DT_PMSR         0x01b0
0059 #define CCN_DT_PMSR_REQ         0x01b8
0060 #define CCN_DT_PMSR_CLR         0x01c0
0061 
0062 #define CCN_HNF_PMU_EVENT_SEL       0x0600
0063 #define CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(n)     ((n) * 4)
0064 #define CCN_HNF_PMU_EVENT_SEL__ID__MASK         0xf
0065 
0066 #define CCN_XP_DT_CONFIG        0x0300
0067 #define CCN_XP_DT_CONFIG__DT_CFG__SHIFT(n)      ((n) * 4)
0068 #define CCN_XP_DT_CONFIG__DT_CFG__MASK          0xf
0069 #define CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH      0x0
0070 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT_0_OR_1 0x1
0071 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(n)     (0x2 + (n))
0072 #define CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(n)   (0x4 + (n))
0073 #define CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(d, n) (0x8 + (d) * 4 + (n))
0074 #define CCN_XP_DT_INTERFACE_SEL     0x0308
0075 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(n)    (0 + (n) * 8)
0076 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK    0x1
0077 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(n)   (1 + (n) * 8)
0078 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK   0x1
0079 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(n)    (2 + (n) * 8)
0080 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK    0x3
0081 #define CCN_XP_DT_CMP_VAL_L(n)      (0x0310 + (n) * 0x40)
0082 #define CCN_XP_DT_CMP_VAL_H(n)      (0x0318 + (n) * 0x40)
0083 #define CCN_XP_DT_CMP_MASK_L(n)     (0x0320 + (n) * 0x40)
0084 #define CCN_XP_DT_CMP_MASK_H(n)     (0x0328 + (n) * 0x40)
0085 #define CCN_XP_DT_CONTROL       0x0370
0086 #define CCN_XP_DT_CONTROL__DT_ENABLE            (1 << 0)
0087 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(n)     (12 + (n) * 4)
0088 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__MASK     0xf
0089 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS       0xf
0090 #define CCN_XP_PMU_EVENT_SEL        0x0600
0091 #define CCN_XP_PMU_EVENT_SEL__ID__SHIFT(n)      ((n) * 7)
0092 #define CCN_XP_PMU_EVENT_SEL__ID__MASK          0x3f
0093 
0094 #define CCN_SBAS_PMU_EVENT_SEL      0x0600
0095 #define CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(n)        ((n) * 4)
0096 #define CCN_SBAS_PMU_EVENT_SEL__ID__MASK        0xf
0097 
0098 #define CCN_RNI_PMU_EVENT_SEL       0x0600
0099 #define CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(n)     ((n) * 4)
0100 #define CCN_RNI_PMU_EVENT_SEL__ID__MASK         0xf
0101 
0102 #define CCN_TYPE_MN 0x01
0103 #define CCN_TYPE_DT 0x02
0104 #define CCN_TYPE_HNF    0x04
0105 #define CCN_TYPE_HNI    0x05
0106 #define CCN_TYPE_XP 0x08
0107 #define CCN_TYPE_SBSX   0x0c
0108 #define CCN_TYPE_SBAS   0x10
0109 #define CCN_TYPE_RNI_1P 0x14
0110 #define CCN_TYPE_RNI_2P 0x15
0111 #define CCN_TYPE_RNI_3P 0x16
0112 #define CCN_TYPE_RND_1P 0x18 /* RN-D = RN-I + DVM */
0113 #define CCN_TYPE_RND_2P 0x19
0114 #define CCN_TYPE_RND_3P 0x1a
0115 #define CCN_TYPE_CYCLES 0xff /* Pseudotype */
0116 
0117 #define CCN_EVENT_WATCHPOINT 0xfe /* Pseudoevent */
0118 
0119 #define CCN_NUM_PMU_EVENTS      4
0120 #define CCN_NUM_XP_WATCHPOINTS      2 /* See DT.dbg_id.num_watchpoints */
0121 #define CCN_NUM_PMU_EVENT_COUNTERS  8 /* See DT.dbg_id.num_pmucntr */
0122 #define CCN_IDX_PMU_CYCLE_COUNTER   CCN_NUM_PMU_EVENT_COUNTERS
0123 
0124 #define CCN_NUM_PREDEFINED_MASKS    4
0125 #define CCN_IDX_MASK_ANY        (CCN_NUM_PMU_EVENT_COUNTERS + 0)
0126 #define CCN_IDX_MASK_EXACT      (CCN_NUM_PMU_EVENT_COUNTERS + 1)
0127 #define CCN_IDX_MASK_ORDER      (CCN_NUM_PMU_EVENT_COUNTERS + 2)
0128 #define CCN_IDX_MASK_OPCODE     (CCN_NUM_PMU_EVENT_COUNTERS + 3)
0129 
0130 struct arm_ccn_component {
0131     void __iomem *base;
0132     u32 type;
0133 
0134     DECLARE_BITMAP(pmu_events_mask, CCN_NUM_PMU_EVENTS);
0135     union {
0136         struct {
0137             DECLARE_BITMAP(dt_cmp_mask, CCN_NUM_XP_WATCHPOINTS);
0138         } xp;
0139     };
0140 };
0141 
0142 #define pmu_to_arm_ccn(_pmu) container_of(container_of(_pmu, \
0143     struct arm_ccn_dt, pmu), struct arm_ccn, dt)
0144 
0145 struct arm_ccn_dt {
0146     int id;
0147     void __iomem *base;
0148 
0149     spinlock_t config_lock;
0150 
0151     DECLARE_BITMAP(pmu_counters_mask, CCN_NUM_PMU_EVENT_COUNTERS + 1);
0152     struct {
0153         struct arm_ccn_component *source;
0154         struct perf_event *event;
0155     } pmu_counters[CCN_NUM_PMU_EVENT_COUNTERS + 1];
0156 
0157     struct {
0158            u64 l, h;
0159     } cmp_mask[CCN_NUM_PMU_EVENT_COUNTERS + CCN_NUM_PREDEFINED_MASKS];
0160 
0161     struct hrtimer hrtimer;
0162 
0163     unsigned int cpu;
0164     struct hlist_node node;
0165 
0166     struct pmu pmu;
0167 };
0168 
0169 struct arm_ccn {
0170     struct device *dev;
0171     void __iomem *base;
0172     unsigned int irq;
0173 
0174     unsigned sbas_present:1;
0175     unsigned sbsx_present:1;
0176 
0177     int num_nodes;
0178     struct arm_ccn_component *node;
0179 
0180     int num_xps;
0181     struct arm_ccn_component *xp;
0182 
0183     struct arm_ccn_dt dt;
0184     int mn_id;
0185 };
0186 
0187 static int arm_ccn_node_to_xp(int node)
0188 {
0189     return node / CCN_NUM_XP_PORTS;
0190 }
0191 
0192 static int arm_ccn_node_to_xp_port(int node)
0193 {
0194     return node % CCN_NUM_XP_PORTS;
0195 }
0196 
0197 
0198 /*
0199  * Bit shifts and masks in these defines must be kept in sync with
0200  * arm_ccn_pmu_config_set() and CCN_FORMAT_ATTRs below!
0201  */
0202 #define CCN_CONFIG_NODE(_config)    (((_config) >> 0) & 0xff)
0203 #define CCN_CONFIG_XP(_config)      (((_config) >> 0) & 0xff)
0204 #define CCN_CONFIG_TYPE(_config)    (((_config) >> 8) & 0xff)
0205 #define CCN_CONFIG_EVENT(_config)   (((_config) >> 16) & 0xff)
0206 #define CCN_CONFIG_PORT(_config)    (((_config) >> 24) & 0x3)
0207 #define CCN_CONFIG_BUS(_config)     (((_config) >> 24) & 0x3)
0208 #define CCN_CONFIG_VC(_config)      (((_config) >> 26) & 0x7)
0209 #define CCN_CONFIG_DIR(_config)     (((_config) >> 29) & 0x1)
0210 #define CCN_CONFIG_MASK(_config)    (((_config) >> 30) & 0xf)
0211 
0212 static void arm_ccn_pmu_config_set(u64 *config, u32 node_xp, u32 type, u32 port)
0213 {
0214     *config &= ~((0xff << 0) | (0xff << 8) | (0x3 << 24));
0215     *config |= (node_xp << 0) | (type << 8) | (port << 24);
0216 }
0217 
0218 static ssize_t arm_ccn_pmu_format_show(struct device *dev,
0219         struct device_attribute *attr, char *buf)
0220 {
0221     struct dev_ext_attribute *ea = container_of(attr,
0222             struct dev_ext_attribute, attr);
0223 
0224     return sysfs_emit(buf, "%s\n", (char *)ea->var);
0225 }
0226 
0227 #define CCN_FORMAT_ATTR(_name, _config) \
0228     struct dev_ext_attribute arm_ccn_pmu_format_attr_##_name = \
0229             { __ATTR(_name, S_IRUGO, arm_ccn_pmu_format_show, \
0230             NULL), _config }
0231 
0232 static CCN_FORMAT_ATTR(node, "config:0-7");
0233 static CCN_FORMAT_ATTR(xp, "config:0-7");
0234 static CCN_FORMAT_ATTR(type, "config:8-15");
0235 static CCN_FORMAT_ATTR(event, "config:16-23");
0236 static CCN_FORMAT_ATTR(port, "config:24-25");
0237 static CCN_FORMAT_ATTR(bus, "config:24-25");
0238 static CCN_FORMAT_ATTR(vc, "config:26-28");
0239 static CCN_FORMAT_ATTR(dir, "config:29-29");
0240 static CCN_FORMAT_ATTR(mask, "config:30-33");
0241 static CCN_FORMAT_ATTR(cmp_l, "config1:0-62");
0242 static CCN_FORMAT_ATTR(cmp_h, "config2:0-59");
0243 
0244 static struct attribute *arm_ccn_pmu_format_attrs[] = {
0245     &arm_ccn_pmu_format_attr_node.attr.attr,
0246     &arm_ccn_pmu_format_attr_xp.attr.attr,
0247     &arm_ccn_pmu_format_attr_type.attr.attr,
0248     &arm_ccn_pmu_format_attr_event.attr.attr,
0249     &arm_ccn_pmu_format_attr_port.attr.attr,
0250     &arm_ccn_pmu_format_attr_bus.attr.attr,
0251     &arm_ccn_pmu_format_attr_vc.attr.attr,
0252     &arm_ccn_pmu_format_attr_dir.attr.attr,
0253     &arm_ccn_pmu_format_attr_mask.attr.attr,
0254     &arm_ccn_pmu_format_attr_cmp_l.attr.attr,
0255     &arm_ccn_pmu_format_attr_cmp_h.attr.attr,
0256     NULL
0257 };
0258 
0259 static const struct attribute_group arm_ccn_pmu_format_attr_group = {
0260     .name = "format",
0261     .attrs = arm_ccn_pmu_format_attrs,
0262 };
0263 
0264 
0265 struct arm_ccn_pmu_event {
0266     struct device_attribute attr;
0267     u32 type;
0268     u32 event;
0269     int num_ports;
0270     int num_vcs;
0271     const char *def;
0272     int mask;
0273 };
0274 
0275 #define CCN_EVENT_ATTR(_name) \
0276     __ATTR(_name, S_IRUGO, arm_ccn_pmu_event_show, NULL)
0277 
0278 /*
0279  * Events defined in TRM for MN, HN-I and SBSX are actually watchpoints set on
0280  * their ports in XP they are connected to. For the sake of usability they are
0281  * explicitly defined here (and translated into a relevant watchpoint in
0282  * arm_ccn_pmu_event_init()) so the user can easily request them without deep
0283  * knowledge of the flit format.
0284  */
0285 
0286 #define CCN_EVENT_MN(_name, _def, _mask) { .attr = CCN_EVENT_ATTR(mn_##_name), \
0287         .type = CCN_TYPE_MN, .event = CCN_EVENT_WATCHPOINT, \
0288         .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, \
0289         .def = _def, .mask = _mask, }
0290 
0291 #define CCN_EVENT_HNI(_name, _def, _mask) { \
0292         .attr = CCN_EVENT_ATTR(hni_##_name), .type = CCN_TYPE_HNI, \
0293         .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
0294         .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
0295 
0296 #define CCN_EVENT_SBSX(_name, _def, _mask) { \
0297         .attr = CCN_EVENT_ATTR(sbsx_##_name), .type = CCN_TYPE_SBSX, \
0298         .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
0299         .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
0300 
0301 #define CCN_EVENT_HNF(_name, _event) { .attr = CCN_EVENT_ATTR(hnf_##_name), \
0302         .type = CCN_TYPE_HNF, .event = _event, }
0303 
0304 #define CCN_EVENT_XP(_name, _event) { .attr = CCN_EVENT_ATTR(xp_##_name), \
0305         .type = CCN_TYPE_XP, .event = _event, \
0306         .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, }
0307 
0308 /*
0309  * RN-I & RN-D (RN-D = RN-I + DVM) nodes have different type ID depending
0310  * on configuration. One of them is picked to represent the whole group,
0311  * as they all share the same event types.
0312  */
0313 #define CCN_EVENT_RNI(_name, _event) { .attr = CCN_EVENT_ATTR(rni_##_name), \
0314         .type = CCN_TYPE_RNI_3P, .event = _event, }
0315 
0316 #define CCN_EVENT_SBAS(_name, _event) { .attr = CCN_EVENT_ATTR(sbas_##_name), \
0317         .type = CCN_TYPE_SBAS, .event = _event, }
0318 
0319 #define CCN_EVENT_CYCLES(_name) { .attr = CCN_EVENT_ATTR(_name), \
0320         .type = CCN_TYPE_CYCLES }
0321 
0322 
0323 static ssize_t arm_ccn_pmu_event_show(struct device *dev,
0324         struct device_attribute *attr, char *buf)
0325 {
0326     struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
0327     struct arm_ccn_pmu_event *event = container_of(attr,
0328             struct arm_ccn_pmu_event, attr);
0329     int res;
0330 
0331     res = sysfs_emit(buf, "type=0x%x", event->type);
0332     if (event->event)
0333         res += sysfs_emit_at(buf, res, ",event=0x%x", event->event);
0334     if (event->def)
0335         res += sysfs_emit_at(buf, res, ",%s", event->def);
0336     if (event->mask)
0337         res += sysfs_emit_at(buf, res, ",mask=0x%x", event->mask);
0338 
0339     /* Arguments required by an event */
0340     switch (event->type) {
0341     case CCN_TYPE_CYCLES:
0342         break;
0343     case CCN_TYPE_XP:
0344         res += sysfs_emit_at(buf, res, ",xp=?,vc=?");
0345         if (event->event == CCN_EVENT_WATCHPOINT)
0346             res += sysfs_emit_at(buf, res,
0347                     ",port=?,dir=?,cmp_l=?,cmp_h=?,mask=?");
0348         else
0349             res += sysfs_emit_at(buf, res, ",bus=?");
0350 
0351         break;
0352     case CCN_TYPE_MN:
0353         res += sysfs_emit_at(buf, res, ",node=%d", ccn->mn_id);
0354         break;
0355     default:
0356         res += sysfs_emit_at(buf, res, ",node=?");
0357         break;
0358     }
0359 
0360     res += sysfs_emit_at(buf, res, "\n");
0361 
0362     return res;
0363 }
0364 
0365 static umode_t arm_ccn_pmu_events_is_visible(struct kobject *kobj,
0366                      struct attribute *attr, int index)
0367 {
0368     struct device *dev = kobj_to_dev(kobj);
0369     struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
0370     struct device_attribute *dev_attr = container_of(attr,
0371             struct device_attribute, attr);
0372     struct arm_ccn_pmu_event *event = container_of(dev_attr,
0373             struct arm_ccn_pmu_event, attr);
0374 
0375     if (event->type == CCN_TYPE_SBAS && !ccn->sbas_present)
0376         return 0;
0377     if (event->type == CCN_TYPE_SBSX && !ccn->sbsx_present)
0378         return 0;
0379 
0380     return attr->mode;
0381 }
0382 
0383 static struct arm_ccn_pmu_event arm_ccn_pmu_events[] = {
0384     CCN_EVENT_MN(eobarrier, "dir=1,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE),
0385     CCN_EVENT_MN(ecbarrier, "dir=1,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE),
0386     CCN_EVENT_MN(dvmop, "dir=1,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE),
0387     CCN_EVENT_HNI(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
0388     CCN_EVENT_HNI(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
0389     CCN_EVENT_HNI(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
0390     CCN_EVENT_HNI(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
0391     CCN_EVENT_HNI(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
0392             CCN_IDX_MASK_ORDER),
0393     CCN_EVENT_SBSX(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
0394     CCN_EVENT_SBSX(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
0395     CCN_EVENT_SBSX(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
0396     CCN_EVENT_SBSX(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
0397     CCN_EVENT_SBSX(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
0398             CCN_IDX_MASK_ORDER),
0399     CCN_EVENT_HNF(cache_miss, 0x1),
0400     CCN_EVENT_HNF(l3_sf_cache_access, 0x02),
0401     CCN_EVENT_HNF(cache_fill, 0x3),
0402     CCN_EVENT_HNF(pocq_retry, 0x4),
0403     CCN_EVENT_HNF(pocq_reqs_recvd, 0x5),
0404     CCN_EVENT_HNF(sf_hit, 0x6),
0405     CCN_EVENT_HNF(sf_evictions, 0x7),
0406     CCN_EVENT_HNF(snoops_sent, 0x8),
0407     CCN_EVENT_HNF(snoops_broadcast, 0x9),
0408     CCN_EVENT_HNF(l3_eviction, 0xa),
0409     CCN_EVENT_HNF(l3_fill_invalid_way, 0xb),
0410     CCN_EVENT_HNF(mc_retries, 0xc),
0411     CCN_EVENT_HNF(mc_reqs, 0xd),
0412     CCN_EVENT_HNF(qos_hh_retry, 0xe),
0413     CCN_EVENT_RNI(rdata_beats_p0, 0x1),
0414     CCN_EVENT_RNI(rdata_beats_p1, 0x2),
0415     CCN_EVENT_RNI(rdata_beats_p2, 0x3),
0416     CCN_EVENT_RNI(rxdat_flits, 0x4),
0417     CCN_EVENT_RNI(txdat_flits, 0x5),
0418     CCN_EVENT_RNI(txreq_flits, 0x6),
0419     CCN_EVENT_RNI(txreq_flits_retried, 0x7),
0420     CCN_EVENT_RNI(rrt_full, 0x8),
0421     CCN_EVENT_RNI(wrt_full, 0x9),
0422     CCN_EVENT_RNI(txreq_flits_replayed, 0xa),
0423     CCN_EVENT_XP(upload_starvation, 0x1),
0424     CCN_EVENT_XP(download_starvation, 0x2),
0425     CCN_EVENT_XP(respin, 0x3),
0426     CCN_EVENT_XP(valid_flit, 0x4),
0427     CCN_EVENT_XP(watchpoint, CCN_EVENT_WATCHPOINT),
0428     CCN_EVENT_SBAS(rdata_beats_p0, 0x1),
0429     CCN_EVENT_SBAS(rxdat_flits, 0x4),
0430     CCN_EVENT_SBAS(txdat_flits, 0x5),
0431     CCN_EVENT_SBAS(txreq_flits, 0x6),
0432     CCN_EVENT_SBAS(txreq_flits_retried, 0x7),
0433     CCN_EVENT_SBAS(rrt_full, 0x8),
0434     CCN_EVENT_SBAS(wrt_full, 0x9),
0435     CCN_EVENT_SBAS(txreq_flits_replayed, 0xa),
0436     CCN_EVENT_CYCLES(cycles),
0437 };
0438 
0439 /* Populated in arm_ccn_init() */
0440 static struct attribute
0441         *arm_ccn_pmu_events_attrs[ARRAY_SIZE(arm_ccn_pmu_events) + 1];
0442 
0443 static const struct attribute_group arm_ccn_pmu_events_attr_group = {
0444     .name = "events",
0445     .is_visible = arm_ccn_pmu_events_is_visible,
0446     .attrs = arm_ccn_pmu_events_attrs,
0447 };
0448 
0449 
0450 static u64 *arm_ccn_pmu_get_cmp_mask(struct arm_ccn *ccn, const char *name)
0451 {
0452     unsigned long i;
0453 
0454     if (WARN_ON(!name || !name[0] || !isxdigit(name[0]) || !name[1]))
0455         return NULL;
0456     i = isdigit(name[0]) ? name[0] - '0' : 0xa + tolower(name[0]) - 'a';
0457 
0458     switch (name[1]) {
0459     case 'l':
0460         return &ccn->dt.cmp_mask[i].l;
0461     case 'h':
0462         return &ccn->dt.cmp_mask[i].h;
0463     default:
0464         return NULL;
0465     }
0466 }
0467 
0468 static ssize_t arm_ccn_pmu_cmp_mask_show(struct device *dev,
0469         struct device_attribute *attr, char *buf)
0470 {
0471     struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
0472     u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
0473 
0474     return mask ? sysfs_emit(buf, "0x%016llx\n", *mask) : -EINVAL;
0475 }
0476 
0477 static ssize_t arm_ccn_pmu_cmp_mask_store(struct device *dev,
0478         struct device_attribute *attr, const char *buf, size_t count)
0479 {
0480     struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
0481     u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
0482     int err = -EINVAL;
0483 
0484     if (mask)
0485         err = kstrtoull(buf, 0, mask);
0486 
0487     return err ? err : count;
0488 }
0489 
0490 #define CCN_CMP_MASK_ATTR(_name) \
0491     struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
0492             __ATTR(_name, S_IRUGO | S_IWUSR, \
0493             arm_ccn_pmu_cmp_mask_show, arm_ccn_pmu_cmp_mask_store)
0494 
0495 #define CCN_CMP_MASK_ATTR_RO(_name) \
0496     struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
0497             __ATTR(_name, S_IRUGO, arm_ccn_pmu_cmp_mask_show, NULL)
0498 
0499 static CCN_CMP_MASK_ATTR(0l);
0500 static CCN_CMP_MASK_ATTR(0h);
0501 static CCN_CMP_MASK_ATTR(1l);
0502 static CCN_CMP_MASK_ATTR(1h);
0503 static CCN_CMP_MASK_ATTR(2l);
0504 static CCN_CMP_MASK_ATTR(2h);
0505 static CCN_CMP_MASK_ATTR(3l);
0506 static CCN_CMP_MASK_ATTR(3h);
0507 static CCN_CMP_MASK_ATTR(4l);
0508 static CCN_CMP_MASK_ATTR(4h);
0509 static CCN_CMP_MASK_ATTR(5l);
0510 static CCN_CMP_MASK_ATTR(5h);
0511 static CCN_CMP_MASK_ATTR(6l);
0512 static CCN_CMP_MASK_ATTR(6h);
0513 static CCN_CMP_MASK_ATTR(7l);
0514 static CCN_CMP_MASK_ATTR(7h);
0515 static CCN_CMP_MASK_ATTR_RO(8l);
0516 static CCN_CMP_MASK_ATTR_RO(8h);
0517 static CCN_CMP_MASK_ATTR_RO(9l);
0518 static CCN_CMP_MASK_ATTR_RO(9h);
0519 static CCN_CMP_MASK_ATTR_RO(al);
0520 static CCN_CMP_MASK_ATTR_RO(ah);
0521 static CCN_CMP_MASK_ATTR_RO(bl);
0522 static CCN_CMP_MASK_ATTR_RO(bh);
0523 
0524 static struct attribute *arm_ccn_pmu_cmp_mask_attrs[] = {
0525     &arm_ccn_pmu_cmp_mask_attr_0l.attr, &arm_ccn_pmu_cmp_mask_attr_0h.attr,
0526     &arm_ccn_pmu_cmp_mask_attr_1l.attr, &arm_ccn_pmu_cmp_mask_attr_1h.attr,
0527     &arm_ccn_pmu_cmp_mask_attr_2l.attr, &arm_ccn_pmu_cmp_mask_attr_2h.attr,
0528     &arm_ccn_pmu_cmp_mask_attr_3l.attr, &arm_ccn_pmu_cmp_mask_attr_3h.attr,
0529     &arm_ccn_pmu_cmp_mask_attr_4l.attr, &arm_ccn_pmu_cmp_mask_attr_4h.attr,
0530     &arm_ccn_pmu_cmp_mask_attr_5l.attr, &arm_ccn_pmu_cmp_mask_attr_5h.attr,
0531     &arm_ccn_pmu_cmp_mask_attr_6l.attr, &arm_ccn_pmu_cmp_mask_attr_6h.attr,
0532     &arm_ccn_pmu_cmp_mask_attr_7l.attr, &arm_ccn_pmu_cmp_mask_attr_7h.attr,
0533     &arm_ccn_pmu_cmp_mask_attr_8l.attr, &arm_ccn_pmu_cmp_mask_attr_8h.attr,
0534     &arm_ccn_pmu_cmp_mask_attr_9l.attr, &arm_ccn_pmu_cmp_mask_attr_9h.attr,
0535     &arm_ccn_pmu_cmp_mask_attr_al.attr, &arm_ccn_pmu_cmp_mask_attr_ah.attr,
0536     &arm_ccn_pmu_cmp_mask_attr_bl.attr, &arm_ccn_pmu_cmp_mask_attr_bh.attr,
0537     NULL
0538 };
0539 
0540 static const struct attribute_group arm_ccn_pmu_cmp_mask_attr_group = {
0541     .name = "cmp_mask",
0542     .attrs = arm_ccn_pmu_cmp_mask_attrs,
0543 };
0544 
0545 static ssize_t arm_ccn_pmu_cpumask_show(struct device *dev,
0546                      struct device_attribute *attr, char *buf)
0547 {
0548     struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
0549 
0550     return cpumap_print_to_pagebuf(true, buf, cpumask_of(ccn->dt.cpu));
0551 }
0552 
0553 static struct device_attribute arm_ccn_pmu_cpumask_attr =
0554         __ATTR(cpumask, S_IRUGO, arm_ccn_pmu_cpumask_show, NULL);
0555 
0556 static struct attribute *arm_ccn_pmu_cpumask_attrs[] = {
0557     &arm_ccn_pmu_cpumask_attr.attr,
0558     NULL,
0559 };
0560 
0561 static const struct attribute_group arm_ccn_pmu_cpumask_attr_group = {
0562     .attrs = arm_ccn_pmu_cpumask_attrs,
0563 };
0564 
0565 /*
0566  * Default poll period is 10ms, which is way over the top anyway,
0567  * as in the worst case scenario (an event every cycle), with 1GHz
0568  * clocked bus, the smallest, 32 bit counter will overflow in
0569  * more than 4s.
0570  */
0571 static unsigned int arm_ccn_pmu_poll_period_us = 10000;
0572 module_param_named(pmu_poll_period_us, arm_ccn_pmu_poll_period_us, uint,
0573         S_IRUGO | S_IWUSR);
0574 
0575 static ktime_t arm_ccn_pmu_timer_period(void)
0576 {
0577     return ns_to_ktime((u64)arm_ccn_pmu_poll_period_us * 1000);
0578 }
0579 
0580 
0581 static const struct attribute_group *arm_ccn_pmu_attr_groups[] = {
0582     &arm_ccn_pmu_events_attr_group,
0583     &arm_ccn_pmu_format_attr_group,
0584     &arm_ccn_pmu_cmp_mask_attr_group,
0585     &arm_ccn_pmu_cpumask_attr_group,
0586     NULL
0587 };
0588 
0589 
0590 static int arm_ccn_pmu_alloc_bit(unsigned long *bitmap, unsigned long size)
0591 {
0592     int bit;
0593 
0594     do {
0595         bit = find_first_zero_bit(bitmap, size);
0596         if (bit >= size)
0597             return -EAGAIN;
0598     } while (test_and_set_bit(bit, bitmap));
0599 
0600     return bit;
0601 }
0602 
0603 /* All RN-I and RN-D nodes have identical PMUs */
0604 static int arm_ccn_pmu_type_eq(u32 a, u32 b)
0605 {
0606     if (a == b)
0607         return 1;
0608 
0609     switch (a) {
0610     case CCN_TYPE_RNI_1P:
0611     case CCN_TYPE_RNI_2P:
0612     case CCN_TYPE_RNI_3P:
0613     case CCN_TYPE_RND_1P:
0614     case CCN_TYPE_RND_2P:
0615     case CCN_TYPE_RND_3P:
0616         switch (b) {
0617         case CCN_TYPE_RNI_1P:
0618         case CCN_TYPE_RNI_2P:
0619         case CCN_TYPE_RNI_3P:
0620         case CCN_TYPE_RND_1P:
0621         case CCN_TYPE_RND_2P:
0622         case CCN_TYPE_RND_3P:
0623             return 1;
0624         }
0625         break;
0626     }
0627 
0628     return 0;
0629 }
0630 
0631 static int arm_ccn_pmu_event_alloc(struct perf_event *event)
0632 {
0633     struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
0634     struct hw_perf_event *hw = &event->hw;
0635     u32 node_xp, type, event_id;
0636     struct arm_ccn_component *source;
0637     int bit;
0638 
0639     node_xp = CCN_CONFIG_NODE(event->attr.config);
0640     type = CCN_CONFIG_TYPE(event->attr.config);
0641     event_id = CCN_CONFIG_EVENT(event->attr.config);
0642 
0643     /* Allocate the cycle counter */
0644     if (type == CCN_TYPE_CYCLES) {
0645         if (test_and_set_bit(CCN_IDX_PMU_CYCLE_COUNTER,
0646                 ccn->dt.pmu_counters_mask))
0647             return -EAGAIN;
0648 
0649         hw->idx = CCN_IDX_PMU_CYCLE_COUNTER;
0650         ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event;
0651 
0652         return 0;
0653     }
0654 
0655     /* Allocate an event counter */
0656     hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask,
0657             CCN_NUM_PMU_EVENT_COUNTERS);
0658     if (hw->idx < 0) {
0659         dev_dbg(ccn->dev, "No more counters available!\n");
0660         return -EAGAIN;
0661     }
0662 
0663     if (type == CCN_TYPE_XP)
0664         source = &ccn->xp[node_xp];
0665     else
0666         source = &ccn->node[node_xp];
0667     ccn->dt.pmu_counters[hw->idx].source = source;
0668 
0669     /* Allocate an event source or a watchpoint */
0670     if (type == CCN_TYPE_XP && event_id == CCN_EVENT_WATCHPOINT)
0671         bit = arm_ccn_pmu_alloc_bit(source->xp.dt_cmp_mask,
0672                 CCN_NUM_XP_WATCHPOINTS);
0673     else
0674         bit = arm_ccn_pmu_alloc_bit(source->pmu_events_mask,
0675                 CCN_NUM_PMU_EVENTS);
0676     if (bit < 0) {
0677         dev_dbg(ccn->dev, "No more event sources/watchpoints on node/XP %d!\n",
0678                 node_xp);
0679         clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
0680         return -EAGAIN;
0681     }
0682     hw->config_base = bit;
0683 
0684     ccn->dt.pmu_counters[hw->idx].event = event;
0685 
0686     return 0;
0687 }
0688 
0689 static void arm_ccn_pmu_event_release(struct perf_event *event)
0690 {
0691     struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
0692     struct hw_perf_event *hw = &event->hw;
0693 
0694     if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) {
0695         clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask);
0696     } else {
0697         struct arm_ccn_component *source =
0698                 ccn->dt.pmu_counters[hw->idx].source;
0699 
0700         if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP &&
0701                 CCN_CONFIG_EVENT(event->attr.config) ==
0702                 CCN_EVENT_WATCHPOINT)
0703             clear_bit(hw->config_base, source->xp.dt_cmp_mask);
0704         else
0705             clear_bit(hw->config_base, source->pmu_events_mask);
0706         clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
0707     }
0708 
0709     ccn->dt.pmu_counters[hw->idx].source = NULL;
0710     ccn->dt.pmu_counters[hw->idx].event = NULL;
0711 }
0712 
0713 static int arm_ccn_pmu_event_init(struct perf_event *event)
0714 {
0715     struct arm_ccn *ccn;
0716     struct hw_perf_event *hw = &event->hw;
0717     u32 node_xp, type, event_id;
0718     int valid;
0719     int i;
0720     struct perf_event *sibling;
0721 
0722     if (event->attr.type != event->pmu->type)
0723         return -ENOENT;
0724 
0725     ccn = pmu_to_arm_ccn(event->pmu);
0726 
0727     if (hw->sample_period) {
0728         dev_dbg(ccn->dev, "Sampling not supported!\n");
0729         return -EOPNOTSUPP;
0730     }
0731 
0732     if (has_branch_stack(event)) {
0733         dev_dbg(ccn->dev, "Can't exclude execution levels!\n");
0734         return -EINVAL;
0735     }
0736 
0737     if (event->cpu < 0) {
0738         dev_dbg(ccn->dev, "Can't provide per-task data!\n");
0739         return -EOPNOTSUPP;
0740     }
0741     /*
0742      * Many perf core operations (eg. events rotation) operate on a
0743      * single CPU context. This is obvious for CPU PMUs, where one
0744      * expects the same sets of events being observed on all CPUs,
0745      * but can lead to issues for off-core PMUs, like CCN, where each
0746      * event could be theoretically assigned to a different CPU. To
0747      * mitigate this, we enforce CPU assignment to one, selected
0748      * processor (the one described in the "cpumask" attribute).
0749      */
0750     event->cpu = ccn->dt.cpu;
0751 
0752     node_xp = CCN_CONFIG_NODE(event->attr.config);
0753     type = CCN_CONFIG_TYPE(event->attr.config);
0754     event_id = CCN_CONFIG_EVENT(event->attr.config);
0755 
0756     /* Validate node/xp vs topology */
0757     switch (type) {
0758     case CCN_TYPE_MN:
0759         if (node_xp != ccn->mn_id) {
0760             dev_dbg(ccn->dev, "Invalid MN ID %d!\n", node_xp);
0761             return -EINVAL;
0762         }
0763         break;
0764     case CCN_TYPE_XP:
0765         if (node_xp >= ccn->num_xps) {
0766             dev_dbg(ccn->dev, "Invalid XP ID %d!\n", node_xp);
0767             return -EINVAL;
0768         }
0769         break;
0770     case CCN_TYPE_CYCLES:
0771         break;
0772     default:
0773         if (node_xp >= ccn->num_nodes) {
0774             dev_dbg(ccn->dev, "Invalid node ID %d!\n", node_xp);
0775             return -EINVAL;
0776         }
0777         if (!arm_ccn_pmu_type_eq(type, ccn->node[node_xp].type)) {
0778             dev_dbg(ccn->dev, "Invalid type 0x%x for node %d!\n",
0779                     type, node_xp);
0780             return -EINVAL;
0781         }
0782         break;
0783     }
0784 
0785     /* Validate event ID vs available for the type */
0786     for (i = 0, valid = 0; i < ARRAY_SIZE(arm_ccn_pmu_events) && !valid;
0787             i++) {
0788         struct arm_ccn_pmu_event *e = &arm_ccn_pmu_events[i];
0789         u32 port = CCN_CONFIG_PORT(event->attr.config);
0790         u32 vc = CCN_CONFIG_VC(event->attr.config);
0791 
0792         if (!arm_ccn_pmu_type_eq(type, e->type))
0793             continue;
0794         if (event_id != e->event)
0795             continue;
0796         if (e->num_ports && port >= e->num_ports) {
0797             dev_dbg(ccn->dev, "Invalid port %d for node/XP %d!\n",
0798                     port, node_xp);
0799             return -EINVAL;
0800         }
0801         if (e->num_vcs && vc >= e->num_vcs) {
0802             dev_dbg(ccn->dev, "Invalid vc %d for node/XP %d!\n",
0803                     vc, node_xp);
0804             return -EINVAL;
0805         }
0806         valid = 1;
0807     }
0808     if (!valid) {
0809         dev_dbg(ccn->dev, "Invalid event 0x%x for node/XP %d!\n",
0810                 event_id, node_xp);
0811         return -EINVAL;
0812     }
0813 
0814     /* Watchpoint-based event for a node is actually set on XP */
0815     if (event_id == CCN_EVENT_WATCHPOINT && type != CCN_TYPE_XP) {
0816         u32 port;
0817 
0818         type = CCN_TYPE_XP;
0819         port = arm_ccn_node_to_xp_port(node_xp);
0820         node_xp = arm_ccn_node_to_xp(node_xp);
0821 
0822         arm_ccn_pmu_config_set(&event->attr.config,
0823                 node_xp, type, port);
0824     }
0825 
0826     /*
0827      * We must NOT create groups containing mixed PMUs, although software
0828      * events are acceptable (for example to create a CCN group
0829      * periodically read when a hrtimer aka cpu-clock leader triggers).
0830      */
0831     if (event->group_leader->pmu != event->pmu &&
0832             !is_software_event(event->group_leader))
0833         return -EINVAL;
0834 
0835     for_each_sibling_event(sibling, event->group_leader) {
0836         if (sibling->pmu != event->pmu &&
0837                 !is_software_event(sibling))
0838             return -EINVAL;
0839     }
0840 
0841     return 0;
0842 }
0843 
0844 static u64 arm_ccn_pmu_read_counter(struct arm_ccn *ccn, int idx)
0845 {
0846     u64 res;
0847 
0848     if (idx == CCN_IDX_PMU_CYCLE_COUNTER) {
0849 #ifdef readq
0850         res = readq(ccn->dt.base + CCN_DT_PMCCNTR);
0851 #else
0852         /* 40 bit counter, can do snapshot and read in two parts */
0853         writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ);
0854         while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1))
0855             ;
0856         writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
0857         res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff;
0858         res <<= 32;
0859         res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR);
0860 #endif
0861     } else {
0862         res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx));
0863     }
0864 
0865     return res;
0866 }
0867 
0868 static void arm_ccn_pmu_event_update(struct perf_event *event)
0869 {
0870     struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
0871     struct hw_perf_event *hw = &event->hw;
0872     u64 prev_count, new_count, mask;
0873 
0874     do {
0875         prev_count = local64_read(&hw->prev_count);
0876         new_count = arm_ccn_pmu_read_counter(ccn, hw->idx);
0877     } while (local64_xchg(&hw->prev_count, new_count) != prev_count);
0878 
0879     mask = (1LLU << (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER ? 40 : 32)) - 1;
0880 
0881     local64_add((new_count - prev_count) & mask, &event->count);
0882 }
0883 
0884 static void arm_ccn_pmu_xp_dt_config(struct perf_event *event, int enable)
0885 {
0886     struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
0887     struct hw_perf_event *hw = &event->hw;
0888     struct arm_ccn_component *xp;
0889     u32 val, dt_cfg;
0890 
0891     /* Nothing to do for cycle counter */
0892     if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
0893         return;
0894 
0895     if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
0896         xp = &ccn->xp[CCN_CONFIG_XP(event->attr.config)];
0897     else
0898         xp = &ccn->xp[arm_ccn_node_to_xp(
0899                 CCN_CONFIG_NODE(event->attr.config))];
0900 
0901     if (enable)
0902         dt_cfg = hw->event_base;
0903     else
0904         dt_cfg = CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH;
0905 
0906     spin_lock(&ccn->dt.config_lock);
0907 
0908     val = readl(xp->base + CCN_XP_DT_CONFIG);
0909     val &= ~(CCN_XP_DT_CONFIG__DT_CFG__MASK <<
0910             CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx));
0911     val |= dt_cfg << CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx);
0912     writel(val, xp->base + CCN_XP_DT_CONFIG);
0913 
0914     spin_unlock(&ccn->dt.config_lock);
0915 }
0916 
0917 static void arm_ccn_pmu_event_start(struct perf_event *event, int flags)
0918 {
0919     struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
0920     struct hw_perf_event *hw = &event->hw;
0921 
0922     local64_set(&event->hw.prev_count,
0923             arm_ccn_pmu_read_counter(ccn, hw->idx));
0924     hw->state = 0;
0925 
0926     /* Set the DT bus input, engaging the counter */
0927     arm_ccn_pmu_xp_dt_config(event, 1);
0928 }
0929 
0930 static void arm_ccn_pmu_event_stop(struct perf_event *event, int flags)
0931 {
0932     struct hw_perf_event *hw = &event->hw;
0933 
0934     /* Disable counting, setting the DT bus to pass-through mode */
0935     arm_ccn_pmu_xp_dt_config(event, 0);
0936 
0937     if (flags & PERF_EF_UPDATE)
0938         arm_ccn_pmu_event_update(event);
0939 
0940     hw->state |= PERF_HES_STOPPED;
0941 }
0942 
0943 static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event)
0944 {
0945     struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
0946     struct hw_perf_event *hw = &event->hw;
0947     struct arm_ccn_component *source =
0948             ccn->dt.pmu_counters[hw->idx].source;
0949     unsigned long wp = hw->config_base;
0950     u32 val;
0951     u64 cmp_l = event->attr.config1;
0952     u64 cmp_h = event->attr.config2;
0953     u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l;
0954     u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h;
0955 
0956     hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp);
0957 
0958     /* Direction (RX/TX), device (port) & virtual channel */
0959     val = readl(source->base + CCN_XP_DT_INTERFACE_SEL);
0960     val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK <<
0961             CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp));
0962     val |= CCN_CONFIG_DIR(event->attr.config) <<
0963             CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp);
0964     val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK <<
0965             CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp));
0966     val |= CCN_CONFIG_PORT(event->attr.config) <<
0967             CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp);
0968     val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK <<
0969             CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp));
0970     val |= CCN_CONFIG_VC(event->attr.config) <<
0971             CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp);
0972     writel(val, source->base + CCN_XP_DT_INTERFACE_SEL);
0973 
0974     /* Comparison values */
0975     writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp));
0976     writel((cmp_l >> 32) & 0x7fffffff,
0977             source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);
0978     writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp));
0979     writel((cmp_h >> 32) & 0x0fffffff,
0980             source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4);
0981 
0982     /* Mask */
0983     writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp));
0984     writel((mask_l >> 32) & 0x7fffffff,
0985             source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);
0986     writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp));
0987     writel((mask_h >> 32) & 0x0fffffff,
0988             source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4);
0989 }
0990 
0991 static void arm_ccn_pmu_xp_event_config(struct perf_event *event)
0992 {
0993     struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
0994     struct hw_perf_event *hw = &event->hw;
0995     struct arm_ccn_component *source =
0996             ccn->dt.pmu_counters[hw->idx].source;
0997     u32 val, id;
0998 
0999     hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base);
1000 
1001     id = (CCN_CONFIG_VC(event->attr.config) << 4) |
1002             (CCN_CONFIG_BUS(event->attr.config) << 3) |
1003             (CCN_CONFIG_EVENT(event->attr.config) << 0);
1004 
1005     val = readl(source->base + CCN_XP_PMU_EVENT_SEL);
1006     val &= ~(CCN_XP_PMU_EVENT_SEL__ID__MASK <<
1007             CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1008     val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1009     writel(val, source->base + CCN_XP_PMU_EVENT_SEL);
1010 }
1011 
1012 static void arm_ccn_pmu_node_event_config(struct perf_event *event)
1013 {
1014     struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1015     struct hw_perf_event *hw = &event->hw;
1016     struct arm_ccn_component *source =
1017             ccn->dt.pmu_counters[hw->idx].source;
1018     u32 type = CCN_CONFIG_TYPE(event->attr.config);
1019     u32 val, port;
1020 
1021     port = arm_ccn_node_to_xp_port(CCN_CONFIG_NODE(event->attr.config));
1022     hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port,
1023             hw->config_base);
1024 
1025     /* These *_event_sel regs should be identical, but let's make sure... */
1026     BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL != CCN_SBAS_PMU_EVENT_SEL);
1027     BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL != CCN_RNI_PMU_EVENT_SEL);
1028     BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(1) !=
1029             CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1));
1030     BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1) !=
1031             CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(1));
1032     BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__MASK !=
1033             CCN_SBAS_PMU_EVENT_SEL__ID__MASK);
1034     BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__MASK !=
1035             CCN_RNI_PMU_EVENT_SEL__ID__MASK);
1036     if (WARN_ON(type != CCN_TYPE_HNF && type != CCN_TYPE_SBAS &&
1037             !arm_ccn_pmu_type_eq(type, CCN_TYPE_RNI_3P)))
1038         return;
1039 
1040     /* Set the event id for the pre-allocated counter */
1041     val = readl(source->base + CCN_HNF_PMU_EVENT_SEL);
1042     val &= ~(CCN_HNF_PMU_EVENT_SEL__ID__MASK <<
1043         CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1044     val |= CCN_CONFIG_EVENT(event->attr.config) <<
1045         CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1046     writel(val, source->base + CCN_HNF_PMU_EVENT_SEL);
1047 }
1048 
1049 static void arm_ccn_pmu_event_config(struct perf_event *event)
1050 {
1051     struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1052     struct hw_perf_event *hw = &event->hw;
1053     u32 xp, offset, val;
1054 
1055     /* Cycle counter requires no setup */
1056     if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
1057         return;
1058 
1059     if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
1060         xp = CCN_CONFIG_XP(event->attr.config);
1061     else
1062         xp = arm_ccn_node_to_xp(CCN_CONFIG_NODE(event->attr.config));
1063 
1064     spin_lock(&ccn->dt.config_lock);
1065 
1066     /* Set the DT bus "distance" register */
1067     offset = (hw->idx / 4) * 4;
1068     val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1069     val &= ~(CCN_DT_ACTIVE_DSM__DSM_ID__MASK <<
1070             CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4));
1071     val |= xp << CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4);
1072     writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1073 
1074     if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) {
1075         if (CCN_CONFIG_EVENT(event->attr.config) ==
1076                 CCN_EVENT_WATCHPOINT)
1077             arm_ccn_pmu_xp_watchpoint_config(event);
1078         else
1079             arm_ccn_pmu_xp_event_config(event);
1080     } else {
1081         arm_ccn_pmu_node_event_config(event);
1082     }
1083 
1084     spin_unlock(&ccn->dt.config_lock);
1085 }
1086 
1087 static int arm_ccn_pmu_active_counters(struct arm_ccn *ccn)
1088 {
1089     return bitmap_weight(ccn->dt.pmu_counters_mask,
1090                  CCN_NUM_PMU_EVENT_COUNTERS + 1);
1091 }
1092 
1093 static int arm_ccn_pmu_event_add(struct perf_event *event, int flags)
1094 {
1095     int err;
1096     struct hw_perf_event *hw = &event->hw;
1097     struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1098 
1099     err = arm_ccn_pmu_event_alloc(event);
1100     if (err)
1101         return err;
1102 
1103     /*
1104      * Pin the timer, so that the overflows are handled by the chosen
1105      * event->cpu (this is the same one as presented in "cpumask"
1106      * attribute).
1107      */
1108     if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 1)
1109         hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),
1110                   HRTIMER_MODE_REL_PINNED);
1111 
1112     arm_ccn_pmu_event_config(event);
1113 
1114     hw->state = PERF_HES_STOPPED;
1115 
1116     if (flags & PERF_EF_START)
1117         arm_ccn_pmu_event_start(event, PERF_EF_UPDATE);
1118 
1119     return 0;
1120 }
1121 
1122 static void arm_ccn_pmu_event_del(struct perf_event *event, int flags)
1123 {
1124     struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1125 
1126     arm_ccn_pmu_event_stop(event, PERF_EF_UPDATE);
1127 
1128     arm_ccn_pmu_event_release(event);
1129 
1130     if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 0)
1131         hrtimer_cancel(&ccn->dt.hrtimer);
1132 }
1133 
1134 static void arm_ccn_pmu_event_read(struct perf_event *event)
1135 {
1136     arm_ccn_pmu_event_update(event);
1137 }
1138 
1139 static void arm_ccn_pmu_enable(struct pmu *pmu)
1140 {
1141     struct arm_ccn *ccn = pmu_to_arm_ccn(pmu);
1142 
1143     u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
1144     val |= CCN_DT_PMCR__PMU_EN;
1145     writel(val, ccn->dt.base + CCN_DT_PMCR);
1146 }
1147 
1148 static void arm_ccn_pmu_disable(struct pmu *pmu)
1149 {
1150     struct arm_ccn *ccn = pmu_to_arm_ccn(pmu);
1151 
1152     u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
1153     val &= ~CCN_DT_PMCR__PMU_EN;
1154     writel(val, ccn->dt.base + CCN_DT_PMCR);
1155 }
1156 
1157 static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt)
1158 {
1159     u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR);
1160     int idx;
1161 
1162     if (!pmovsr)
1163         return IRQ_NONE;
1164 
1165     writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR);
1166 
1167     BUILD_BUG_ON(CCN_IDX_PMU_CYCLE_COUNTER != CCN_NUM_PMU_EVENT_COUNTERS);
1168 
1169     for (idx = 0; idx < CCN_NUM_PMU_EVENT_COUNTERS + 1; idx++) {
1170         struct perf_event *event = dt->pmu_counters[idx].event;
1171         int overflowed = pmovsr & BIT(idx);
1172 
1173         WARN_ON_ONCE(overflowed && !event &&
1174                 idx != CCN_IDX_PMU_CYCLE_COUNTER);
1175 
1176         if (!event || !overflowed)
1177             continue;
1178 
1179         arm_ccn_pmu_event_update(event);
1180     }
1181 
1182     return IRQ_HANDLED;
1183 }
1184 
1185 static enum hrtimer_restart arm_ccn_pmu_timer_handler(struct hrtimer *hrtimer)
1186 {
1187     struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt,
1188             hrtimer);
1189     unsigned long flags;
1190 
1191     local_irq_save(flags);
1192     arm_ccn_pmu_overflow_handler(dt);
1193     local_irq_restore(flags);
1194 
1195     hrtimer_forward_now(hrtimer, arm_ccn_pmu_timer_period());
1196     return HRTIMER_RESTART;
1197 }
1198 
1199 
1200 static int arm_ccn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
1201 {
1202     struct arm_ccn_dt *dt = hlist_entry_safe(node, struct arm_ccn_dt, node);
1203     struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt);
1204     unsigned int target;
1205 
1206     if (cpu != dt->cpu)
1207         return 0;
1208     target = cpumask_any_but(cpu_online_mask, cpu);
1209     if (target >= nr_cpu_ids)
1210         return 0;
1211     perf_pmu_migrate_context(&dt->pmu, cpu, target);
1212     dt->cpu = target;
1213     if (ccn->irq)
1214         WARN_ON(irq_set_affinity(ccn->irq, cpumask_of(dt->cpu)));
1215     return 0;
1216 }
1217 
1218 static DEFINE_IDA(arm_ccn_pmu_ida);
1219 
1220 static int arm_ccn_pmu_init(struct arm_ccn *ccn)
1221 {
1222     int i;
1223     char *name;
1224     int err;
1225 
1226     /* Initialize DT subsystem */
1227     ccn->dt.base = ccn->base + CCN_REGION_SIZE;
1228     spin_lock_init(&ccn->dt.config_lock);
1229     writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR);
1230     writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL);
1231     writel(CCN_DT_PMCR__OVFL_INTR_EN | CCN_DT_PMCR__PMU_EN,
1232             ccn->dt.base + CCN_DT_PMCR);
1233     writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
1234     for (i = 0; i < ccn->num_xps; i++) {
1235         writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG);
1236         writel((CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1237                 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(0)) |
1238                 (CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1239                 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(1)) |
1240                 CCN_XP_DT_CONTROL__DT_ENABLE,
1241                 ccn->xp[i].base + CCN_XP_DT_CONTROL);
1242     }
1243     ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0;
1244     ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0;
1245     ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0;
1246     ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0;
1247     ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0;
1248     ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15);
1249     ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0;
1250     ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9);
1251 
1252     /* Get a convenient /sys/event_source/devices/ name */
1253     ccn->dt.id = ida_alloc(&arm_ccn_pmu_ida, GFP_KERNEL);
1254     if (ccn->dt.id == 0) {
1255         name = "ccn";
1256     } else {
1257         name = devm_kasprintf(ccn->dev, GFP_KERNEL, "ccn_%d",
1258                       ccn->dt.id);
1259         if (!name) {
1260             err = -ENOMEM;
1261             goto error_choose_name;
1262         }
1263     }
1264 
1265     /* Perf driver registration */
1266     ccn->dt.pmu = (struct pmu) {
1267         .module = THIS_MODULE,
1268         .attr_groups = arm_ccn_pmu_attr_groups,
1269         .task_ctx_nr = perf_invalid_context,
1270         .event_init = arm_ccn_pmu_event_init,
1271         .add = arm_ccn_pmu_event_add,
1272         .del = arm_ccn_pmu_event_del,
1273         .start = arm_ccn_pmu_event_start,
1274         .stop = arm_ccn_pmu_event_stop,
1275         .read = arm_ccn_pmu_event_read,
1276         .pmu_enable = arm_ccn_pmu_enable,
1277         .pmu_disable = arm_ccn_pmu_disable,
1278         .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
1279     };
1280 
1281     /* No overflow interrupt? Have to use a timer instead. */
1282     if (!ccn->irq) {
1283         dev_info(ccn->dev, "No access to interrupts, using timer.\n");
1284         hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC,
1285                 HRTIMER_MODE_REL);
1286         ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler;
1287     }
1288 
1289     /* Pick one CPU which we will use to collect data from CCN... */
1290     ccn->dt.cpu = raw_smp_processor_id();
1291 
1292     /* Also make sure that the overflow interrupt is handled by this CPU */
1293     if (ccn->irq) {
1294         err = irq_set_affinity(ccn->irq, cpumask_of(ccn->dt.cpu));
1295         if (err) {
1296             dev_err(ccn->dev, "Failed to set interrupt affinity!\n");
1297             goto error_set_affinity;
1298         }
1299     }
1300 
1301     cpuhp_state_add_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1302                      &ccn->dt.node);
1303 
1304     err = perf_pmu_register(&ccn->dt.pmu, name, -1);
1305     if (err)
1306         goto error_pmu_register;
1307 
1308     return 0;
1309 
1310 error_pmu_register:
1311     cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1312                         &ccn->dt.node);
1313 error_set_affinity:
1314 error_choose_name:
1315     ida_free(&arm_ccn_pmu_ida, ccn->dt.id);
1316     for (i = 0; i < ccn->num_xps; i++)
1317         writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1318     writel(0, ccn->dt.base + CCN_DT_PMCR);
1319     return err;
1320 }
1321 
1322 static void arm_ccn_pmu_cleanup(struct arm_ccn *ccn)
1323 {
1324     int i;
1325 
1326     cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1327                         &ccn->dt.node);
1328     for (i = 0; i < ccn->num_xps; i++)
1329         writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1330     writel(0, ccn->dt.base + CCN_DT_PMCR);
1331     perf_pmu_unregister(&ccn->dt.pmu);
1332     ida_free(&arm_ccn_pmu_ida, ccn->dt.id);
1333 }
1334 
1335 static int arm_ccn_for_each_valid_region(struct arm_ccn *ccn,
1336         int (*callback)(struct arm_ccn *ccn, int region,
1337         void __iomem *base, u32 type, u32 id))
1338 {
1339     int region;
1340 
1341     for (region = 0; region < CCN_NUM_REGIONS; region++) {
1342         u32 val, type, id;
1343         void __iomem *base;
1344         int err;
1345 
1346         val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 +
1347                 4 * (region / 32));
1348         if (!(val & (1 << (region % 32))))
1349             continue;
1350 
1351         base = ccn->base + region * CCN_REGION_SIZE;
1352         val = readl(base + CCN_ALL_OLY_ID);
1353         type = (val >> CCN_ALL_OLY_ID__OLY_ID__SHIFT) &
1354                 CCN_ALL_OLY_ID__OLY_ID__MASK;
1355         id = (val >> CCN_ALL_OLY_ID__NODE_ID__SHIFT) &
1356                 CCN_ALL_OLY_ID__NODE_ID__MASK;
1357 
1358         err = callback(ccn, region, base, type, id);
1359         if (err)
1360             return err;
1361     }
1362 
1363     return 0;
1364 }
1365 
1366 static int arm_ccn_get_nodes_num(struct arm_ccn *ccn, int region,
1367         void __iomem *base, u32 type, u32 id)
1368 {
1369 
1370     if (type == CCN_TYPE_XP && id >= ccn->num_xps)
1371         ccn->num_xps = id + 1;
1372     else if (id >= ccn->num_nodes)
1373         ccn->num_nodes = id + 1;
1374 
1375     return 0;
1376 }
1377 
1378 static int arm_ccn_init_nodes(struct arm_ccn *ccn, int region,
1379         void __iomem *base, u32 type, u32 id)
1380 {
1381     struct arm_ccn_component *component;
1382 
1383     dev_dbg(ccn->dev, "Region %d: id=%u, type=0x%02x\n", region, id, type);
1384 
1385     switch (type) {
1386     case CCN_TYPE_MN:
1387         ccn->mn_id = id;
1388         return 0;
1389     case CCN_TYPE_DT:
1390         return 0;
1391     case CCN_TYPE_XP:
1392         component = &ccn->xp[id];
1393         break;
1394     case CCN_TYPE_SBSX:
1395         ccn->sbsx_present = 1;
1396         component = &ccn->node[id];
1397         break;
1398     case CCN_TYPE_SBAS:
1399         ccn->sbas_present = 1;
1400         fallthrough;
1401     default:
1402         component = &ccn->node[id];
1403         break;
1404     }
1405 
1406     component->base = base;
1407     component->type = type;
1408 
1409     return 0;
1410 }
1411 
1412 
1413 static irqreturn_t arm_ccn_error_handler(struct arm_ccn *ccn,
1414         const u32 *err_sig_val)
1415 {
1416     /* This should be really handled by firmware... */
1417     dev_err(ccn->dev, "Error reported in %08x%08x%08x%08x%08x%08x.\n",
1418             err_sig_val[5], err_sig_val[4], err_sig_val[3],
1419             err_sig_val[2], err_sig_val[1], err_sig_val[0]);
1420     dev_err(ccn->dev, "Disabling interrupt generation for all errors.\n");
1421     writel(CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE,
1422             ccn->base + CCN_MN_ERRINT_STATUS);
1423 
1424     return IRQ_HANDLED;
1425 }
1426 
1427 
1428 static irqreturn_t arm_ccn_irq_handler(int irq, void *dev_id)
1429 {
1430     irqreturn_t res = IRQ_NONE;
1431     struct arm_ccn *ccn = dev_id;
1432     u32 err_sig_val[6];
1433     u32 err_or;
1434     int i;
1435 
1436     /* PMU overflow is a special case */
1437     err_or = err_sig_val[0] = readl(ccn->base + CCN_MN_ERR_SIG_VAL_63_0);
1438     if (err_or & CCN_MN_ERR_SIG_VAL_63_0__DT) {
1439         err_or &= ~CCN_MN_ERR_SIG_VAL_63_0__DT;
1440         res = arm_ccn_pmu_overflow_handler(&ccn->dt);
1441     }
1442 
1443     /* Have to read all err_sig_vals to clear them */
1444     for (i = 1; i < ARRAY_SIZE(err_sig_val); i++) {
1445         err_sig_val[i] = readl(ccn->base +
1446                 CCN_MN_ERR_SIG_VAL_63_0 + i * 4);
1447         err_or |= err_sig_val[i];
1448     }
1449     if (err_or)
1450         res |= arm_ccn_error_handler(ccn, err_sig_val);
1451 
1452     if (res != IRQ_NONE)
1453         writel(CCN_MN_ERRINT_STATUS__INTREQ__DESSERT,
1454                 ccn->base + CCN_MN_ERRINT_STATUS);
1455 
1456     return res;
1457 }
1458 
1459 
1460 static int arm_ccn_probe(struct platform_device *pdev)
1461 {
1462     struct arm_ccn *ccn;
1463     int irq;
1464     int err;
1465 
1466     ccn = devm_kzalloc(&pdev->dev, sizeof(*ccn), GFP_KERNEL);
1467     if (!ccn)
1468         return -ENOMEM;
1469     ccn->dev = &pdev->dev;
1470     platform_set_drvdata(pdev, ccn);
1471 
1472     ccn->base = devm_platform_ioremap_resource(pdev, 0);
1473     if (IS_ERR(ccn->base))
1474         return PTR_ERR(ccn->base);
1475 
1476     irq = platform_get_irq(pdev, 0);
1477     if (irq < 0)
1478         return irq;
1479 
1480     /* Check if we can use the interrupt */
1481     writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE,
1482             ccn->base + CCN_MN_ERRINT_STATUS);
1483     if (readl(ccn->base + CCN_MN_ERRINT_STATUS) &
1484             CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED) {
1485         /* Can set 'disable' bits, so can acknowledge interrupts */
1486         writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE,
1487                 ccn->base + CCN_MN_ERRINT_STATUS);
1488         err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler,
1489                        IRQF_NOBALANCING | IRQF_NO_THREAD,
1490                        dev_name(ccn->dev), ccn);
1491         if (err)
1492             return err;
1493 
1494         ccn->irq = irq;
1495     }
1496 
1497 
1498     /* Build topology */
1499 
1500     err = arm_ccn_for_each_valid_region(ccn, arm_ccn_get_nodes_num);
1501     if (err)
1502         return err;
1503 
1504     ccn->node = devm_kcalloc(ccn->dev, ccn->num_nodes, sizeof(*ccn->node),
1505                  GFP_KERNEL);
1506     ccn->xp = devm_kcalloc(ccn->dev, ccn->num_xps, sizeof(*ccn->node),
1507                    GFP_KERNEL);
1508     if (!ccn->node || !ccn->xp)
1509         return -ENOMEM;
1510 
1511     err = arm_ccn_for_each_valid_region(ccn, arm_ccn_init_nodes);
1512     if (err)
1513         return err;
1514 
1515     return arm_ccn_pmu_init(ccn);
1516 }
1517 
1518 static int arm_ccn_remove(struct platform_device *pdev)
1519 {
1520     struct arm_ccn *ccn = platform_get_drvdata(pdev);
1521 
1522     arm_ccn_pmu_cleanup(ccn);
1523 
1524     return 0;
1525 }
1526 
1527 static const struct of_device_id arm_ccn_match[] = {
1528     { .compatible = "arm,ccn-502", },
1529     { .compatible = "arm,ccn-504", },
1530     { .compatible = "arm,ccn-512", },
1531     {},
1532 };
1533 MODULE_DEVICE_TABLE(of, arm_ccn_match);
1534 
1535 static struct platform_driver arm_ccn_driver = {
1536     .driver = {
1537         .name = "arm-ccn",
1538         .of_match_table = arm_ccn_match,
1539         .suppress_bind_attrs = true,
1540     },
1541     .probe = arm_ccn_probe,
1542     .remove = arm_ccn_remove,
1543 };
1544 
1545 static int __init arm_ccn_init(void)
1546 {
1547     int i, ret;
1548 
1549     ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1550                       "perf/arm/ccn:online", NULL,
1551                       arm_ccn_pmu_offline_cpu);
1552     if (ret)
1553         return ret;
1554 
1555     for (i = 0; i < ARRAY_SIZE(arm_ccn_pmu_events); i++)
1556         arm_ccn_pmu_events_attrs[i] = &arm_ccn_pmu_events[i].attr.attr;
1557 
1558     ret = platform_driver_register(&arm_ccn_driver);
1559     if (ret)
1560         cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE);
1561     return ret;
1562 }
1563 
1564 static void __exit arm_ccn_exit(void)
1565 {
1566     platform_driver_unregister(&arm_ccn_driver);
1567     cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE);
1568 }
1569 
1570 module_init(arm_ccn_init);
1571 module_exit(arm_ccn_exit);
1572 
1573 MODULE_AUTHOR("Pawel Moll <pawel.moll@arm.com>");
1574 MODULE_LICENSE("GPL v2");
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