0001 # SPDX-License-Identifier: GPL-2.0-only
0002 #
0003 # Performance Monitor Drivers
0004 #
0005
0006 menu "Performance monitor support"
0007 depends on PERF_EVENTS
0008
0009 config ARM_CCI_PMU
0010 tristate "ARM CCI PMU driver"
0011 depends on (ARM && CPU_V7) || ARM64
0012 select ARM_CCI
0013 help
0014 Support for PMU events monitoring on the ARM CCI (Cache Coherent
0015 Interconnect) family of products.
0016
0017 If compiled as a module, it will be called arm-cci.
0018
0019 config ARM_CCI400_PMU
0020 bool "support CCI-400"
0021 default y
0022 depends on ARM_CCI_PMU
0023 select ARM_CCI400_COMMON
0024 help
0025 CCI-400 provides 4 independent event counters counting events related
0026 to the connected slave/master interfaces, plus a cycle counter.
0027
0028 config ARM_CCI5xx_PMU
0029 bool "support CCI-500/CCI-550"
0030 default y
0031 depends on ARM_CCI_PMU
0032 help
0033 CCI-500/CCI-550 both provide 8 independent event counters, which can
0034 count events pertaining to the slave/master interfaces as well as the
0035 internal events to the CCI.
0036
0037 config ARM_CCN
0038 tristate "ARM CCN driver support"
0039 depends on ARM || ARM64 || COMPILE_TEST
0040 help
0041 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)
0042 interconnect.
0043
0044 config ARM_CMN
0045 tristate "Arm CMN-600 PMU support"
0046 depends on ARM64 || COMPILE_TEST
0047 help
0048 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
0049 Network interconnect.
0050
0051 config ARM_PMU
0052 depends on ARM || ARM64
0053 bool "ARM PMU framework"
0054 default y
0055 help
0056 Say y if you want to use CPU performance monitors on ARM-based
0057 systems.
0058
0059 config RISCV_PMU
0060 depends on RISCV
0061 bool "RISC-V PMU framework"
0062 default y
0063 help
0064 Say y if you want to use CPU performance monitors on RISCV-based
0065 systems. This provides the core PMU framework that abstracts common
0066 PMU functionalities in a core library so that different PMU drivers
0067 can reuse it.
0068
0069 config RISCV_PMU_LEGACY
0070 depends on RISCV_PMU
0071 bool "RISC-V legacy PMU implementation"
0072 default y
0073 help
0074 Say y if you want to use the legacy CPU performance monitor
0075 implementation on RISC-V based systems. This only allows counting
0076 of cycle/instruction counter and doesn't support counter overflow,
0077 or programmable counters. It will be removed in future.
0078
0079 config RISCV_PMU_SBI
0080 depends on RISCV_PMU && RISCV_SBI
0081 bool "RISC-V PMU based on SBI PMU extension"
0082 default y
0083 help
0084 Say y if you want to use the CPU performance monitor
0085 using SBI PMU extension on RISC-V based systems. This option provides
0086 full perf feature support i.e. counter overflow, privilege mode
0087 filtering, counter configuration.
0088
0089 config ARM_PMU_ACPI
0090 depends on ARM_PMU && ACPI
0091 def_bool y
0092
0093 config ARM_SMMU_V3_PMU
0094 tristate "ARM SMMUv3 Performance Monitors Extension"
0095 depends on (ARM64 && ACPI) || (COMPILE_TEST && 64BIT)
0096 depends on GENERIC_MSI_IRQ_DOMAIN
0097 help
0098 Provides support for the ARM SMMUv3 Performance Monitor Counter
0099 Groups (PMCG), which provide monitoring of transactions passing
0100 through the SMMU and allow the resulting information to be filtered
0101 based on the Stream ID of the corresponding master.
0102
0103 config ARM_DSU_PMU
0104 tristate "ARM DynamIQ Shared Unit (DSU) PMU"
0105 depends on ARM64
0106 help
0107 Provides support for performance monitor unit in ARM DynamIQ Shared
0108 Unit (DSU). The DSU integrates one or more cores with an L3 memory
0109 system, control logic. The PMU allows counting various events related
0110 to DSU.
0111
0112 config FSL_IMX8_DDR_PMU
0113 tristate "Freescale i.MX8 DDR perf monitor"
0114 depends on ARCH_MXC || COMPILE_TEST
0115 help
0116 Provides support for the DDR performance monitor in i.MX8, which
0117 can give information about memory throughput and other related
0118 events.
0119
0120 config QCOM_L2_PMU
0121 bool "Qualcomm Technologies L2-cache PMU"
0122 depends on ARCH_QCOM && ARM64 && ACPI
0123 select QCOM_KRYO_L2_ACCESSORS
0124 help
0125 Provides support for the L2 cache performance monitor unit (PMU)
0126 in Qualcomm Technologies processors.
0127 Adds the L2 cache PMU into the perf events subsystem for
0128 monitoring L2 cache events.
0129
0130 config QCOM_L3_PMU
0131 bool "Qualcomm Technologies L3-cache PMU"
0132 depends on ARCH_QCOM && ARM64 && ACPI
0133 select QCOM_IRQ_COMBINER
0134 help
0135 Provides support for the L3 cache performance monitor unit (PMU)
0136 in Qualcomm Technologies processors.
0137 Adds the L3 cache PMU into the perf events subsystem for
0138 monitoring L3 cache events.
0139
0140 config THUNDERX2_PMU
0141 tristate "Cavium ThunderX2 SoC PMU UNCORE"
0142 depends on ARCH_THUNDER2 || COMPILE_TEST
0143 depends on NUMA && ACPI
0144 default m
0145 help
0146 Provides support for ThunderX2 UNCORE events.
0147 The SoC has PMU support in its L3 cache controller (L3C) and
0148 in the DDR4 Memory Controller (DMC).
0149
0150 config XGENE_PMU
0151 depends on ARCH_XGENE || (COMPILE_TEST && 64BIT)
0152 bool "APM X-Gene SoC PMU"
0153 default n
0154 help
0155 Say y if you want to use APM X-Gene SoC performance monitors.
0156
0157 config ARM_SPE_PMU
0158 tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"
0159 depends on ARM64
0160 help
0161 Enable perf support for the ARMv8.2 Statistical Profiling
0162 Extension, which provides periodic sampling of operations in
0163 the CPU pipeline and reports this via the perf AUX interface.
0164
0165 config ARM_DMC620_PMU
0166 tristate "Enable PMU support for the ARM DMC-620 memory controller"
0167 depends on (ARM64 && ACPI) || COMPILE_TEST
0168 help
0169 Support for PMU events monitoring on the ARM DMC-620 memory
0170 controller.
0171
0172 config MARVELL_CN10K_TAD_PMU
0173 tristate "Marvell CN10K LLC-TAD PMU"
0174 depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT)
0175 help
0176 Provides support for Last-Level cache Tag-and-data Units (LLC-TAD)
0177 performance monitors on CN10K family silicons.
0178
0179 config APPLE_M1_CPU_PMU
0180 bool "Apple M1 CPU PMU support"
0181 depends on ARM_PMU && ARCH_APPLE
0182 help
0183 Provides support for the non-architectural CPU PMUs present on
0184 the Apple M1 SoCs and derivatives.
0185
0186 source "drivers/perf/hisilicon/Kconfig"
0187
0188 config MARVELL_CN10K_DDR_PMU
0189 tristate "Enable MARVELL CN10K DRAM Subsystem(DSS) PMU Support"
0190 depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT)
0191 help
0192 Enable perf support for Marvell DDR Performance monitoring
0193 event on CN10K platform.
0194
0195 endmenu
