drivers/pcmcia/vg468.h

0001 /*
0002  * vg468.h 1.11 1999/10/25 20:03:34
0003  *
0004  * The contents of this file are subject to the Mozilla Public License
0005  * Version 1.1 (the "License"); you may not use this file except in
0006  * compliance with the License. You may obtain a copy of the License
0007  * at http://www.mozilla.org/MPL/
0008  *
0009  * Software distributed under the License is distributed on an "AS IS"
0010  * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
0011  * the License for the specific language governing rights and
0012  * limitations under the License.
0013  *
0014  * The initial developer of the original code is David A. Hinds
0015  * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
0016  * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
0017  *
0018  * Alternatively, the contents of this file may be used under the
0019  * terms of the GNU General Public License version 2 (the "GPL"), in which
0020  * case the provisions of the GPL are applicable instead of the
0021  * above.  If you wish to allow the use of your version of this file
0022  * only under the terms of the GPL and not to allow others to use
0023  * your version of this file under the MPL, indicate your decision by
0024  * deleting the provisions above and replace them with the notice and
0025  * other provisions required by the GPL.  If you do not delete the
0026  * provisions above, a recipient may use your version of this file
0027  * under either the MPL or the GPL.
0028  */
0029
0030 #ifndef _LINUX_VG468_H
0031 #define _LINUX_VG468_H
0032
0033 /* Special bit in I365_IDENT used for Vadem chip detection */
0034 #define I365_IDENT_VADEM    0x08
0035
0036 /* Special definitions in I365_POWER */
0037 #define VG468_VPP2_MASK     0x0c
0038 #define VG468_VPP2_5V       0x04
0039 #define VG468_VPP2_12V      0x08
0040
0041 /* Unique Vadem registers */
0042 #define VG469_VSENSE        0x1f    /* Card voltage sense */
0043 #define VG469_VSELECT       0x2f    /* Card voltage select */
0044 #define VG468_CTL       0x38    /* Control register */
0045 #define VG468_TIMER     0x39    /* Timer control */
0046 #define VG468_MISC      0x3a    /* Miscellaneous */
0047 #define VG468_GPIO_CFG      0x3b    /* GPIO configuration */
0048 #define VG469_EXT_MODE      0x3c    /* Extended mode register */
0049 #define VG468_SELECT        0x3d    /* Programmable chip select */
0050 #define VG468_SELECT_CFG    0x3e    /* Chip select configuration */
0051 #define VG468_ATA       0x3f    /* ATA control */
0052
0053 /* Flags for VG469_VSENSE */
0054 #define VG469_VSENSE_A_VS1  0x01
0055 #define VG469_VSENSE_A_VS2  0x02
0056 #define VG469_VSENSE_B_VS1  0x04
0057 #define VG469_VSENSE_B_VS2  0x08
0058
0059 /* Flags for VG469_VSELECT */
0060 #define VG469_VSEL_VCC      0x03
0061 #define VG469_VSEL_5V       0x00
0062 #define VG469_VSEL_3V       0x03
0063 #define VG469_VSEL_MAX      0x0c
0064 #define VG469_VSEL_EXT_STAT 0x10
0065 #define VG469_VSEL_EXT_BUS  0x20
0066 #define VG469_VSEL_MIXED    0x40
0067 #define VG469_VSEL_ISA      0x80
0068
0069 /* Flags for VG468_CTL */
0070 #define VG468_CTL_SLOW      0x01    /* 600ns memory timing */
0071 #define VG468_CTL_ASYNC     0x02    /* Asynchronous bus clocking */
0072 #define VG468_CTL_TSSI      0x08    /* Tri-state some outputs */
0073 #define VG468_CTL_DELAY     0x10    /* Card detect debounce */
0074 #define VG468_CTL_INPACK    0x20    /* Obey INPACK signal? */
0075 #define VG468_CTL_POLARITY  0x40    /* VCCEN polarity */
0076 #define VG468_CTL_COMPAT    0x80    /* Compatibility stuff */
0077
0078 #define VG469_CTL_WS_COMPAT 0x04    /* Wait state compatibility */
0079 #define VG469_CTL_STRETCH   0x10    /* LED stretch */
0080
0081 /* Flags for VG468_TIMER */
0082 #define VG468_TIMER_ZEROPWR 0x10    /* Zero power control */
0083 #define VG468_TIMER_SIGEN   0x20    /* Power up */
0084 #define VG468_TIMER_STATUS  0x40    /* Activity timer status */
0085 #define VG468_TIMER_RES     0x80    /* Timer resolution */
0086 #define VG468_TIMER_MASK    0x0f    /* Activity timer timeout */
0087
0088 /* Flags for VG468_MISC */
0089 #define VG468_MISC_GPIO     0x04    /* General-purpose IO */
0090 #define VG468_MISC_DMAWSB   0x08    /* DMA wait state control */
0091 #define VG469_MISC_LEDENA   0x10    /* LED enable */
0092 #define VG468_MISC_VADEMREV 0x40    /* Vadem revision control */
0093 #define VG468_MISC_UNLOCK   0x80    /* Unique register lock */
0094
0095 /* Flags for VG469_EXT_MODE_A */
0096 #define VG469_MODE_VPPST    0x03    /* Vpp steering control */
0097 #define VG469_MODE_INT_SENSE    0x04    /* Internal voltage sense */
0098 #define VG469_MODE_CABLE    0x08
0099 #define VG469_MODE_COMPAT   0x10    /* i82365sl B or DF step */
0100 #define VG469_MODE_TEST     0x20
0101 #define VG469_MODE_RIO      0x40    /* Steer RIO to INTR? */
0102
0103 /* Flags for VG469_EXT_MODE_B */
0104 #define VG469_MODE_B_3V     0x01    /* 3.3v for socket B */
0105
0106 #endif /* _LINUX_VG468_H */