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0001 /*
0002  * ti113x.h 1.16 1999/10/25 20:03:34
0003  *
0004  * The contents of this file are subject to the Mozilla Public License
0005  * Version 1.1 (the "License"); you may not use this file except in
0006  * compliance with the License. You may obtain a copy of the License
0007  * at http://www.mozilla.org/MPL/
0008  *
0009  * Software distributed under the License is distributed on an "AS IS"
0010  * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
0011  * the License for the specific language governing rights and
0012  * limitations under the License. 
0013  *
0014  * The initial developer of the original code is David A. Hinds
0015  * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
0016  * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
0017  *
0018  * Alternatively, the contents of this file may be used under the
0019  * terms of the GNU General Public License version 2 (the "GPL"), in which
0020  * case the provisions of the GPL are applicable instead of the
0021  * above.  If you wish to allow the use of your version of this file
0022  * only under the terms of the GPL and not to allow others to use
0023  * your version of this file under the MPL, indicate your decision by
0024  * deleting the provisions above and replace them with the notice and
0025  * other provisions required by the GPL.  If you do not delete the
0026  * provisions above, a recipient may use your version of this file
0027  * under either the MPL or the GPL.
0028  */
0029 
0030 #ifndef _LINUX_TI113X_H
0031 #define _LINUX_TI113X_H
0032 
0033 
0034 /* Register definitions for TI 113X PCI-to-CardBus bridges */
0035 
0036 /* System Control Register */
0037 #define TI113X_SYSTEM_CONTROL       0x0080  /* 32 bit */
0038 #define  TI113X_SCR_SMIROUTE        0x04000000
0039 #define  TI113X_SCR_SMISTATUS       0x02000000
0040 #define  TI113X_SCR_SMIENB      0x01000000
0041 #define  TI113X_SCR_VCCPROT     0x00200000
0042 #define  TI113X_SCR_REDUCEZV        0x00100000
0043 #define  TI113X_SCR_CDREQEN     0x00080000
0044 #define  TI113X_SCR_CDMACHAN        0x00070000
0045 #define  TI113X_SCR_SOCACTIVE       0x00002000
0046 #define  TI113X_SCR_PWRSTREAM       0x00000800
0047 #define  TI113X_SCR_DELAYUP     0x00000400
0048 #define  TI113X_SCR_DELAYDOWN       0x00000200
0049 #define  TI113X_SCR_INTERROGATE     0x00000100
0050 #define  TI113X_SCR_CLKRUN_SEL      0x00000080
0051 #define  TI113X_SCR_PWRSAVINGS      0x00000040
0052 #define  TI113X_SCR_SUBSYSRW        0x00000020
0053 #define  TI113X_SCR_CB_DPAR     0x00000010
0054 #define  TI113X_SCR_CDMA_EN     0x00000008
0055 #define  TI113X_SCR_ASYNC_IRQ       0x00000004
0056 #define  TI113X_SCR_KEEPCLK     0x00000002
0057 #define  TI113X_SCR_CLKRUN_ENA      0x00000001  
0058 
0059 #define  TI122X_SCR_SER_STEP        0xc0000000
0060 #define  TI122X_SCR_INTRTIE     0x20000000
0061 #define  TIXX21_SCR_TIEALL      0x10000000
0062 #define  TI122X_SCR_CBRSVD      0x00400000
0063 #define  TI122X_SCR_MRBURSTDN       0x00008000
0064 #define  TI122X_SCR_MRBURSTUP       0x00004000
0065 #define  TI122X_SCR_RIMUX       0x00000001
0066 
0067 /* Multimedia Control Register */
0068 #define TI1250_MULTIMEDIA_CTL       0x0084  /* 8 bit */
0069 #define  TI1250_MMC_ZVOUTEN     0x80
0070 #define  TI1250_MMC_PORTSEL     0x40
0071 #define  TI1250_MMC_ZVEN1       0x02
0072 #define  TI1250_MMC_ZVEN0       0x01
0073 
0074 #define TI1250_GENERAL_STATUS       0x0085  /* 8 bit */
0075 #define TI1250_GPIO0_CONTROL        0x0088  /* 8 bit */
0076 #define TI1250_GPIO1_CONTROL        0x0089  /* 8 bit */
0077 #define TI1250_GPIO2_CONTROL        0x008a  /* 8 bit */
0078 #define TI1250_GPIO3_CONTROL        0x008b  /* 8 bit */
0079 #define TI1250_GPIO_MODE_MASK       0xc0
0080 
0081 /* IRQMUX/MFUNC Register */
0082 #define TI122X_MFUNC            0x008c  /* 32 bit */
0083 #define TI122X_MFUNC0_MASK      0x0000000f
0084 #define TI122X_MFUNC1_MASK      0x000000f0
0085 #define TI122X_MFUNC2_MASK      0x00000f00
0086 #define TI122X_MFUNC3_MASK      0x0000f000
0087 #define TI122X_MFUNC4_MASK      0x000f0000
0088 #define TI122X_MFUNC5_MASK      0x00f00000
0089 #define TI122X_MFUNC6_MASK      0x0f000000
0090 
0091 #define TI122X_MFUNC0_INTA      0x00000002
0092 #define TI125X_MFUNC0_INTB      0x00000001
0093 #define TI122X_MFUNC1_INTB      0x00000020
0094 #define TI122X_MFUNC3_IRQSER        0x00001000
0095 
0096 
0097 /* Retry Status Register */
0098 #define TI113X_RETRY_STATUS     0x0090  /* 8 bit */
0099 #define  TI113X_RSR_PCIRETRY        0x80
0100 #define  TI113X_RSR_CBRETRY     0x40
0101 #define  TI113X_RSR_TEXP_CBB        0x20
0102 #define  TI113X_RSR_MEXP_CBB        0x10
0103 #define  TI113X_RSR_TEXP_CBA        0x08
0104 #define  TI113X_RSR_MEXP_CBA        0x04
0105 #define  TI113X_RSR_TEXP_PCI        0x02
0106 #define  TI113X_RSR_MEXP_PCI        0x01
0107 
0108 /* Card Control Register */
0109 #define TI113X_CARD_CONTROL     0x0091  /* 8 bit */
0110 #define  TI113X_CCR_RIENB       0x80
0111 #define  TI113X_CCR_ZVENABLE        0x40
0112 #define  TI113X_CCR_PCI_IRQ_ENA     0x20
0113 #define  TI113X_CCR_PCI_IREQ        0x10
0114 #define  TI113X_CCR_PCI_CSC     0x08
0115 #define  TI113X_CCR_SPKROUTEN       0x02
0116 #define  TI113X_CCR_IFG         0x01
0117 
0118 #define  TI1220_CCR_PORT_SEL        0x20
0119 #define  TI122X_CCR_AUD2MUX     0x04
0120 
0121 /* Device Control Register */
0122 #define TI113X_DEVICE_CONTROL       0x0092  /* 8 bit */
0123 #define  TI113X_DCR_5V_FORCE        0x40
0124 #define  TI113X_DCR_3V_FORCE        0x20
0125 #define  TI113X_DCR_IMODE_MASK      0x06
0126 #define  TI113X_DCR_IMODE_ISA       0x02
0127 #define  TI113X_DCR_IMODE_SERIAL    0x04
0128 
0129 #define  TI12XX_DCR_IMODE_PCI_ONLY  0x00
0130 #define  TI12XX_DCR_IMODE_ALL_SERIAL    0x06
0131 
0132 /* Buffer Control Register */
0133 #define TI113X_BUFFER_CONTROL       0x0093  /* 8 bit */
0134 #define  TI113X_BCR_CB_READ_DEPTH   0x08
0135 #define  TI113X_BCR_CB_WRITE_DEPTH  0x04
0136 #define  TI113X_BCR_PCI_READ_DEPTH  0x02
0137 #define  TI113X_BCR_PCI_WRITE_DEPTH 0x01
0138 
0139 /* Diagnostic Register */
0140 #define TI1250_DIAGNOSTIC       0x0093  /* 8 bit */
0141 #define  TI1250_DIAG_TRUE_VALUE     0x80
0142 #define  TI1250_DIAG_PCI_IREQ       0x40
0143 #define  TI1250_DIAG_PCI_CSC        0x20
0144 #define  TI1250_DIAG_ASYNC_CSC      0x01
0145 
0146 /* DMA Registers */
0147 #define TI113X_DMA_0            0x0094  /* 32 bit */
0148 #define TI113X_DMA_1            0x0098  /* 32 bit */
0149 
0150 /* ExCA IO offset registers */
0151 #define TI113X_IO_OFFSET(map)       (0x36+((map)<<1))
0152 
0153 /* EnE test register */
0154 #define ENE_TEST_C9         0xc9    /* 8bit */
0155 #define ENE_TEST_C9_TLTENABLE       0x02
0156 #define ENE_TEST_C9_PFENABLE_F0     0x04
0157 #define ENE_TEST_C9_PFENABLE_F1     0x08
0158 #define ENE_TEST_C9_PFENABLE        (ENE_TEST_C9_PFENABLE_F0 | ENE_TEST_C9_PFENABLE_F1)
0159 #define ENE_TEST_C9_WPDISALBLE_F0   0x40
0160 #define ENE_TEST_C9_WPDISALBLE_F1   0x80
0161 #define ENE_TEST_C9_WPDISALBLE      (ENE_TEST_C9_WPDISALBLE_F0 | ENE_TEST_C9_WPDISALBLE_F1)
0162 
0163 /*
0164  * Texas Instruments CardBus controller overrides.
0165  */
0166 #define ti_sysctl(socket)   ((socket)->private[0])
0167 #define ti_cardctl(socket)  ((socket)->private[1])
0168 #define ti_devctl(socket)   ((socket)->private[2])
0169 #define ti_diag(socket)     ((socket)->private[3])
0170 #define ti_mfunc(socket)    ((socket)->private[4])
0171 #define ene_test_c9(socket) ((socket)->private[5])
0172 
0173 /*
0174  * These are the TI specific power management handlers.
0175  */
0176 static void ti_save_state(struct yenta_socket *socket)
0177 {
0178     ti_sysctl(socket) = config_readl(socket, TI113X_SYSTEM_CONTROL);
0179     ti_mfunc(socket) = config_readl(socket, TI122X_MFUNC);
0180     ti_cardctl(socket) = config_readb(socket, TI113X_CARD_CONTROL);
0181     ti_devctl(socket) = config_readb(socket, TI113X_DEVICE_CONTROL);
0182     ti_diag(socket) = config_readb(socket, TI1250_DIAGNOSTIC);
0183 
0184     if (socket->dev->vendor == PCI_VENDOR_ID_ENE)
0185         ene_test_c9(socket) = config_readb(socket, ENE_TEST_C9);
0186 }
0187 
0188 static void ti_restore_state(struct yenta_socket *socket)
0189 {
0190     config_writel(socket, TI113X_SYSTEM_CONTROL, ti_sysctl(socket));
0191     config_writel(socket, TI122X_MFUNC, ti_mfunc(socket));
0192     config_writeb(socket, TI113X_CARD_CONTROL, ti_cardctl(socket));
0193     config_writeb(socket, TI113X_DEVICE_CONTROL, ti_devctl(socket));
0194     config_writeb(socket, TI1250_DIAGNOSTIC, ti_diag(socket));
0195 
0196     if (socket->dev->vendor == PCI_VENDOR_ID_ENE)
0197         config_writeb(socket, ENE_TEST_C9, ene_test_c9(socket));
0198 }
0199 
0200 /*
0201  *  Zoom video control for TI122x/113x chips
0202  */
0203 
0204 static void ti_zoom_video(struct pcmcia_socket *sock, int onoff)
0205 {
0206     u8 reg;
0207     struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
0208 
0209     /* If we don't have a Zoom Video switch this is harmless,
0210        we just tristate the unused (ZV) lines */
0211     reg = config_readb(socket, TI113X_CARD_CONTROL);
0212     if (onoff)
0213         /* Zoom zoom, we will all go together, zoom zoom, zoom zoom */
0214         reg |= TI113X_CCR_ZVENABLE;
0215     else
0216         reg &= ~TI113X_CCR_ZVENABLE;
0217     config_writeb(socket, TI113X_CARD_CONTROL, reg);
0218 }
0219 
0220 /*
0221  *  The 145x series can also use this. They have an additional
0222  *  ZV autodetect mode we don't use but don't actually need.
0223  *  FIXME: manual says its in func0 and func1 but disagrees with
0224  *  itself about this - do we need to force func0, if so we need
0225  *  to know a lot more about socket pairings in pcmcia_socket than
0226  *  we do now.. uggh.
0227  */
0228  
0229 static void ti1250_zoom_video(struct pcmcia_socket *sock, int onoff)
0230 {   
0231     struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
0232     int shift = 0;
0233     u8 reg;
0234 
0235     ti_zoom_video(sock, onoff);
0236 
0237     reg = config_readb(socket, TI1250_MULTIMEDIA_CTL);
0238     reg |= TI1250_MMC_ZVOUTEN;  /* ZV bus enable */
0239 
0240     if(PCI_FUNC(socket->dev->devfn)==1)
0241         shift = 1;
0242     
0243     if(onoff)
0244     {
0245         reg &= ~(1<<6);     /* Clear select bit */
0246         reg |= shift<<6;    /* Favour our socket */
0247         reg |= 1<<shift;    /* Socket zoom video on */
0248     }
0249     else
0250     {
0251         reg &= ~(1<<6);     /* Clear select bit */
0252         reg |= (1^shift)<<6;    /* Favour other socket */
0253         reg &= ~(1<<shift); /* Socket zoon video off */
0254     }
0255 
0256     config_writeb(socket, TI1250_MULTIMEDIA_CTL, reg);
0257 }
0258 
0259 static void ti_set_zv(struct yenta_socket *socket)
0260 {
0261     if(socket->dev->vendor == PCI_VENDOR_ID_TI)
0262     {
0263         switch(socket->dev->device)
0264         {
0265             /* There may be more .. */
0266             case PCI_DEVICE_ID_TI_1220:
0267             case PCI_DEVICE_ID_TI_1221:
0268             case PCI_DEVICE_ID_TI_1225:
0269             case PCI_DEVICE_ID_TI_4510:
0270                 socket->socket.zoom_video = ti_zoom_video;
0271                 break;  
0272             case PCI_DEVICE_ID_TI_1250:
0273             case PCI_DEVICE_ID_TI_1251A:
0274             case PCI_DEVICE_ID_TI_1251B:
0275             case PCI_DEVICE_ID_TI_1450:
0276                 socket->socket.zoom_video = ti1250_zoom_video;
0277         }
0278     }
0279 }
0280 
0281 
0282 /*
0283  * Generic TI init - TI has an extension for the
0284  * INTCTL register that sets the PCI CSC interrupt.
0285  * Make sure we set it correctly at open and init
0286  * time
0287  * - override: disable the PCI CSC interrupt. This makes
0288  *   it possible to use the CSC interrupt to probe the
0289  *   ISA interrupts.
0290  * - init: set the interrupt to match our PCI state.
0291  *   This makes us correctly get PCI CSC interrupt
0292  *   events.
0293  */
0294 static int ti_init(struct yenta_socket *socket)
0295 {
0296     u8 new, reg = exca_readb(socket, I365_INTCTL);
0297 
0298     new = reg & ~I365_INTR_ENA;
0299     if (socket->dev->irq)
0300         new |= I365_INTR_ENA;
0301     if (new != reg)
0302         exca_writeb(socket, I365_INTCTL, new);
0303     return 0;
0304 }
0305 
0306 static int ti_override(struct yenta_socket *socket)
0307 {
0308     u8 new, reg = exca_readb(socket, I365_INTCTL);
0309 
0310     new = reg & ~I365_INTR_ENA;
0311     if (new != reg)
0312         exca_writeb(socket, I365_INTCTL, new);
0313 
0314     ti_set_zv(socket);
0315 
0316     return 0;
0317 }
0318 
0319 static void ti113x_use_isa_irq(struct yenta_socket *socket)
0320 {
0321     int isa_irq = -1;
0322     u8 intctl;
0323     u32 isa_irq_mask = 0;
0324 
0325     if (!isa_probe)
0326         return;
0327 
0328     /* get a free isa int */
0329     isa_irq_mask = yenta_probe_irq(socket, isa_interrupts);
0330     if (!isa_irq_mask)
0331         return; /* no useable isa irq found */
0332 
0333     /* choose highest available */
0334     for (; isa_irq_mask; isa_irq++)
0335         isa_irq_mask >>= 1;
0336     socket->cb_irq = isa_irq;
0337 
0338     exca_writeb(socket, I365_CSCINT, (isa_irq << 4));
0339 
0340     intctl = exca_readb(socket, I365_INTCTL);
0341     intctl &= ~(I365_INTR_ENA | I365_IRQ_MASK);     /* CSC Enable */
0342     exca_writeb(socket, I365_INTCTL, intctl);
0343 
0344     dev_info(&socket->dev->dev,
0345         "Yenta TI113x: using isa irq %d for CardBus\n", isa_irq);
0346 }
0347 
0348 
0349 static int ti113x_override(struct yenta_socket *socket)
0350 {
0351     u8 cardctl;
0352 
0353     cardctl = config_readb(socket, TI113X_CARD_CONTROL);
0354     cardctl &= ~(TI113X_CCR_PCI_IRQ_ENA | TI113X_CCR_PCI_IREQ | TI113X_CCR_PCI_CSC);
0355     if (socket->dev->irq)
0356         cardctl |= TI113X_CCR_PCI_IRQ_ENA | TI113X_CCR_PCI_CSC | TI113X_CCR_PCI_IREQ;
0357     else
0358         ti113x_use_isa_irq(socket);
0359 
0360     config_writeb(socket, TI113X_CARD_CONTROL, cardctl);
0361 
0362     return ti_override(socket);
0363 }
0364 
0365 
0366 /* irqrouting for func0, probes PCI interrupt and ISA interrupts */
0367 static void ti12xx_irqroute_func0(struct yenta_socket *socket)
0368 {
0369     u32 mfunc, mfunc_old, devctl;
0370     u8 gpio3, gpio3_old;
0371     int pci_irq_status;
0372 
0373     mfunc = mfunc_old = config_readl(socket, TI122X_MFUNC);
0374     devctl = config_readb(socket, TI113X_DEVICE_CONTROL);
0375     dev_info(&socket->dev->dev, "TI: mfunc 0x%08x, devctl 0x%02x\n",
0376          mfunc, devctl);
0377 
0378     /* make sure PCI interrupts are enabled before probing */
0379     ti_init(socket);
0380 
0381     /* test PCI interrupts first. only try fixing if return value is 0! */
0382     pci_irq_status = yenta_probe_cb_irq(socket);
0383     if (pci_irq_status)
0384         goto out;
0385 
0386     /*
0387      * We're here which means PCI interrupts are _not_ delivered. try to
0388      * find the right setting (all serial or parallel)
0389      */
0390     dev_info(&socket->dev->dev,
0391          "TI: probing PCI interrupt failed, trying to fix\n");
0392 
0393     /* for serial PCI make sure MFUNC3 is set to IRQSER */
0394     if ((devctl & TI113X_DCR_IMODE_MASK) == TI12XX_DCR_IMODE_ALL_SERIAL) {
0395         switch (socket->dev->device) {
0396         case PCI_DEVICE_ID_TI_1250:
0397         case PCI_DEVICE_ID_TI_1251A:
0398         case PCI_DEVICE_ID_TI_1251B:
0399         case PCI_DEVICE_ID_TI_1450:
0400         case PCI_DEVICE_ID_TI_1451A:
0401         case PCI_DEVICE_ID_TI_4450:
0402         case PCI_DEVICE_ID_TI_4451:
0403             /* these chips have no IRQSER setting in MFUNC3  */
0404             break;
0405 
0406         default:
0407             mfunc = (mfunc & ~TI122X_MFUNC3_MASK) | TI122X_MFUNC3_IRQSER;
0408 
0409             /* write down if changed, probe */
0410             if (mfunc != mfunc_old) {
0411                 config_writel(socket, TI122X_MFUNC, mfunc);
0412 
0413                 pci_irq_status = yenta_probe_cb_irq(socket);
0414                 if (pci_irq_status == 1) {
0415                     dev_info(&socket->dev->dev,
0416                          "TI: all-serial interrupts ok\n");
0417                     mfunc_old = mfunc;
0418                     goto out;
0419                 }
0420 
0421                 /* not working, back to old value */
0422                 mfunc = mfunc_old;
0423                 config_writel(socket, TI122X_MFUNC, mfunc);
0424 
0425                 if (pci_irq_status == -1)
0426                     goto out;
0427             }
0428         }
0429 
0430         /* serial PCI interrupts not working fall back to parallel */
0431         dev_info(&socket->dev->dev,
0432              "TI: falling back to parallel PCI interrupts\n");
0433         devctl &= ~TI113X_DCR_IMODE_MASK;
0434         devctl |= TI113X_DCR_IMODE_SERIAL; /* serial ISA could be right */
0435         config_writeb(socket, TI113X_DEVICE_CONTROL, devctl);
0436     }
0437 
0438     /* parallel PCI interrupts: route INTA */
0439     switch (socket->dev->device) {
0440     case PCI_DEVICE_ID_TI_1250:
0441     case PCI_DEVICE_ID_TI_1251A:
0442     case PCI_DEVICE_ID_TI_1251B:
0443     case PCI_DEVICE_ID_TI_1450:
0444         /* make sure GPIO3 is set to INTA */
0445         gpio3 = gpio3_old = config_readb(socket, TI1250_GPIO3_CONTROL);
0446         gpio3 &= ~TI1250_GPIO_MODE_MASK;
0447         if (gpio3 != gpio3_old)
0448             config_writeb(socket, TI1250_GPIO3_CONTROL, gpio3);
0449         break;
0450 
0451     default:
0452         gpio3 = gpio3_old = 0;
0453 
0454         mfunc = (mfunc & ~TI122X_MFUNC0_MASK) | TI122X_MFUNC0_INTA;
0455         if (mfunc != mfunc_old)
0456             config_writel(socket, TI122X_MFUNC, mfunc);
0457     }
0458 
0459     /* time to probe again */
0460     pci_irq_status = yenta_probe_cb_irq(socket);
0461     if (pci_irq_status == 1) {
0462         mfunc_old = mfunc;
0463         dev_info(&socket->dev->dev, "TI: parallel PCI interrupts ok\n");
0464     } else {
0465         /* not working, back to old value */
0466         mfunc = mfunc_old;
0467         config_writel(socket, TI122X_MFUNC, mfunc);
0468         if (gpio3 != gpio3_old)
0469             config_writeb(socket, TI1250_GPIO3_CONTROL, gpio3_old);
0470     }
0471 
0472 out:
0473     if (pci_irq_status < 1) {
0474         socket->cb_irq = 0;
0475         dev_info(&socket->dev->dev,
0476              "Yenta TI: no PCI interrupts. Fish. Please report.\n");
0477     }
0478 }
0479 
0480 
0481 /* changes the irq of func1 to match that of func0 */
0482 static int ti12xx_align_irqs(struct yenta_socket *socket, int *old_irq)
0483 {
0484     struct pci_dev *func0;
0485 
0486     /* find func0 device */
0487     func0 = pci_get_slot(socket->dev->bus, socket->dev->devfn & ~0x07);
0488     if (!func0)
0489         return 0;
0490 
0491     if (old_irq)
0492         *old_irq = socket->cb_irq;
0493     socket->cb_irq = socket->dev->irq = func0->irq;
0494 
0495     pci_dev_put(func0);
0496 
0497     return 1;
0498 }
0499 
0500 /*
0501  * ties INTA and INTB together. also changes the devices irq to that of
0502  * the function 0 device. call from func1 only.
0503  * returns 1 if INTRTIE changed, 0 otherwise.
0504  */
0505 static int ti12xx_tie_interrupts(struct yenta_socket *socket, int *old_irq)
0506 {
0507     u32 sysctl;
0508     int ret;
0509 
0510     sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL);
0511     if (sysctl & TI122X_SCR_INTRTIE)
0512         return 0;
0513 
0514     /* align */
0515     ret = ti12xx_align_irqs(socket, old_irq);
0516     if (!ret)
0517         return 0;
0518 
0519     /* tie */
0520     sysctl |= TI122X_SCR_INTRTIE;
0521     config_writel(socket, TI113X_SYSTEM_CONTROL, sysctl);
0522 
0523     return 1;
0524 }
0525 
0526 /* undo what ti12xx_tie_interrupts() did */
0527 static void ti12xx_untie_interrupts(struct yenta_socket *socket, int old_irq)
0528 {
0529     u32 sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL);
0530     sysctl &= ~TI122X_SCR_INTRTIE;
0531     config_writel(socket, TI113X_SYSTEM_CONTROL, sysctl);
0532 
0533     socket->cb_irq = socket->dev->irq = old_irq;
0534 }
0535 
0536 /* 
0537  * irqrouting for func1, plays with INTB routing
0538  * only touches MFUNC for INTB routing. all other bits are taken
0539  * care of in func0 already.
0540  */
0541 static void ti12xx_irqroute_func1(struct yenta_socket *socket)
0542 {
0543     u32 mfunc, mfunc_old, devctl, sysctl;
0544     int pci_irq_status;
0545 
0546     mfunc = mfunc_old = config_readl(socket, TI122X_MFUNC);
0547     devctl = config_readb(socket, TI113X_DEVICE_CONTROL);
0548     dev_info(&socket->dev->dev, "TI: mfunc 0x%08x, devctl 0x%02x\n",
0549          mfunc, devctl);
0550 
0551     /* if IRQs are configured as tied, align irq of func1 with func0 */
0552     sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL);
0553     if (sysctl & TI122X_SCR_INTRTIE)
0554         ti12xx_align_irqs(socket, NULL);
0555 
0556     /* make sure PCI interrupts are enabled before probing */
0557     ti_init(socket);
0558 
0559     /* test PCI interrupts first. only try fixing if return value is 0! */
0560     pci_irq_status = yenta_probe_cb_irq(socket);
0561     if (pci_irq_status)
0562         goto out;
0563 
0564     /*
0565      * We're here which means PCI interrupts are _not_ delivered. try to
0566      * find the right setting
0567      */
0568     dev_info(&socket->dev->dev,
0569          "TI: probing PCI interrupt failed, trying to fix\n");
0570 
0571     /* if all serial: set INTRTIE, probe again */
0572     if ((devctl & TI113X_DCR_IMODE_MASK) == TI12XX_DCR_IMODE_ALL_SERIAL) {
0573         int old_irq;
0574 
0575         if (ti12xx_tie_interrupts(socket, &old_irq)) {
0576             pci_irq_status = yenta_probe_cb_irq(socket);
0577             if (pci_irq_status == 1) {
0578                 dev_info(&socket->dev->dev,
0579                      "TI: all-serial interrupts, tied ok\n");
0580                 goto out;
0581             }
0582 
0583             ti12xx_untie_interrupts(socket, old_irq);
0584         }
0585     }
0586     /* parallel PCI: route INTB, probe again */
0587     else {
0588         int old_irq;
0589 
0590         switch (socket->dev->device) {
0591         case PCI_DEVICE_ID_TI_1250:
0592             /* the 1250 has one pin for IRQSER/INTB depending on devctl */
0593             break;
0594 
0595         case PCI_DEVICE_ID_TI_1251A:
0596         case PCI_DEVICE_ID_TI_1251B:
0597         case PCI_DEVICE_ID_TI_1450:
0598             /*
0599              *  those have a pin for IRQSER/INTB plus INTB in MFUNC0
0600              *  we alread probed the shared pin, now go for MFUNC0
0601              */
0602             mfunc = (mfunc & ~TI122X_MFUNC0_MASK) | TI125X_MFUNC0_INTB;
0603             break;
0604 
0605         default:
0606             mfunc = (mfunc & ~TI122X_MFUNC1_MASK) | TI122X_MFUNC1_INTB;
0607             break;
0608         }
0609 
0610         /* write, probe */
0611         if (mfunc != mfunc_old) {
0612             config_writel(socket, TI122X_MFUNC, mfunc);
0613 
0614             pci_irq_status = yenta_probe_cb_irq(socket);
0615             if (pci_irq_status == 1) {
0616                 dev_info(&socket->dev->dev,
0617                      "TI: parallel PCI interrupts ok\n");
0618                 goto out;
0619             }
0620 
0621             mfunc = mfunc_old;
0622             config_writel(socket, TI122X_MFUNC, mfunc);
0623 
0624             if (pci_irq_status == -1)
0625                 goto out;
0626         }
0627 
0628         /* still nothing: set INTRTIE */
0629         if (ti12xx_tie_interrupts(socket, &old_irq)) {
0630             pci_irq_status = yenta_probe_cb_irq(socket);
0631             if (pci_irq_status == 1) {
0632                 dev_info(&socket->dev->dev,
0633                      "TI: parallel PCI interrupts, tied ok\n");
0634                 goto out;
0635             }
0636 
0637             ti12xx_untie_interrupts(socket, old_irq);
0638         }
0639     }
0640 
0641 out:
0642     if (pci_irq_status < 1) {
0643         socket->cb_irq = 0;
0644         dev_info(&socket->dev->dev,
0645              "TI: no PCI interrupts. Fish. Please report.\n");
0646     }
0647 }
0648 
0649 
0650 /* Returns true value if the second slot of a two-slot controller is empty */
0651 static int ti12xx_2nd_slot_empty(struct yenta_socket *socket)
0652 {
0653     struct pci_dev *func;
0654     struct yenta_socket *slot2;
0655     int devfn;
0656     unsigned int state;
0657     int ret = 1;
0658     u32 sysctl;
0659 
0660     /* catch the two-slot controllers */
0661     switch (socket->dev->device) {
0662     case PCI_DEVICE_ID_TI_1220:
0663     case PCI_DEVICE_ID_TI_1221:
0664     case PCI_DEVICE_ID_TI_1225:
0665     case PCI_DEVICE_ID_TI_1251A:
0666     case PCI_DEVICE_ID_TI_1251B:
0667     case PCI_DEVICE_ID_TI_1420:
0668     case PCI_DEVICE_ID_TI_1450:
0669     case PCI_DEVICE_ID_TI_1451A:
0670     case PCI_DEVICE_ID_TI_1520:
0671     case PCI_DEVICE_ID_TI_1620:
0672     case PCI_DEVICE_ID_TI_4520:
0673     case PCI_DEVICE_ID_TI_4450:
0674     case PCI_DEVICE_ID_TI_4451:
0675         /*
0676          * there are way more, but they need to be added in yenta_socket.c
0677          * and pci_ids.h first anyway.
0678          */
0679         break;
0680 
0681     case PCI_DEVICE_ID_TI_XX12:
0682     case PCI_DEVICE_ID_TI_X515:
0683     case PCI_DEVICE_ID_TI_X420:
0684     case PCI_DEVICE_ID_TI_X620:
0685     case PCI_DEVICE_ID_TI_XX21_XX11:
0686     case PCI_DEVICE_ID_TI_7410:
0687     case PCI_DEVICE_ID_TI_7610:
0688         /*
0689          * those are either single or dual slot CB with additional functions
0690          * like 1394, smartcard reader, etc. check the TIEALL flag for them
0691          * the TIEALL flag binds the IRQ of all functions together.
0692          * we catch the single slot variants later.
0693          */
0694         sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL);
0695         if (sysctl & TIXX21_SCR_TIEALL)
0696             return 0;
0697 
0698         break;
0699 
0700     /* single-slot controllers have the 2nd slot empty always :) */
0701     default:
0702         return 1;
0703     }
0704 
0705     /* get other slot */
0706     devfn = socket->dev->devfn & ~0x07;
0707     func = pci_get_slot(socket->dev->bus,
0708                         (socket->dev->devfn & 0x07) ? devfn : devfn | 0x01);
0709     if (!func)
0710         return 1;
0711 
0712     /*
0713      * check that the device id of both slots match. this is needed for the
0714      * XX21 and the XX11 controller that share the same device id for single
0715      * and dual slot controllers. return '2nd slot empty'. we already checked
0716      * if the interrupt is tied to another function.
0717      */
0718     if (socket->dev->device != func->device)
0719         goto out;
0720 
0721     slot2 = pci_get_drvdata(func);
0722     if (!slot2)
0723         goto out;
0724 
0725     /* check state */
0726     yenta_get_status(&slot2->socket, &state);
0727     if (state & SS_DETECT) {
0728         ret = 0;
0729         goto out;
0730     }
0731 
0732 out:
0733     pci_dev_put(func);
0734     return ret;
0735 }
0736 
0737 /*
0738  * TI specifiy parts for the power hook.
0739  *
0740  * some TI's with some CB's produces interrupt storm on power on. it has been
0741  * seen with atheros wlan cards on TI1225 and TI1410. solution is simply to
0742  * disable any CB interrupts during this time.
0743  */
0744 static int ti12xx_power_hook(struct pcmcia_socket *sock, int operation)
0745 {
0746     struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
0747     u32 mfunc, devctl, sysctl;
0748     u8 gpio3;
0749 
0750     /* only POWER_PRE and POWER_POST are interesting */
0751     if ((operation != HOOK_POWER_PRE) && (operation != HOOK_POWER_POST))
0752         return 0;
0753 
0754     devctl = config_readb(socket, TI113X_DEVICE_CONTROL);
0755     sysctl = config_readl(socket, TI113X_SYSTEM_CONTROL);
0756     mfunc = config_readl(socket, TI122X_MFUNC);
0757 
0758     /*
0759      * all serial/tied: only disable when modparm set. always doing it
0760      * would mean a regression for working setups 'cos it disables the
0761      * interrupts for both both slots on 2-slot controllers
0762      * (and users of single slot controllers where it's save have to
0763      * live with setting the modparm, most don't have to anyway)
0764      */
0765     if (((devctl & TI113X_DCR_IMODE_MASK) == TI12XX_DCR_IMODE_ALL_SERIAL) &&
0766         (pwr_irqs_off || ti12xx_2nd_slot_empty(socket))) {
0767         switch (socket->dev->device) {
0768         case PCI_DEVICE_ID_TI_1250:
0769         case PCI_DEVICE_ID_TI_1251A:
0770         case PCI_DEVICE_ID_TI_1251B:
0771         case PCI_DEVICE_ID_TI_1450:
0772         case PCI_DEVICE_ID_TI_1451A:
0773         case PCI_DEVICE_ID_TI_4450:
0774         case PCI_DEVICE_ID_TI_4451:
0775             /* these chips have no IRQSER setting in MFUNC3  */
0776             break;
0777 
0778         default:
0779             if (operation == HOOK_POWER_PRE)
0780                 mfunc = (mfunc & ~TI122X_MFUNC3_MASK);
0781             else
0782                 mfunc = (mfunc & ~TI122X_MFUNC3_MASK) | TI122X_MFUNC3_IRQSER;
0783         }
0784 
0785         return 0;
0786     }
0787 
0788     /* do the job differently for func0/1 */
0789     if ((PCI_FUNC(socket->dev->devfn) == 0) ||
0790         ((sysctl & TI122X_SCR_INTRTIE) &&
0791          (pwr_irqs_off || ti12xx_2nd_slot_empty(socket)))) {
0792         /* some bridges are different */
0793         switch (socket->dev->device) {
0794         case PCI_DEVICE_ID_TI_1250:
0795         case PCI_DEVICE_ID_TI_1251A:
0796         case PCI_DEVICE_ID_TI_1251B:
0797         case PCI_DEVICE_ID_TI_1450:
0798             /* those oldies use gpio3 for INTA */
0799             gpio3 = config_readb(socket, TI1250_GPIO3_CONTROL);
0800             if (operation == HOOK_POWER_PRE)
0801                 gpio3 = (gpio3 & ~TI1250_GPIO_MODE_MASK) | 0x40;
0802             else
0803                 gpio3 &= ~TI1250_GPIO_MODE_MASK;
0804             config_writeb(socket, TI1250_GPIO3_CONTROL, gpio3);
0805             break;
0806 
0807         default:
0808             /* all new bridges are the same */
0809             if (operation == HOOK_POWER_PRE)
0810                 mfunc &= ~TI122X_MFUNC0_MASK;
0811             else
0812                 mfunc |= TI122X_MFUNC0_INTA;
0813             config_writel(socket, TI122X_MFUNC, mfunc);
0814         }
0815     } else {
0816         switch (socket->dev->device) {
0817         case PCI_DEVICE_ID_TI_1251A:
0818         case PCI_DEVICE_ID_TI_1251B:
0819         case PCI_DEVICE_ID_TI_1450:
0820             /* those have INTA elsewhere and INTB in MFUNC0 */
0821             if (operation == HOOK_POWER_PRE)
0822                 mfunc &= ~TI122X_MFUNC0_MASK;
0823             else
0824                 mfunc |= TI125X_MFUNC0_INTB;
0825             config_writel(socket, TI122X_MFUNC, mfunc);
0826 
0827             break;
0828 
0829         default:
0830             /* all new bridges are the same */
0831             if (operation == HOOK_POWER_PRE)
0832                 mfunc &= ~TI122X_MFUNC1_MASK;
0833             else
0834                 mfunc |= TI122X_MFUNC1_INTB;
0835             config_writel(socket, TI122X_MFUNC, mfunc);
0836         }
0837     }
0838 
0839     return 0;
0840 }
0841 
0842 static int ti12xx_override(struct yenta_socket *socket)
0843 {
0844     u32 val, val_orig;
0845 
0846     /* make sure that memory burst is active */
0847     val_orig = val = config_readl(socket, TI113X_SYSTEM_CONTROL);
0848     if (disable_clkrun && PCI_FUNC(socket->dev->devfn) == 0) {
0849         dev_info(&socket->dev->dev, "Disabling CLKRUN feature\n");
0850         val |= TI113X_SCR_KEEPCLK;
0851     }
0852     if (!(val & TI122X_SCR_MRBURSTUP)) {
0853         dev_info(&socket->dev->dev,
0854              "Enabling burst memory read transactions\n");
0855         val |= TI122X_SCR_MRBURSTUP;
0856     }
0857     if (val_orig != val)
0858         config_writel(socket, TI113X_SYSTEM_CONTROL, val);
0859 
0860     /*
0861      * Yenta expects controllers to use CSCINT to route
0862      * CSC interrupts to PCI rather than INTVAL.
0863      */
0864     val = config_readb(socket, TI1250_DIAGNOSTIC);
0865     dev_info(&socket->dev->dev, "Using %s to route CSC interrupts to PCI\n",
0866          (val & TI1250_DIAG_PCI_CSC) ? "CSCINT" : "INTVAL");
0867     dev_info(&socket->dev->dev, "Routing CardBus interrupts to %s\n",
0868          (val & TI1250_DIAG_PCI_IREQ) ? "PCI" : "ISA");
0869 
0870     /* do irqrouting, depending on function */
0871     if (PCI_FUNC(socket->dev->devfn) == 0)
0872         ti12xx_irqroute_func0(socket);
0873     else
0874         ti12xx_irqroute_func1(socket);
0875 
0876     /* install power hook */
0877     socket->socket.power_hook = ti12xx_power_hook;
0878 
0879     return ti_override(socket);
0880 }
0881 
0882 
0883 static int ti1250_override(struct yenta_socket *socket)
0884 {
0885     u8 old, diag;
0886 
0887     old = config_readb(socket, TI1250_DIAGNOSTIC);
0888     diag = old & ~(TI1250_DIAG_PCI_CSC | TI1250_DIAG_PCI_IREQ);
0889     if (socket->cb_irq)
0890         diag |= TI1250_DIAG_PCI_CSC | TI1250_DIAG_PCI_IREQ;
0891 
0892     if (diag != old) {
0893         dev_info(&socket->dev->dev,
0894              "adjusting diagnostic: %02x -> %02x\n",
0895              old, diag);
0896         config_writeb(socket, TI1250_DIAGNOSTIC, diag);
0897     }
0898 
0899     return ti12xx_override(socket);
0900 }
0901 
0902 
0903 /**
0904  * EnE specific part. EnE bridges are register compatible with TI bridges but
0905  * have their own test registers and more important their own little problems.
0906  * Some fixup code to make everybody happy (TM).
0907  */
0908 
0909 #ifdef CONFIG_YENTA_ENE_TUNE
0910 /*
0911  * set/clear various test bits:
0912  * Defaults to clear the bit.
0913  * - mask (u8) defines what bits to change
0914  * - bits (u8) is the values to change them to
0915  * -> it's
0916  *  current = (current & ~mask) | bits
0917  */
0918 /* pci ids of devices that wants to have the bit set */
0919 #define DEVID(_vend,_dev,_subvend,_subdev,mask,bits) {      \
0920         .vendor     = _vend,            \
0921         .device     = _dev,             \
0922         .subvendor  = _subvend,         \
0923         .subdevice  = _subdev,          \
0924         .driver_data    = ((mask) << 8 | (bits)),   \
0925     }
0926 static struct pci_device_id ene_tune_tbl[] = {
0927     /* Echo Audio products based on motorola DSP56301 and DSP56361 */
0928     DEVID(PCI_VENDOR_ID_MOTOROLA, 0x1801, 0xECC0, PCI_ANY_ID,
0929         ENE_TEST_C9_TLTENABLE | ENE_TEST_C9_PFENABLE, ENE_TEST_C9_TLTENABLE),
0930     DEVID(PCI_VENDOR_ID_MOTOROLA, 0x3410, 0xECC0, PCI_ANY_ID,
0931         ENE_TEST_C9_TLTENABLE | ENE_TEST_C9_PFENABLE, ENE_TEST_C9_TLTENABLE),
0932 
0933     {}
0934 };
0935 
0936 static void ene_tune_bridge(struct pcmcia_socket *sock, struct pci_bus *bus)
0937 {
0938     struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
0939     struct pci_dev *dev;
0940     struct pci_device_id *id = NULL;
0941     u8 test_c9, old_c9, mask, bits;
0942 
0943     list_for_each_entry(dev, &bus->devices, bus_list) {
0944         id = (struct pci_device_id *) pci_match_id(ene_tune_tbl, dev);
0945         if (id)
0946             break;
0947     }
0948 
0949     test_c9 = old_c9 = config_readb(socket, ENE_TEST_C9);
0950     if (id) {
0951         mask = (id->driver_data >> 8) & 0xFF;
0952         bits = id->driver_data & 0xFF;
0953 
0954         test_c9 = (test_c9 & ~mask) | bits;
0955     }
0956     else
0957         /* default to clear TLTEnable bit, old behaviour */
0958         test_c9 &= ~ENE_TEST_C9_TLTENABLE;
0959 
0960     dev_info(&socket->dev->dev,
0961          "EnE: changing testregister 0xC9, %02x -> %02x\n",
0962          old_c9, test_c9);
0963     config_writeb(socket, ENE_TEST_C9, test_c9);
0964 }
0965 
0966 static int ene_override(struct yenta_socket *socket)
0967 {
0968     /* install tune_bridge() function */
0969     socket->socket.tune_bridge = ene_tune_bridge;
0970 
0971     return ti1250_override(socket);
0972 }
0973 #else
0974 #  define ene_override ti1250_override
0975 #endif /* !CONFIG_YENTA_ENE_TUNE */
0976 
0977 #endif /* _LINUX_TI113X_H */
0978
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