drivers/pcmcia/sa11xx_base.h

0001 /*======================================================================
0002
0003     Device driver for the PCMCIA control functionality of StrongARM
0004     SA-1100 microprocessors.
0005
0006     The contents of this file are subject to the Mozilla Public
0007     License Version 1.1 (the "License"); you may not use this file
0008     except in compliance with the License. You may obtain a copy of
0009     the License at http://www.mozilla.org/MPL/
0010
0011     Software distributed under the License is distributed on an "AS
0012     IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
0013     implied. See the License for the specific language governing
0014     rights and limitations under the License.
0015
0016     The initial developer of the original code is John G. Dorsey
0017     <john+@cs.cmu.edu>.  Portions created by John G. Dorsey are
0018     Copyright (C) 1999 John G. Dorsey.  All Rights Reserved.
0019
0020     Alternatively, the contents of this file may be used under the
0021     terms of the GNU Public License version 2 (the "GPL"), in which
0022     case the provisions of the GPL are applicable instead of the
0023     above.  If you wish to allow the use of your version of this file
0024     only under the terms of the GPL and not to allow others to use
0025     your version of this file under the MPL, indicate your decision
0026     by deleting the provisions above and replace them with the notice
0027     and other provisions required by the GPL.  If you do not delete
0028     the provisions above, a recipient may use your version of this
0029     file under either the MPL or the GPL.
0030
0031 ======================================================================*/
0032
0033 #if !defined(_PCMCIA_SA1100_H)
0034 # define _PCMCIA_SA1100_H
0035
0036 /* SA-1100 PCMCIA Memory and I/O timing
0037  * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
0038  * The SA-1110 Developer's Manual, section 10.2.5, says the following:
0039  *
0040  *  "To calculate the recommended BS_xx value for each address space:
0041  *   divide the command width time (the greater of twIOWR and twIORD,
0042  *   or the greater of twWE and twOE) by processor cycle time; divide
0043  *   by 2; divide again by 3 (number of BCLK's per command assertion);
0044  *   round up to the next whole number; and subtract 1."
0045  */
0046
0047 /* MECR: Expansion Memory Configuration Register
0048  * (SA-1100 Developers Manual, p.10-13; SA-1110 Developers Manual, p.10-24)
0049  *
0050  * MECR layout is:
0051  *
0052  *   FAST1 BSM1<4:0> BSA1<4:0> BSIO1<4:0> FAST0 BSM0<4:0> BSA0<4:0> BSIO0<4:0>
0053  *
0054  * (This layout is actually true only for the SA-1110; the FASTn bits are
0055  * reserved on the SA-1100.)
0056  */
0057
0058 #define MECR_SOCKET_0_SHIFT (0)
0059 #define MECR_SOCKET_1_SHIFT (16)
0060
0061 #define MECR_BS_MASK        (0x1f)
0062 #define MECR_FAST_MODE_MASK (0x01)
0063
0064 #define MECR_BSIO_SHIFT (0)
0065 #define MECR_BSA_SHIFT  (5)
0066 #define MECR_BSM_SHIFT  (10)
0067 #define MECR_FAST_SHIFT (15)
0068
0069 #define MECR_SET(mecr, sock, shift, mask, bs) \
0070 ((mecr)=((mecr)&~(((mask)<<(shift))<<\
0071                   ((sock)==0?MECR_SOCKET_0_SHIFT:MECR_SOCKET_1_SHIFT)))|\
0072         (((bs)<<(shift))<<((sock)==0?MECR_SOCKET_0_SHIFT:MECR_SOCKET_1_SHIFT)))
0073
0074 #define MECR_GET(mecr, sock, shift, mask) \
0075 ((((mecr)>>(((sock)==0)?MECR_SOCKET_0_SHIFT:MECR_SOCKET_1_SHIFT))>>\
0076  (shift))&(mask))
0077
0078 #define MECR_BSIO_SET(mecr, sock, bs) \
0079 MECR_SET((mecr), (sock), MECR_BSIO_SHIFT, MECR_BS_MASK, (bs))
0080
0081 #define MECR_BSIO_GET(mecr, sock) \
0082 MECR_GET((mecr), (sock), MECR_BSIO_SHIFT, MECR_BS_MASK)
0083
0084 #define MECR_BSA_SET(mecr, sock, bs) \
0085 MECR_SET((mecr), (sock), MECR_BSA_SHIFT, MECR_BS_MASK, (bs))
0086
0087 #define MECR_BSA_GET(mecr, sock) \
0088 MECR_GET((mecr), (sock), MECR_BSA_SHIFT, MECR_BS_MASK)
0089
0090 #define MECR_BSM_SET(mecr, sock, bs) \
0091 MECR_SET((mecr), (sock), MECR_BSM_SHIFT, MECR_BS_MASK, (bs))
0092
0093 #define MECR_BSM_GET(mecr, sock) \
0094 MECR_GET((mecr), (sock), MECR_BSM_SHIFT, MECR_BS_MASK)
0095
0096 #define MECR_FAST_SET(mecr, sock, fast) \
0097 MECR_SET((mecr), (sock), MECR_FAST_SHIFT, MECR_FAST_MODE_MASK, (fast))
0098
0099 #define MECR_FAST_GET(mecr, sock) \
0100 MECR_GET((mecr), (sock), MECR_FAST_SHIFT, MECR_FAST_MODE_MASK)
0101
0102
0103 /* This function implements the BS value calculation for setting the MECR
0104  * using integer arithmetic:
0105  */
0106 static inline unsigned int sa1100_pcmcia_mecr_bs(unsigned int pcmcia_cycle_ns,
0107                          unsigned int cpu_clock_khz){
0108   unsigned int t = ((pcmcia_cycle_ns * cpu_clock_khz) / 6) - 1000000;
0109   return (t / 1000000) + (((t % 1000000) == 0) ? 0 : 1);
0110 }
0111
0112 /* This function returns the (approximate) command assertion period, in
0113  * nanoseconds, for a given CPU clock frequency and MECR BS value:
0114  */
0115 static inline unsigned int sa1100_pcmcia_cmd_time(unsigned int cpu_clock_khz,
0116                           unsigned int pcmcia_mecr_bs){
0117   return (((10000000 * 2) / cpu_clock_khz) * (3 * (pcmcia_mecr_bs + 1))) / 10;
0118 }
0119
0120
0121 int sa11xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt);
0122 void sa11xx_drv_pcmcia_ops(struct pcmcia_low_level *ops);
0123 extern int sa11xx_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, int first, int nr);
0124
0125 #endif  /* !defined(_PCMCIA_SA1100_H) */