drivers/pcmcia/ricoh.h

0001 /*
0002  * ricoh.h 1.9 1999/10/25 20:03:34
0003  *
0004  * The contents of this file are subject to the Mozilla Public License
0005  * Version 1.1 (the "License"); you may not use this file except in
0006  * compliance with the License. You may obtain a copy of the License
0007  * at http://www.mozilla.org/MPL/
0008  *
0009  * Software distributed under the License is distributed on an "AS IS"
0010  * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
0011  * the License for the specific language governing rights and
0012  * limitations under the License.
0013  *
0014  * The initial developer of the original code is David A. Hinds
0015  * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
0016  * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
0017  *
0018  * Alternatively, the contents of this file may be used under the
0019  * terms of the GNU General Public License version 2 (the "GPL"), in which
0020  * case the provisions of the GPL are applicable instead of the
0021  * above.  If you wish to allow the use of your version of this file
0022  * only under the terms of the GPL and not to allow others to use
0023  * your version of this file under the MPL, indicate your decision by
0024  * deleting the provisions above and replace them with the notice and
0025  * other provisions required by the GPL.  If you do not delete the
0026  * provisions above, a recipient may use your version of this file
0027  * under either the MPL or the GPL.
0028  */
0029
0030 #ifndef _LINUX_RICOH_H
0031 #define _LINUX_RICOH_H
0032
0033
0034 #define RF5C_MODE_CTL       0x1f    /* Mode control */
0035 #define RF5C_PWR_CTL        0x2f    /* Mixed voltage control */
0036 #define RF5C_CHIP_ID        0x3a    /* Chip identification */
0037 #define RF5C_MODE_CTL_3     0x3b    /* Mode control 3 */
0038
0039 /* I/O window address offset */
0040 #define RF5C_IO_OFF(w)      (0x36+((w)<<1))
0041
0042 /* Flags for RF5C_MODE_CTL */
0043 #define RF5C_MODE_ATA       0x01    /* ATA mode */
0044 #define RF5C_MODE_LED_ENA   0x02    /* IRQ 12 is LED */
0045 #define RF5C_MODE_CA21      0x04
0046 #define RF5C_MODE_CA22      0x08
0047 #define RF5C_MODE_CA23      0x10
0048 #define RF5C_MODE_CA24      0x20
0049 #define RF5C_MODE_CA25      0x40
0050 #define RF5C_MODE_3STATE_BIT7   0x80
0051
0052 /* Flags for RF5C_PWR_CTL */
0053 #define RF5C_PWR_VCC_3V     0x01
0054 #define RF5C_PWR_IREQ_HIGH  0x02
0055 #define RF5C_PWR_INPACK_ENA 0x04
0056 #define RF5C_PWR_5V_DET     0x08
0057 #define RF5C_PWR_TC_SEL     0x10    /* Terminal Count: irq 11 or 15 */
0058 #define RF5C_PWR_DREQ_LOW   0x20
0059 #define RF5C_PWR_DREQ_OFF   0x00    /* DREQ steering control */
0060 #define RF5C_PWR_DREQ_INPACK    0x40
0061 #define RF5C_PWR_DREQ_SPKR  0x80
0062 #define RF5C_PWR_DREQ_IOIS16    0xc0
0063
0064 /* Values for RF5C_CHIP_ID */
0065 #define RF5C_CHIP_RF5C296   0x32
0066 #define RF5C_CHIP_RF5C396   0xb2
0067
0068 /* Flags for RF5C_MODE_CTL_3 */
0069 #define RF5C_MCTL3_DISABLE  0x01    /* Disable PCMCIA interface */
0070 #define RF5C_MCTL3_DMA_ENA  0x02
0071
0072 /* Register definitions for Ricoh PCI-to-CardBus bridges */
0073
0074 /* Extra bits in CB_BRIDGE_CONTROL */
0075 #define RL5C46X_BCR_3E0_ENA     0x0800
0076 #define RL5C46X_BCR_3E2_ENA     0x1000
0077
0078 /* Bridge Configuration Register */
0079 #define RL5C4XX_CONFIG          0x80    /* 16 bit */
0080 #define  RL5C4XX_CONFIG_IO_1_MODE   0x0200
0081 #define  RL5C4XX_CONFIG_IO_0_MODE   0x0100
0082 #define  RL5C4XX_CONFIG_PREFETCH    0x0001
0083
0084 /* Misc Control Register */
0085 #define RL5C4XX_MISC            0x0082  /* 16 bit */
0086 #define  RL5C4XX_MISC_HW_SUSPEND_ENA    0x0002
0087 #define  RL5C4XX_MISC_VCCEN_POL     0x0100
0088 #define  RL5C4XX_MISC_VPPEN_POL     0x0200
0089 #define  RL5C46X_MISC_SUSPEND       0x0001
0090 #define  RL5C46X_MISC_PWR_SAVE_2    0x0004
0091 #define  RL5C46X_MISC_IFACE_BUSY    0x0008
0092 #define  RL5C46X_MISC_B_LOCK        0x0010
0093 #define  RL5C46X_MISC_A_LOCK        0x0020
0094 #define  RL5C46X_MISC_PCI_LOCK      0x0040
0095 #define  RL5C47X_MISC_IFACE_BUSY    0x0004
0096 #define  RL5C47X_MISC_PCI_INT_MASK  0x0018
0097 #define  RL5C47X_MISC_PCI_INT_DIS   0x0020
0098 #define  RL5C47X_MISC_SUBSYS_WR     0x0040
0099 #define  RL5C47X_MISC_SRIRQ_ENA     0x0080
0100 #define  RL5C47X_MISC_5V_DISABLE    0x0400
0101 #define  RL5C47X_MISC_LED_POL       0x0800
0102
0103 /* 16-bit Interface Control Register */
0104 #define RL5C4XX_16BIT_CTL       0x0084  /* 16 bit */
0105 #define  RL5C4XX_16CTL_IO_TIMING    0x0100
0106 #define  RL5C4XX_16CTL_MEM_TIMING   0x0200
0107 #define  RL5C46X_16CTL_LEVEL_1      0x0010
0108 #define  RL5C46X_16CTL_LEVEL_2      0x0020
0109
0110 /* 16-bit IO and memory timing registers */
0111 #define RL5C4XX_16BIT_IO_0      0x0088  /* 16 bit */
0112 #define RL5C4XX_16BIT_MEM_0     0x008a  /* 16 bit */
0113 #define  RL5C4XX_SETUP_MASK     0x0007
0114 #define  RL5C4XX_SETUP_SHIFT        0
0115 #define  RL5C4XX_CMD_MASK       0x01f0
0116 #define  RL5C4XX_CMD_SHIFT      4
0117 #define  RL5C4XX_HOLD_MASK      0x1c00
0118 #define  RL5C4XX_HOLD_SHIFT     10
0119 #define  RL5C4XX_MISC_CONTROL           0x2F /* 8 bit */
0120 #define  RL5C4XX_ZV_ENABLE              0x08
0121
0122 /* Misc Control 3 Register */
0123 #define RL5C4XX_MISC3           0x00A2 /* 16 bit */
0124 #define  RL5C47X_MISC3_CB_CLKRUN_DIS    BIT(1)
0125
0126 #ifdef __YENTA_H
0127
0128 #define rl_misc(socket)     ((socket)->private[0])
0129 #define rl_ctl(socket)      ((socket)->private[1])
0130 #define rl_io(socket)       ((socket)->private[2])
0131 #define rl_mem(socket)      ((socket)->private[3])
0132 #define rl_config(socket)   ((socket)->private[4])
0133
0134 static void ricoh_zoom_video(struct pcmcia_socket *sock, int onoff)
0135 {
0136         u8 reg;
0137     struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
0138
0139         reg = config_readb(socket, RL5C4XX_MISC_CONTROL);
0140         if (onoff)
0141                 /* Zoom zoom, we will all go together, zoom zoom, zoom zoom */
0142                 reg |=  RL5C4XX_ZV_ENABLE;
0143         else
0144                 reg &= ~RL5C4XX_ZV_ENABLE;
0145
0146         config_writeb(socket, RL5C4XX_MISC_CONTROL, reg);
0147 }
0148
0149 static void ricoh_set_zv(struct yenta_socket *socket)
0150 {
0151         if(socket->dev->vendor == PCI_VENDOR_ID_RICOH)
0152         {
0153                 switch(socket->dev->device)
0154                 {
0155                         /* There may be more .. */
0156         case  PCI_DEVICE_ID_RICOH_RL5C478:
0157             socket->socket.zoom_video = ricoh_zoom_video;
0158             break;
0159                 }
0160         }
0161 }
0162
0163 static void ricoh_set_clkrun(struct yenta_socket *socket, bool quiet)
0164 {
0165     u16 misc3;
0166
0167     /*
0168      * RL5C475II likely has this setting, too, however no datasheet
0169      * is publicly available for this chip
0170      */
0171     if (socket->dev->device != PCI_DEVICE_ID_RICOH_RL5C476 &&
0172         socket->dev->device != PCI_DEVICE_ID_RICOH_RL5C478)
0173         return;
0174
0175     if (socket->dev->revision < 0x80)
0176         return;
0177
0178     misc3 = config_readw(socket, RL5C4XX_MISC3);
0179     if (misc3 & RL5C47X_MISC3_CB_CLKRUN_DIS) {
0180         if (!quiet)
0181             dev_dbg(&socket->dev->dev,
0182                 "CLKRUN feature already disabled\n");
0183     } else if (disable_clkrun) {
0184         if (!quiet)
0185             dev_info(&socket->dev->dev,
0186                  "Disabling CLKRUN feature\n");
0187         misc3 |= RL5C47X_MISC3_CB_CLKRUN_DIS;
0188         config_writew(socket, RL5C4XX_MISC3, misc3);
0189     }
0190 }
0191
0192 static void ricoh_save_state(struct yenta_socket *socket)
0193 {
0194     rl_misc(socket) = config_readw(socket, RL5C4XX_MISC);
0195     rl_ctl(socket) = config_readw(socket, RL5C4XX_16BIT_CTL);
0196     rl_io(socket) = config_readw(socket, RL5C4XX_16BIT_IO_0);
0197     rl_mem(socket) = config_readw(socket, RL5C4XX_16BIT_MEM_0);
0198     rl_config(socket) = config_readw(socket, RL5C4XX_CONFIG);
0199 }
0200
0201 static void ricoh_restore_state(struct yenta_socket *socket)
0202 {
0203     config_writew(socket, RL5C4XX_MISC, rl_misc(socket));
0204     config_writew(socket, RL5C4XX_16BIT_CTL, rl_ctl(socket));
0205     config_writew(socket, RL5C4XX_16BIT_IO_0, rl_io(socket));
0206     config_writew(socket, RL5C4XX_16BIT_MEM_0, rl_mem(socket));
0207     config_writew(socket, RL5C4XX_CONFIG, rl_config(socket));
0208     ricoh_set_clkrun(socket, true);
0209 }
0210
0211
0212 /*
0213  * Magic Ricoh initialization code..
0214  */
0215 static int ricoh_override(struct yenta_socket *socket)
0216 {
0217     u16 config, ctl;
0218
0219     config = config_readw(socket, RL5C4XX_CONFIG);
0220
0221     /* Set the default timings, don't trust the original values */
0222     ctl = RL5C4XX_16CTL_IO_TIMING | RL5C4XX_16CTL_MEM_TIMING;
0223
0224     if(socket->dev->device < PCI_DEVICE_ID_RICOH_RL5C475) {
0225         ctl |= RL5C46X_16CTL_LEVEL_1 | RL5C46X_16CTL_LEVEL_2;
0226     } else {
0227         config |= RL5C4XX_CONFIG_PREFETCH;
0228     }
0229
0230     config_writew(socket, RL5C4XX_16BIT_CTL, ctl);
0231     config_writew(socket, RL5C4XX_CONFIG, config);
0232
0233     ricoh_set_zv(socket);
0234     ricoh_set_clkrun(socket, false);
0235
0236     return 0;
0237 }
0238
0239 #endif /* CONFIG_CARDBUS */
0240
0241 #endif /* _LINUX_RICOH_H */