drivers/pcmcia/o2micro.h

0001 /*
0002  * o2micro.h 1.13 1999/10/25 20:03:34
0003  *
0004  * The contents of this file are subject to the Mozilla Public License
0005  * Version 1.1 (the "License"); you may not use this file except in
0006  * compliance with the License. You may obtain a copy of the License
0007  * at http://www.mozilla.org/MPL/
0008  *
0009  * Software distributed under the License is distributed on an "AS IS"
0010  * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
0011  * the License for the specific language governing rights and
0012  * limitations under the License.
0013  *
0014  * The initial developer of the original code is David A. Hinds
0015  * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
0016  * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
0017  *
0018  * Alternatively, the contents of this file may be used under the
0019  * terms of the GNU General Public License version 2 (the "GPL"), in which
0020  * case the provisions of the GPL are applicable instead of the
0021  * above.  If you wish to allow the use of your version of this file
0022  * only under the terms of the GPL and not to allow others to use
0023  * your version of this file under the MPL, indicate your decision by
0024  * deleting the provisions above and replace them with the notice and
0025  * other provisions required by the GPL.  If you do not delete the
0026  * provisions above, a recipient may use your version of this file
0027  * under either the MPL or the GPL.
0028  */
0029
0030 #ifndef _LINUX_O2MICRO_H
0031 #define _LINUX_O2MICRO_H
0032
0033 /* Additional PCI configuration registers */
0034
0035 #define O2_MUX_CONTROL      0x90    /* 32 bit */
0036 #define  O2_MUX_RING_OUT    0x0000000f
0037 #define  O2_MUX_SKTB_ACTV   0x000000f0
0038 #define  O2_MUX_SCTA_ACTV_ENA   0x00000100
0039 #define  O2_MUX_SCTB_ACTV_ENA   0x00000200
0040 #define  O2_MUX_SER_IRQ_ROUTE   0x0000e000
0041 #define  O2_MUX_SER_PCI     0x00010000
0042
0043 #define  O2_MUX_SKTA_TURBO  0x000c0000  /* for 6833, 6860 */
0044 #define  O2_MUX_SKTB_TURBO  0x00300000
0045 #define  O2_MUX_AUX_VCC_3V  0x00400000
0046 #define  O2_MUX_PCI_VCC_5V  0x00800000
0047 #define  O2_MUX_PME_MUX     0x0f000000
0048
0049 /* Additional ExCA registers */
0050
0051 #define O2_MODE_A       0x38
0052 #define O2_MODE_A_2     0x26    /* for 6833B, 6860C */
0053 #define  O2_MODE_A_CD_PULSE 0x04
0054 #define  O2_MODE_A_SUSP_EDGE    0x08
0055 #define  O2_MODE_A_HOST_SUSP    0x10
0056 #define  O2_MODE_A_PWR_MASK 0x60
0057 #define  O2_MODE_A_QUIET    0x80
0058
0059 #define O2_MODE_B       0x39
0060 #define O2_MODE_B_2     0x2e    /* for 6833B, 6860C */
0061 #define  O2_MODE_B_IDENT    0x03
0062 #define  O2_MODE_B_ID_BSTEP 0x00
0063 #define  O2_MODE_B_ID_CSTEP 0x01
0064 #define  O2_MODE_B_ID_O2    0x02
0065 #define  O2_MODE_B_VS1      0x04
0066 #define  O2_MODE_B_VS2      0x08
0067 #define  O2_MODE_B_IRQ15_RI 0x80
0068
0069 #define O2_MODE_C       0x3a
0070 #define  O2_MODE_C_DREQ_MASK    0x03
0071 #define  O2_MODE_C_DREQ_INPACK  0x01
0072 #define  O2_MODE_C_DREQ_WP  0x02
0073 #define  O2_MODE_C_DREQ_BVD2    0x03
0074 #define  O2_MODE_C_ZVIDEO   0x08
0075 #define  O2_MODE_C_IREQ_SEL 0x30
0076 #define  O2_MODE_C_MGMT_SEL 0xc0
0077
0078 #define O2_MODE_D       0x3b
0079 #define  O2_MODE_D_IRQ_MODE 0x03
0080 #define  O2_MODE_D_PCI_CLKRUN   0x04
0081 #define  O2_MODE_D_CB_CLKRUN    0x08
0082 #define  O2_MODE_D_SKT_ACTV 0x20
0083 #define  O2_MODE_D_PCI_FIFO 0x40    /* for OZ6729, OZ6730 */
0084 #define  O2_MODE_D_W97_IRQ  0x40
0085 #define  O2_MODE_D_ISA_IRQ  0x80
0086
0087 #define O2_MHPG_DMA     0x3c
0088 #define  O2_MHPG_CHANNEL    0x07
0089 #define  O2_MHPG_CINT_ENA   0x08
0090 #define  O2_MHPG_CSC_ENA    0x10
0091
0092 #define O2_FIFO_ENA     0x3d
0093 #define  O2_FIFO_ZVIDEO_3   0x08
0094 #define  O2_FIFO_PCI_FIFO   0x10
0095 #define  O2_FIFO_POSTWR     0x40
0096 #define  O2_FIFO_BUFFER     0x80
0097
0098 #define O2_MODE_E       0x3e
0099 #define  O2_MODE_E_MHPG_DMA 0x01
0100 #define  O2_MODE_E_SPKR_OUT 0x02
0101 #define  O2_MODE_E_LED_OUT  0x08
0102 #define  O2_MODE_E_SKTA_ACTV    0x10
0103
0104 #define O2_RESERVED1        0x94
0105 #define O2_RESERVED2        0xD4
0106 #define O2_RES_READ_PREFETCH    0x02
0107 #define O2_RES_WRITE_BURST  0x08
0108
0109 static int o2micro_override(struct yenta_socket *socket)
0110 {
0111     /*
0112      * 'reserved' register at 0x94/D4. allows setting read prefetch and write
0113      * bursting. read prefetching for example makes the RME Hammerfall DSP
0114      * working. for some bridges it is at 0x94, for others at 0xD4. it's
0115      * ok to write to both registers on all O2 bridges.
0116      * from Eric Still, 02Micro.
0117      */
0118     u8 a, b;
0119     bool use_speedup;
0120
0121     if (PCI_FUNC(socket->dev->devfn) == 0) {
0122         a = config_readb(socket, O2_RESERVED1);
0123         b = config_readb(socket, O2_RESERVED2);
0124         dev_dbg(&socket->dev->dev, "O2: 0x94/0xD4: %02x/%02x\n", a, b);
0125
0126         switch (socket->dev->device) {
0127         /*
0128          * older bridges have problems with both read prefetch and write
0129          * bursting depending on the combination of the chipset, bridge
0130          * and the cardbus card. so disable them to be on the safe side.
0131          */
0132         case PCI_DEVICE_ID_O2_6729:
0133         case PCI_DEVICE_ID_O2_6730:
0134         case PCI_DEVICE_ID_O2_6812:
0135         case PCI_DEVICE_ID_O2_6832:
0136         case PCI_DEVICE_ID_O2_6836:
0137         case PCI_DEVICE_ID_O2_6933:
0138             use_speedup = false;
0139             break;
0140         default:
0141             use_speedup = true;
0142             break;
0143         }
0144
0145         /* the user may override our decision */
0146         if (strcasecmp(o2_speedup, "on") == 0)
0147             use_speedup = true;
0148         else if (strcasecmp(o2_speedup, "off") == 0)
0149             use_speedup = false;
0150         else if (strcasecmp(o2_speedup, "default") != 0)
0151             dev_warn(&socket->dev->dev,
0152                 "O2: Unknown parameter, using 'default'");
0153
0154         if (use_speedup) {
0155             dev_info(&socket->dev->dev,
0156                 "O2: enabling read prefetch/write burst. If you experience problems or performance issues, use the yenta_socket parameter 'o2_speedup=off'\n");
0157             config_writeb(socket, O2_RESERVED1,
0158                       a | O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST);
0159             config_writeb(socket, O2_RESERVED2,
0160                       b | O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST);
0161         } else {
0162             dev_info(&socket->dev->dev,
0163                 "O2: disabling read prefetch/write burst. If you experience problems or performance issues, use the yenta_socket parameter 'o2_speedup=on'\n");
0164             config_writeb(socket, O2_RESERVED1,
0165                       a & ~(O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST));
0166             config_writeb(socket, O2_RESERVED2,
0167                       b & ~(O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST));
0168         }
0169     }
0170
0171     return 0;
0172 }
0173
0174 static void o2micro_restore_state(struct yenta_socket *socket)
0175 {
0176     /*
0177      * as long as read prefetch is the only thing in
0178      * o2micro_override, it's safe to call it from here
0179      */
0180     o2micro_override(socket);
0181 }
0182
0183 #endif /* _LINUX_O2MICRO_H */