drivers/pcmcia/i82365.h

0001 /*
0002  * i82365.h 1.15 1999/10/25 20:03:34
0003  *
0004  * The contents of this file are subject to the Mozilla Public License
0005  * Version 1.1 (the "License"); you may not use this file except in
0006  * compliance with the License. You may obtain a copy of the License
0007  * at http://www.mozilla.org/MPL/
0008  *
0009  * Software distributed under the License is distributed on an "AS IS"
0010  * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
0011  * the License for the specific language governing rights and
0012  * limitations under the License.
0013  *
0014  * The initial developer of the original code is David A. Hinds
0015  * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
0016  * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
0017  *
0018  * Alternatively, the contents of this file may be used under the
0019  * terms of the GNU General Public License version 2 (the "GPL"), in which
0020  * case the provisions of the GPL are applicable instead of the
0021  * above.  If you wish to allow the use of your version of this file
0022  * only under the terms of the GPL and not to allow others to use
0023  * your version of this file under the MPL, indicate your decision by
0024  * deleting the provisions above and replace them with the notice and
0025  * other provisions required by the GPL.  If you do not delete the
0026  * provisions above, a recipient may use your version of this file
0027  * under either the MPL or the GPL.
0028  */
0029
0030 #ifndef _LINUX_I82365_H
0031 #define _LINUX_I82365_H
0032
0033 /* register definitions for the Intel 82365SL PCMCIA controller */
0034
0035 /* Offsets for PCIC registers */
0036 #define I365_IDENT  0x00    /* Identification and revision */
0037 #define I365_STATUS 0x01    /* Interface status */
0038 #define I365_POWER  0x02    /* Power and RESETDRV control */
0039 #define I365_INTCTL 0x03    /* Interrupt and general control */
0040 #define I365_CSC    0x04    /* Card status change */
0041 #define I365_CSCINT 0x05    /* Card status change interrupt control */
0042 #define I365_ADDRWIN    0x06    /* Address window enable */
0043 #define I365_IOCTL  0x07    /* I/O control */
0044 #define I365_GENCTL 0x16    /* Card detect and general control */
0045 #define I365_GBLCTL 0x1E    /* Global control register */
0046
0047 /* Offsets for I/O and memory window registers */
0048 #define I365_IO(map)    (0x08+((map)<<2))
0049 #define I365_MEM(map)   (0x10+((map)<<3))
0050 #define I365_W_START    0
0051 #define I365_W_STOP 2
0052 #define I365_W_OFF  4
0053
0054 /* Flags for I365_STATUS */
0055 #define I365_CS_BVD1    0x01
0056 #define I365_CS_STSCHG  0x01
0057 #define I365_CS_BVD2    0x02
0058 #define I365_CS_SPKR    0x02
0059 #define I365_CS_DETECT  0x0C
0060 #define I365_CS_WRPROT  0x10
0061 #define I365_CS_READY   0x20    /* Inverted */
0062 #define I365_CS_POWERON 0x40
0063 #define I365_CS_GPI 0x80
0064
0065 /* Flags for I365_POWER */
0066 #define I365_PWR_OFF    0x00    /* Turn off the socket */
0067 #define I365_PWR_OUT    0x80    /* Output enable */
0068 #define I365_PWR_NORESET 0x40   /* Disable RESETDRV on resume */
0069 #define I365_PWR_AUTO   0x20    /* Auto pwr switch enable */
0070 #define I365_VCC_MASK   0x18    /* Mask for turning off Vcc */
0071 /* There are different layouts for B-step and DF-step chips: the B
0072    step has independent Vpp1/Vpp2 control, and the DF step has only
0073    Vpp1 control, plus 3V control */
0074 #define I365_VCC_5V 0x10    /* Vcc = 5.0v */
0075 #define I365_VCC_3V 0x18    /* Vcc = 3.3v */
0076 #define I365_VPP2_MASK  0x0c    /* Mask for turning off Vpp2 */
0077 #define I365_VPP2_5V    0x04    /* Vpp2 = 5.0v */
0078 #define I365_VPP2_12V   0x08    /* Vpp2 = 12.0v */
0079 #define I365_VPP1_MASK  0x03    /* Mask for turning off Vpp1 */
0080 #define I365_VPP1_5V    0x01    /* Vpp1 = 5.0v */
0081 #define I365_VPP1_12V   0x02    /* Vpp1 = 12.0v */
0082
0083 /* Flags for I365_INTCTL */
0084 #define I365_RING_ENA   0x80
0085 #define I365_PC_RESET   0x40
0086 #define I365_PC_IOCARD  0x20
0087 #define I365_INTR_ENA   0x10
0088 #define I365_IRQ_MASK   0x0F
0089
0090 /* Flags for I365_CSC and I365_CSCINT*/
0091 #define I365_CSC_BVD1   0x01
0092 #define I365_CSC_STSCHG 0x01
0093 #define I365_CSC_BVD2   0x02
0094 #define I365_CSC_READY  0x04
0095 #define I365_CSC_DETECT 0x08
0096 #define I365_CSC_ANY    0x0F
0097 #define I365_CSC_GPI    0x10
0098 #define I365_CSC_IRQ_MASK   0xF0
0099
0100 /* Flags for I365_ADDRWIN */
0101 #define I365_ENA_IO(map)    (0x40 << (map))
0102 #define I365_ENA_MEM(map)   (0x01 << (map))
0103
0104 /* Flags for I365_IOCTL */
0105 #define I365_IOCTL_MASK(map)    (0x0F << (map<<2))
0106 #define I365_IOCTL_WAIT(map)    (0x08 << (map<<2))
0107 #define I365_IOCTL_0WS(map) (0x04 << (map<<2))
0108 #define I365_IOCTL_IOCS16(map)  (0x02 << (map<<2))
0109 #define I365_IOCTL_16BIT(map)   (0x01 << (map<<2))
0110
0111 /* Flags for I365_GENCTL */
0112 #define I365_CTL_16DELAY    0x01
0113 #define I365_CTL_RESET      0x02
0114 #define I365_CTL_GPI_ENA    0x04
0115 #define I365_CTL_GPI_CTL    0x08
0116 #define I365_CTL_RESUME     0x10
0117 #define I365_CTL_SW_IRQ     0x20
0118
0119 /* Flags for I365_GBLCTL */
0120 #define I365_GBL_PWRDOWN    0x01
0121 #define I365_GBL_CSC_LEV    0x02
0122 #define I365_GBL_WRBACK     0x04
0123 #define I365_GBL_IRQ_0_LEV  0x08
0124 #define I365_GBL_IRQ_1_LEV  0x10
0125
0126 /* Flags for memory window registers */
0127 #define I365_MEM_16BIT  0x8000  /* In memory start high byte */
0128 #define I365_MEM_0WS    0x4000
0129 #define I365_MEM_WS1    0x8000  /* In memory stop high byte */
0130 #define I365_MEM_WS0    0x4000
0131 #define I365_MEM_WRPROT 0x8000  /* In offset high byte */
0132 #define I365_MEM_REG    0x4000
0133
0134 #define I365_REG(slot, reg) (((slot) << 6) + reg)
0135
0136 #endif /* _LINUX_I82365_H */