drivers/pcmcia/i82092.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Driver for Intel I82092AA PCI-PCMCIA bridge.
0004  *
0005  * (C) 2001 Red Hat, Inc.
0006  *
0007  * Author: Arjan Van De Ven <arjanv@redhat.com>
0008  * Loosly based on i82365.c from the pcmcia-cs package
0009  */
0010
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/pci.h>
0014 #include <linux/init.h>
0015 #include <linux/workqueue.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/device.h>
0018
0019 #include <pcmcia/ss.h>
0020
0021 #include <linux/io.h>
0022
0023 #include "i82092aa.h"
0024 #include "i82365.h"
0025
0026 MODULE_LICENSE("GPL");
0027
0028 /* PCI core routines */
0029 static const struct pci_device_id i82092aa_pci_ids[] = {
0030     { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82092AA_0) },
0031     { }
0032 };
0033 MODULE_DEVICE_TABLE(pci, i82092aa_pci_ids);
0034
0035 static struct pci_driver i82092aa_pci_driver = {
0036     .name       = "i82092aa",
0037     .id_table   = i82092aa_pci_ids,
0038     .probe      = i82092aa_pci_probe,
0039     .remove = i82092aa_pci_remove,
0040 };
0041
0042
0043 /* the pccard structure and its functions */
0044 static struct pccard_operations i82092aa_operations = {
0045     .init           = i82092aa_init,
0046     .get_status     = i82092aa_get_status,
0047     .set_socket     = i82092aa_set_socket,
0048     .set_io_map     = i82092aa_set_io_map,
0049     .set_mem_map        = i82092aa_set_mem_map,
0050 };
0051
0052 /* The card can do up to 4 sockets, allocate a structure for each of them */
0053
0054 struct socket_info {
0055     int number;
0056     int card_state;
0057         /* 0 = no socket,
0058          * 1 = empty socket,
0059          * 2 = card but not initialized,
0060          * 3 = operational card
0061          */
0062     unsigned int io_base;   /* base io address of the socket */
0063
0064     struct pcmcia_socket socket;
0065     struct pci_dev *dev;    /* The PCI device for the socket */
0066 };
0067
0068 #define MAX_SOCKETS 4
0069 static struct socket_info sockets[MAX_SOCKETS];
0070 static int socket_count;    /* shortcut */
0071
0072
0073 static int i82092aa_pci_probe(struct pci_dev *dev,
0074                   const struct pci_device_id *id)
0075 {
0076     unsigned char configbyte;
0077     int i, ret;
0078
0079     ret = pci_enable_device(dev);
0080     if (ret)
0081         return ret;
0082
0083     /* PCI Configuration Control */
0084     pci_read_config_byte(dev, 0x40, &configbyte);
0085
0086     switch (configbyte&6) {
0087     case 0:
0088         socket_count = 2;
0089         break;
0090     case 2:
0091         socket_count = 1;
0092         break;
0093     case 4:
0094     case 6:
0095         socket_count = 4;
0096         break;
0097
0098     default:
0099         dev_err(&dev->dev,
0100             "Oops, you did something we didn't think of.\n");
0101         ret = -EIO;
0102         goto err_out_disable;
0103     }
0104     dev_info(&dev->dev, "configured as a %d socket device.\n",
0105          socket_count);
0106
0107     if (!request_region(pci_resource_start(dev, 0), 2, "i82092aa")) {
0108         ret = -EBUSY;
0109         goto err_out_disable;
0110     }
0111
0112     for (i = 0; i < socket_count; i++) {
0113         sockets[i].card_state = 1; /* 1 = present but empty */
0114         sockets[i].io_base = pci_resource_start(dev, 0);
0115         sockets[i].dev = dev;
0116         sockets[i].socket.features |= SS_CAP_PCCARD;
0117         sockets[i].socket.map_size = 0x1000;
0118         sockets[i].socket.irq_mask = 0;
0119         sockets[i].socket.pci_irq  = dev->irq;
0120         sockets[i].socket.cb_dev  = dev;
0121         sockets[i].socket.owner = THIS_MODULE;
0122
0123         sockets[i].number = i;
0124
0125         if (card_present(i)) {
0126             sockets[i].card_state = 3;
0127             dev_dbg(&dev->dev, "slot %i is occupied\n", i);
0128         } else {
0129             dev_dbg(&dev->dev, "slot %i is vacant\n", i);
0130         }
0131     }
0132
0133     /* Now, specifiy that all interrupts are to be done as PCI interrupts
0134      * bitmask, one bit per event, 1 = PCI interrupt, 0 = ISA interrupt
0135      */
0136     configbyte = 0xFF;
0137
0138     /* PCI Interrupt Routing Register */
0139     pci_write_config_byte(dev, 0x50, configbyte);
0140
0141     /* Register the interrupt handler */
0142     dev_dbg(&dev->dev, "Requesting interrupt %i\n", dev->irq);
0143     ret = request_irq(dev->irq, i82092aa_interrupt, IRQF_SHARED,
0144               "i82092aa", i82092aa_interrupt);
0145     if (ret) {
0146         dev_err(&dev->dev, "Failed to register IRQ %d, aborting\n",
0147             dev->irq);
0148         goto err_out_free_res;
0149     }
0150
0151     for (i = 0; i < socket_count; i++) {
0152         sockets[i].socket.dev.parent = &dev->dev;
0153         sockets[i].socket.ops = &i82092aa_operations;
0154         sockets[i].socket.resource_ops = &pccard_nonstatic_ops;
0155         ret = pcmcia_register_socket(&sockets[i].socket);
0156         if (ret)
0157             goto err_out_free_sockets;
0158     }
0159
0160     return 0;
0161
0162 err_out_free_sockets:
0163     if (i) {
0164         for (i--; i >= 0; i--)
0165             pcmcia_unregister_socket(&sockets[i].socket);
0166     }
0167     free_irq(dev->irq, i82092aa_interrupt);
0168 err_out_free_res:
0169     release_region(pci_resource_start(dev, 0), 2);
0170 err_out_disable:
0171     pci_disable_device(dev);
0172     return ret;
0173 }
0174
0175 static void i82092aa_pci_remove(struct pci_dev *dev)
0176 {
0177     int i;
0178
0179     free_irq(dev->irq, i82092aa_interrupt);
0180
0181     for (i = 0; i < socket_count; i++)
0182         pcmcia_unregister_socket(&sockets[i].socket);
0183 }
0184
0185 static DEFINE_SPINLOCK(port_lock);
0186
0187 /* basic value read/write functions */
0188
0189 static unsigned char indirect_read(int socket, unsigned short reg)
0190 {
0191     unsigned short int port;
0192     unsigned char val;
0193     unsigned long flags;
0194
0195     spin_lock_irqsave(&port_lock, flags);
0196     reg += socket * 0x40;
0197     port = sockets[socket].io_base;
0198     outb(reg, port);
0199     val = inb(port+1);
0200     spin_unlock_irqrestore(&port_lock, flags);
0201     return val;
0202 }
0203
0204 static void indirect_write(int socket, unsigned short reg, unsigned char value)
0205 {
0206     unsigned short int port;
0207     unsigned long flags;
0208
0209     spin_lock_irqsave(&port_lock, flags);
0210     reg = reg + socket * 0x40;
0211     port = sockets[socket].io_base;
0212     outb(reg, port);
0213     outb(value, port+1);
0214     spin_unlock_irqrestore(&port_lock, flags);
0215 }
0216
0217 static void indirect_setbit(int socket, unsigned short reg, unsigned char mask)
0218 {
0219     unsigned short int port;
0220     unsigned char val;
0221     unsigned long flags;
0222
0223     spin_lock_irqsave(&port_lock, flags);
0224     reg = reg + socket * 0x40;
0225     port = sockets[socket].io_base;
0226     outb(reg, port);
0227     val = inb(port+1);
0228     val |= mask;
0229     outb(reg, port);
0230     outb(val, port+1);
0231     spin_unlock_irqrestore(&port_lock, flags);
0232 }
0233
0234
0235 static void indirect_resetbit(int socket,
0236                   unsigned short reg, unsigned char mask)
0237 {
0238     unsigned short int port;
0239     unsigned char val;
0240     unsigned long flags;
0241
0242     spin_lock_irqsave(&port_lock, flags);
0243     reg = reg + socket * 0x40;
0244     port = sockets[socket].io_base;
0245     outb(reg, port);
0246     val = inb(port+1);
0247     val &= ~mask;
0248     outb(reg, port);
0249     outb(val, port+1);
0250     spin_unlock_irqrestore(&port_lock, flags);
0251 }
0252
0253 static void indirect_write16(int socket,
0254                  unsigned short reg, unsigned short value)
0255 {
0256     unsigned short int port;
0257     unsigned char val;
0258     unsigned long flags;
0259
0260     spin_lock_irqsave(&port_lock, flags);
0261     reg = reg + socket * 0x40;
0262     port = sockets[socket].io_base;
0263
0264     outb(reg, port);
0265     val = value & 255;
0266     outb(val, port+1);
0267
0268     reg++;
0269
0270     outb(reg, port);
0271     val = value>>8;
0272     outb(val, port+1);
0273     spin_unlock_irqrestore(&port_lock, flags);
0274 }
0275
0276 /* simple helper functions */
0277 /* External clock time, in nanoseconds.  120 ns = 8.33 MHz */
0278 static int cycle_time = 120;
0279
0280 static int to_cycles(int ns)
0281 {
0282     if (cycle_time != 0)
0283         return ns/cycle_time;
0284     else
0285         return 0;
0286 }
0287
0288
0289 /* Interrupt handler functionality */
0290
0291 static irqreturn_t i82092aa_interrupt(int irq, void *dev)
0292 {
0293     int i;
0294     int loopcount = 0;
0295     int handled = 0;
0296
0297     unsigned int events, active = 0;
0298
0299     while (1) {
0300         loopcount++;
0301         if (loopcount > 20) {
0302             pr_err("i82092aa: infinite eventloop in interrupt\n");
0303             break;
0304         }
0305
0306         active = 0;
0307
0308         for (i = 0; i < socket_count; i++) {
0309             int csc;
0310
0311             /* Inactive socket, should not happen */
0312             if (sockets[i].card_state == 0)
0313                 continue;
0314
0315             /* card status change register */
0316             csc = indirect_read(i, I365_CSC);
0317
0318             if (csc == 0)  /* no events on this socket */
0319                 continue;
0320             handled = 1;
0321             events = 0;
0322
0323             if (csc & I365_CSC_DETECT) {
0324                 events |= SS_DETECT;
0325                 dev_info(&sockets[i].dev->dev,
0326                      "Card detected in socket %i!\n", i);
0327             }
0328
0329             if (indirect_read(i, I365_INTCTL) & I365_PC_IOCARD) {
0330                 /* For IO/CARDS, bit 0 means "read the card" */
0331                 if (csc & I365_CSC_STSCHG)
0332                     events |= SS_STSCHG;
0333             } else {
0334                 /* Check for battery/ready events */
0335                 if (csc & I365_CSC_BVD1)
0336                     events |= SS_BATDEAD;
0337                 if (csc & I365_CSC_BVD2)
0338                     events |= SS_BATWARN;
0339                 if (csc & I365_CSC_READY)
0340                     events |= SS_READY;
0341             }
0342
0343             if (events)
0344                 pcmcia_parse_events(&sockets[i].socket, events);
0345             active |= events;
0346         }
0347
0348         if (active == 0) /* no more events to handle */
0349             break;
0350     }
0351     return IRQ_RETVAL(handled);
0352 }
0353
0354
0355
0356 /* socket functions */
0357
0358 static int card_present(int socketno)
0359 {
0360     unsigned int val;
0361
0362     if ((socketno < 0) || (socketno >= MAX_SOCKETS))
0363         return 0;
0364     if (sockets[socketno].io_base == 0)
0365         return 0;
0366
0367
0368     val = indirect_read(socketno, 1); /* Interface status register */
0369     if ((val&12) == 12)
0370         return 1;
0371
0372     return 0;
0373 }
0374
0375 static void set_bridge_state(int sock)
0376 {
0377     indirect_write(sock, I365_GBLCTL, 0x00);
0378     indirect_write(sock, I365_GENCTL, 0x00);
0379
0380     indirect_setbit(sock, I365_INTCTL, 0x08);
0381 }
0382
0383
0384 static int i82092aa_init(struct pcmcia_socket *sock)
0385 {
0386     int i;
0387     struct resource res = { .start = 0, .end = 0x0fff };
0388     pccard_io_map io = { 0, 0, 0, 0, 1 };
0389     pccard_mem_map mem = { .res = &res, };
0390
0391     for (i = 0; i < 2; i++) {
0392         io.map = i;
0393         i82092aa_set_io_map(sock, &io);
0394     }
0395     for (i = 0; i < 5; i++) {
0396         mem.map = i;
0397         i82092aa_set_mem_map(sock, &mem);
0398     }
0399
0400     return 0;
0401 }
0402
0403 static int i82092aa_get_status(struct pcmcia_socket *socket, u_int *value)
0404 {
0405     unsigned int sock = container_of(socket,
0406                 struct socket_info, socket)->number;
0407     unsigned int status;
0408
0409     /* Interface Status Register */
0410     status = indirect_read(sock, I365_STATUS);
0411
0412     *value = 0;
0413
0414     if ((status & I365_CS_DETECT) == I365_CS_DETECT)
0415         *value |= SS_DETECT;
0416
0417     /* IO cards have a different meaning of bits 0,1 */
0418     /* Also notice the inverse-logic on the bits */
0419     if (indirect_read(sock, I365_INTCTL) & I365_PC_IOCARD) {
0420         /* IO card */
0421         if (!(status & I365_CS_STSCHG))
0422             *value |= SS_STSCHG;
0423     } else { /* non I/O card */
0424         if (!(status & I365_CS_BVD1))
0425             *value |= SS_BATDEAD;
0426         if (!(status & I365_CS_BVD2))
0427             *value |= SS_BATWARN;
0428     }
0429
0430     if (status & I365_CS_WRPROT)
0431         (*value) |= SS_WRPROT;  /* card is write protected */
0432
0433     if (status & I365_CS_READY)
0434         (*value) |= SS_READY;    /* card is not busy */
0435
0436     if (status & I365_CS_POWERON)
0437         (*value) |= SS_POWERON;  /* power is applied to the card */
0438
0439     return 0;
0440 }
0441
0442
0443 static int i82092aa_set_socket(struct pcmcia_socket *socket,
0444                    socket_state_t *state)
0445 {
0446     struct socket_info *sock_info = container_of(socket, struct socket_info,
0447                              socket);
0448     unsigned int sock = sock_info->number;
0449     unsigned char reg;
0450
0451     /* First, set the global controller options */
0452
0453     set_bridge_state(sock);
0454
0455     /* Values for the IGENC register */
0456
0457     reg = 0;
0458
0459     /* The reset bit has "inverse" logic */
0460     if (!(state->flags & SS_RESET))
0461         reg = reg | I365_PC_RESET;
0462     if (state->flags & SS_IOCARD)
0463         reg = reg | I365_PC_IOCARD;
0464
0465     /* IGENC, Interrupt and General Control Register */
0466     indirect_write(sock, I365_INTCTL, reg);
0467
0468     /* Power registers */
0469
0470     reg = I365_PWR_NORESET; /* default: disable resetdrv on resume */
0471
0472     if (state->flags & SS_PWR_AUTO) {
0473         dev_info(&sock_info->dev->dev, "Auto power\n");
0474         reg |= I365_PWR_AUTO;   /* automatic power mngmnt */
0475     }
0476     if (state->flags & SS_OUTPUT_ENA) {
0477         dev_info(&sock_info->dev->dev, "Power Enabled\n");
0478         reg |= I365_PWR_OUT;    /* enable power */
0479     }
0480
0481     switch (state->Vcc) {
0482     case 0:
0483         break;
0484     case 50:
0485         dev_info(&sock_info->dev->dev,
0486              "setting voltage to Vcc to 5V on socket %i\n",
0487              sock);
0488         reg |= I365_VCC_5V;
0489         break;
0490     default:
0491         dev_err(&sock_info->dev->dev,
0492             "%s called with invalid VCC power value: %i",
0493             __func__, state->Vcc);
0494         return -EINVAL;
0495     }
0496
0497     switch (state->Vpp) {
0498     case 0:
0499         dev_info(&sock_info->dev->dev,
0500              "not setting Vpp on socket %i\n", sock);
0501         break;
0502     case 50:
0503         dev_info(&sock_info->dev->dev,
0504              "setting Vpp to 5.0 for socket %i\n", sock);
0505         reg |= I365_VPP1_5V | I365_VPP2_5V;
0506         break;
0507     case 120:
0508         dev_info(&sock_info->dev->dev, "setting Vpp to 12.0\n");
0509         reg |= I365_VPP1_12V | I365_VPP2_12V;
0510         break;
0511     default:
0512         dev_err(&sock_info->dev->dev,
0513             "%s called with invalid VPP power value: %i",
0514             __func__, state->Vcc);
0515         return -EINVAL;
0516     }
0517
0518     if (reg != indirect_read(sock, I365_POWER)) /* only write if changed */
0519         indirect_write(sock, I365_POWER, reg);
0520
0521     /* Enable specific interrupt events */
0522
0523     reg = 0x00;
0524     if (state->csc_mask & SS_DETECT)
0525         reg |= I365_CSC_DETECT;
0526     if (state->flags & SS_IOCARD) {
0527         if (state->csc_mask & SS_STSCHG)
0528             reg |= I365_CSC_STSCHG;
0529     } else {
0530         if (state->csc_mask & SS_BATDEAD)
0531             reg |= I365_CSC_BVD1;
0532         if (state->csc_mask & SS_BATWARN)
0533             reg |= I365_CSC_BVD2;
0534         if (state->csc_mask & SS_READY)
0535             reg |= I365_CSC_READY;
0536
0537     }
0538
0539     /* now write the value and clear the (probably bogus) pending stuff
0540      * by doing a dummy read
0541      */
0542
0543     indirect_write(sock, I365_CSCINT, reg);
0544     (void)indirect_read(sock, I365_CSC);
0545
0546     return 0;
0547 }
0548
0549 static int i82092aa_set_io_map(struct pcmcia_socket *socket,
0550                    struct pccard_io_map *io)
0551 {
0552     struct socket_info *sock_info = container_of(socket, struct socket_info,
0553                              socket);
0554     unsigned int sock = sock_info->number;
0555     unsigned char map, ioctl;
0556
0557     map = io->map;
0558
0559     /* Check error conditions */
0560     if (map > 1)
0561         return -EINVAL;
0562
0563     if ((io->start > 0xffff) || (io->stop > 0xffff)
0564                  || (io->stop < io->start))
0565         return -EINVAL;
0566
0567     /* Turn off the window before changing anything */
0568     if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_IO(map))
0569         indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_IO(map));
0570
0571     /* write the new values */
0572     indirect_write16(sock, I365_IO(map)+I365_W_START, io->start);
0573     indirect_write16(sock, I365_IO(map)+I365_W_STOP, io->stop);
0574
0575     ioctl = indirect_read(sock, I365_IOCTL) & ~I365_IOCTL_MASK(map);
0576
0577     if (io->flags & (MAP_16BIT|MAP_AUTOSZ))
0578         ioctl |= I365_IOCTL_16BIT(map);
0579
0580     indirect_write(sock, I365_IOCTL, ioctl);
0581
0582     /* Turn the window back on if needed */
0583     if (io->flags & MAP_ACTIVE)
0584         indirect_setbit(sock, I365_ADDRWIN, I365_ENA_IO(map));
0585
0586     return 0;
0587 }
0588
0589 static int i82092aa_set_mem_map(struct pcmcia_socket *socket,
0590                 struct pccard_mem_map *mem)
0591 {
0592     struct socket_info *sock_info = container_of(socket, struct socket_info,
0593                              socket);
0594     unsigned int sock = sock_info->number;
0595     struct pci_bus_region region;
0596     unsigned short base, i;
0597     unsigned char map;
0598
0599     pcibios_resource_to_bus(sock_info->dev->bus, &region, mem->res);
0600
0601     map = mem->map;
0602     if (map > 4)
0603         return -EINVAL;
0604
0605     if ((mem->card_start > 0x3ffffff) || (region.start > region.end) ||
0606          (mem->speed > 1000)) {
0607         dev_err(&sock_info->dev->dev,
0608             "invalid mem map for socket %i: %llx to %llx with a start of %x\n",
0609             sock,
0610             (unsigned long long)region.start,
0611             (unsigned long long)region.end,
0612             mem->card_start);
0613         return -EINVAL;
0614     }
0615
0616     /* Turn off the window before changing anything */
0617     if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_MEM(map))
0618         indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_MEM(map));
0619
0620     /* write the start address */
0621     base = I365_MEM(map);
0622     i = (region.start >> 12) & 0x0fff;
0623     if (mem->flags & MAP_16BIT)
0624         i |= I365_MEM_16BIT;
0625     if (mem->flags & MAP_0WS)
0626         i |= I365_MEM_0WS;
0627     indirect_write16(sock, base+I365_W_START, i);
0628
0629     /* write the stop address */
0630
0631     i = (region.end >> 12) & 0x0fff;
0632     switch (to_cycles(mem->speed)) {
0633     case 0:
0634         break;
0635     case 1:
0636         i |= I365_MEM_WS0;
0637         break;
0638     case 2:
0639         i |= I365_MEM_WS1;
0640         break;
0641     default:
0642         i |= I365_MEM_WS1 | I365_MEM_WS0;
0643         break;
0644     }
0645
0646     indirect_write16(sock, base+I365_W_STOP, i);
0647
0648     /* card start */
0649
0650     i = ((mem->card_start - region.start) >> 12) & 0x3fff;
0651     if (mem->flags & MAP_WRPROT)
0652         i |= I365_MEM_WRPROT;
0653     if (mem->flags & MAP_ATTRIB)
0654         i |= I365_MEM_REG;
0655     indirect_write16(sock, base+I365_W_OFF, i);
0656
0657     /* Enable the window if necessary */
0658     if (mem->flags & MAP_ACTIVE)
0659         indirect_setbit(sock, I365_ADDRWIN, I365_ENA_MEM(map));
0660
0661     return 0;
0662 }
0663
0664 static int i82092aa_module_init(void)
0665 {
0666     return pci_register_driver(&i82092aa_pci_driver);
0667 }
0668
0669 static void i82092aa_module_exit(void)
0670 {
0671     pci_unregister_driver(&i82092aa_pci_driver);
0672     if (sockets[0].io_base > 0)
0673         release_region(sockets[0].io_base, 2);
0674 }
0675
0676 module_init(i82092aa_module_init);
0677 module_exit(i82092aa_module_exit);
0678