drivers/pcmcia/cirrus.h

0001 /*
0002  * cirrus.h 1.4 1999/10/25 20:03:34
0003  *
0004  * The contents of this file are subject to the Mozilla Public License
0005  * Version 1.1 (the "License"); you may not use this file except in
0006  * compliance with the License. You may obtain a copy of the License
0007  * at http://www.mozilla.org/MPL/
0008  *
0009  * Software distributed under the License is distributed on an "AS IS"
0010  * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
0011  * the License for the specific language governing rights and
0012  * limitations under the License.
0013  *
0014  * The initial developer of the original code is David A. Hinds
0015  * <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
0016  * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
0017  *
0018  * Alternatively, the contents of this file may be used under the
0019  * terms of the GNU General Public License version 2 (the "GPL"), in which
0020  * case the provisions of the GPL are applicable instead of the
0021  * above.  If you wish to allow the use of your version of this file
0022  * only under the terms of the GPL and not to allow others to use
0023  * your version of this file under the MPL, indicate your decision by
0024  * deleting the provisions above and replace them with the notice and
0025  * other provisions required by the GPL.  If you do not delete the
0026  * provisions above, a recipient may use your version of this file
0027  * under either the MPL or the GPL.
0028  */
0029
0030 #ifndef _LINUX_CIRRUS_H
0031 #define _LINUX_CIRRUS_H
0032
0033 #define PD67_MISC_CTL_1     0x16    /* Misc control 1 */
0034 #define PD67_FIFO_CTL       0x17    /* FIFO control */
0035 #define PD67_MISC_CTL_2     0x1E    /* Misc control 2 */
0036 #define PD67_CHIP_INFO      0x1f    /* Chip information */
0037 #define PD67_ATA_CTL        0x026   /* 6730: ATA control */
0038 #define PD67_EXT_INDEX      0x2e    /* Extension index */
0039 #define PD67_EXT_DATA       0x2f    /* Extension data */
0040
0041 /* PD6722 extension registers -- indexed in PD67_EXT_INDEX */
0042 #define PD67_DATA_MASK0     0x01    /* Data mask 0 */
0043 #define PD67_DATA_MASK1     0x02    /* Data mask 1 */
0044 #define PD67_DMA_CTL        0x03    /* DMA control */
0045
0046 /* PD6730 extension registers -- indexed in PD67_EXT_INDEX */
0047 #define PD67_EXT_CTL_1      0x03    /* Extension control 1 */
0048 #define PD67_MEM_PAGE(n)    ((n)+5) /* PCI window bits 31:24 */
0049 #define PD67_EXTERN_DATA    0x0a
0050 #define PD67_MISC_CTL_3     0x25
0051 #define PD67_SMB_PWR_CTL    0x26
0052
0053 /* I/O window address offset */
0054 #define PD67_IO_OFF(w)      (0x36+((w)<<1))
0055
0056 /* Timing register sets */
0057 #define PD67_TIME_SETUP(n)  (0x3a + 3*(n))
0058 #define PD67_TIME_CMD(n)    (0x3b + 3*(n))
0059 #define PD67_TIME_RECOV(n)  (0x3c + 3*(n))
0060
0061 /* Flags for PD67_MISC_CTL_1 */
0062 #define PD67_MC1_5V_DET     0x01    /* 5v detect */
0063 #define PD67_MC1_MEDIA_ENA  0x01    /* 6730: Multimedia enable */
0064 #define PD67_MC1_VCC_3V     0x02    /* 3.3v Vcc */
0065 #define PD67_MC1_PULSE_MGMT 0x04
0066 #define PD67_MC1_PULSE_IRQ  0x08
0067 #define PD67_MC1_SPKR_ENA   0x10
0068 #define PD67_MC1_INPACK_ENA 0x80
0069
0070 /* Flags for PD67_FIFO_CTL */
0071 #define PD67_FIFO_EMPTY     0x80
0072
0073 /* Flags for PD67_MISC_CTL_2 */
0074 #define PD67_MC2_FREQ_BYPASS    0x01
0075 #define PD67_MC2_DYNAMIC_MODE   0x02
0076 #define PD67_MC2_SUSPEND    0x04
0077 #define PD67_MC2_5V_CORE    0x08
0078 #define PD67_MC2_LED_ENA    0x10    /* IRQ 12 is LED enable */
0079 #define PD67_MC2_FAST_PCI   0x10    /* 6729: PCI bus > 25 MHz */
0080 #define PD67_MC2_3STATE_BIT7    0x20    /* Floppy change bit */
0081 #define PD67_MC2_DMA_MODE   0x40
0082 #define PD67_MC2_IRQ15_RI   0x80    /* IRQ 15 is ring enable */
0083
0084 /* Flags for PD67_CHIP_INFO */
0085 #define PD67_INFO_SLOTS     0x20    /* 0 = 1 slot, 1 = 2 slots */
0086 #define PD67_INFO_CHIP_ID   0xc0
0087 #define PD67_INFO_REV       0x1c
0088
0089 /* Fields in PD67_TIME_* registers */
0090 #define PD67_TIME_SCALE     0xc0
0091 #define PD67_TIME_SCALE_1   0x00
0092 #define PD67_TIME_SCALE_16  0x40
0093 #define PD67_TIME_SCALE_256 0x80
0094 #define PD67_TIME_SCALE_4096    0xc0
0095 #define PD67_TIME_MULT      0x3f
0096
0097 /* Fields in PD67_DMA_CTL */
0098 #define PD67_DMA_MODE       0xc0
0099 #define PD67_DMA_OFF        0x00
0100 #define PD67_DMA_DREQ_INPACK    0x40
0101 #define PD67_DMA_DREQ_WP    0x80
0102 #define PD67_DMA_DREQ_BVD2  0xc0
0103 #define PD67_DMA_PULLUP     0x20    /* Disable socket pullups? */
0104
0105 /* Fields in PD67_EXT_CTL_1 */
0106 #define PD67_EC1_VCC_PWR_LOCK   0x01
0107 #define PD67_EC1_AUTO_PWR_CLEAR 0x02
0108 #define PD67_EC1_LED_ENA    0x04
0109 #define PD67_EC1_INV_CARD_IRQ   0x08
0110 #define PD67_EC1_INV_MGMT_IRQ   0x10
0111 #define PD67_EC1_PULLUP_CTL 0x20
0112
0113 /* Fields in PD67_MISC_CTL_3 */
0114 #define PD67_MC3_IRQ_MASK   0x03
0115 #define PD67_MC3_IRQ_PCPCI  0x00
0116 #define PD67_MC3_IRQ_EXTERN 0x01
0117 #define PD67_MC3_IRQ_PCIWAY 0x02
0118 #define PD67_MC3_IRQ_PCI    0x03
0119 #define PD67_MC3_PWR_MASK   0x0c
0120 #define PD67_MC3_PWR_SERIAL 0x00
0121 #define PD67_MC3_PWR_TI2202 0x08
0122 #define PD67_MC3_PWR_SMB    0x0c
0123
0124 /* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */
0125
0126 /* PD6832 extension registers -- indexed in PD67_EXT_INDEX */
0127 #define PD68_EXT_CTL_2          0x0b
0128 #define PD68_PCI_SPACE          0x22
0129 #define PD68_PCCARD_SPACE       0x23
0130 #define PD68_WINDOW_TYPE        0x24
0131 #define PD68_EXT_CSC            0x2e
0132 #define PD68_MISC_CTL_4         0x2f
0133 #define PD68_MISC_CTL_5         0x30
0134 #define PD68_MISC_CTL_6         0x31
0135
0136 /* Extra flags in PD67_MISC_CTL_3 */
0137 #define PD68_MC3_HW_SUSP        0x10
0138 #define PD68_MC3_MM_EXPAND      0x40
0139 #define PD68_MC3_MM_ARM         0x80
0140
0141 /* Bridge Control Register */
0142 #define  PD6832_BCR_MGMT_IRQ_ENA    0x0800
0143
0144 /* Socket Number Register */
0145 #define PD6832_SOCKET_NUMBER        0x004c  /* 8 bit */
0146
0147 #endif /* _LINUX_CIRRUS_H */