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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * PCI VPD support
0004  *
0005  * Copyright (C) 2010 Broadcom Corporation.
0006  */
0007 
0008 #include <linux/pci.h>
0009 #include <linux/delay.h>
0010 #include <linux/export.h>
0011 #include <linux/sched/signal.h>
0012 #include <asm/unaligned.h>
0013 #include "pci.h"
0014 
0015 #define PCI_VPD_LRDT_TAG_SIZE       3
0016 #define PCI_VPD_SRDT_LEN_MASK       0x07
0017 #define PCI_VPD_SRDT_TAG_SIZE       1
0018 #define PCI_VPD_STIN_END        0x0f
0019 #define PCI_VPD_INFO_FLD_HDR_SIZE   3
0020 
0021 static u16 pci_vpd_lrdt_size(const u8 *lrdt)
0022 {
0023     return get_unaligned_le16(lrdt + 1);
0024 }
0025 
0026 static u8 pci_vpd_srdt_tag(const u8 *srdt)
0027 {
0028     return *srdt >> 3;
0029 }
0030 
0031 static u8 pci_vpd_srdt_size(const u8 *srdt)
0032 {
0033     return *srdt & PCI_VPD_SRDT_LEN_MASK;
0034 }
0035 
0036 static u8 pci_vpd_info_field_size(const u8 *info_field)
0037 {
0038     return info_field[2];
0039 }
0040 
0041 /* VPD access through PCI 2.2+ VPD capability */
0042 
0043 static struct pci_dev *pci_get_func0_dev(struct pci_dev *dev)
0044 {
0045     return pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
0046 }
0047 
0048 #define PCI_VPD_MAX_SIZE    (PCI_VPD_ADDR_MASK + 1)
0049 #define PCI_VPD_SZ_INVALID  UINT_MAX
0050 
0051 /**
0052  * pci_vpd_size - determine actual size of Vital Product Data
0053  * @dev:    pci device struct
0054  */
0055 static size_t pci_vpd_size(struct pci_dev *dev)
0056 {
0057     size_t off = 0, size;
0058     unsigned char tag, header[1+2]; /* 1 byte tag, 2 bytes length */
0059 
0060     while (pci_read_vpd_any(dev, off, 1, header) == 1) {
0061         size = 0;
0062 
0063         if (off == 0 && (header[0] == 0x00 || header[0] == 0xff))
0064             goto error;
0065 
0066         if (header[0] & PCI_VPD_LRDT) {
0067             /* Large Resource Data Type Tag */
0068             if (pci_read_vpd_any(dev, off + 1, 2, &header[1]) != 2) {
0069                 pci_warn(dev, "failed VPD read at offset %zu\n",
0070                      off + 1);
0071                 return off ?: PCI_VPD_SZ_INVALID;
0072             }
0073             size = pci_vpd_lrdt_size(header);
0074             if (off + size > PCI_VPD_MAX_SIZE)
0075                 goto error;
0076 
0077             off += PCI_VPD_LRDT_TAG_SIZE + size;
0078         } else {
0079             /* Short Resource Data Type Tag */
0080             tag = pci_vpd_srdt_tag(header);
0081             size = pci_vpd_srdt_size(header);
0082             if (off + size > PCI_VPD_MAX_SIZE)
0083                 goto error;
0084 
0085             off += PCI_VPD_SRDT_TAG_SIZE + size;
0086             if (tag == PCI_VPD_STIN_END)    /* End tag descriptor */
0087                 return off;
0088         }
0089     }
0090     return off;
0091 
0092 error:
0093     pci_info(dev, "invalid VPD tag %#04x (size %zu) at offset %zu%s\n",
0094          header[0], size, off, off == 0 ?
0095          "; assume missing optional EEPROM" : "");
0096     return off ?: PCI_VPD_SZ_INVALID;
0097 }
0098 
0099 static bool pci_vpd_available(struct pci_dev *dev, bool check_size)
0100 {
0101     struct pci_vpd *vpd = &dev->vpd;
0102 
0103     if (!vpd->cap)
0104         return false;
0105 
0106     if (vpd->len == 0 && check_size) {
0107         vpd->len = pci_vpd_size(dev);
0108         if (vpd->len == PCI_VPD_SZ_INVALID) {
0109             vpd->cap = 0;
0110             return false;
0111         }
0112     }
0113 
0114     return true;
0115 }
0116 
0117 /*
0118  * Wait for last operation to complete.
0119  * This code has to spin since there is no other notification from the PCI
0120  * hardware. Since the VPD is often implemented by serial attachment to an
0121  * EEPROM, it may take many milliseconds to complete.
0122  * @set: if true wait for flag to be set, else wait for it to be cleared
0123  *
0124  * Returns 0 on success, negative values indicate error.
0125  */
0126 static int pci_vpd_wait(struct pci_dev *dev, bool set)
0127 {
0128     struct pci_vpd *vpd = &dev->vpd;
0129     unsigned long timeout = jiffies + msecs_to_jiffies(125);
0130     unsigned long max_sleep = 16;
0131     u16 status;
0132     int ret;
0133 
0134     do {
0135         ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
0136                         &status);
0137         if (ret < 0)
0138             return ret;
0139 
0140         if (!!(status & PCI_VPD_ADDR_F) == set)
0141             return 0;
0142 
0143         if (time_after(jiffies, timeout))
0144             break;
0145 
0146         usleep_range(10, max_sleep);
0147         if (max_sleep < 1024)
0148             max_sleep *= 2;
0149     } while (true);
0150 
0151     pci_warn(dev, "VPD access failed.  This is likely a firmware bug on this device.  Contact the card vendor for a firmware update\n");
0152     return -ETIMEDOUT;
0153 }
0154 
0155 static ssize_t pci_vpd_read(struct pci_dev *dev, loff_t pos, size_t count,
0156                 void *arg, bool check_size)
0157 {
0158     struct pci_vpd *vpd = &dev->vpd;
0159     unsigned int max_len;
0160     int ret = 0;
0161     loff_t end = pos + count;
0162     u8 *buf = arg;
0163 
0164     if (!pci_vpd_available(dev, check_size))
0165         return -ENODEV;
0166 
0167     if (pos < 0)
0168         return -EINVAL;
0169 
0170     max_len = check_size ? vpd->len : PCI_VPD_MAX_SIZE;
0171 
0172     if (pos >= max_len)
0173         return 0;
0174 
0175     if (end > max_len) {
0176         end = max_len;
0177         count = end - pos;
0178     }
0179 
0180     if (mutex_lock_killable(&vpd->lock))
0181         return -EINTR;
0182 
0183     while (pos < end) {
0184         u32 val;
0185         unsigned int i, skip;
0186 
0187         if (fatal_signal_pending(current)) {
0188             ret = -EINTR;
0189             break;
0190         }
0191 
0192         ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
0193                          pos & ~3);
0194         if (ret < 0)
0195             break;
0196         ret = pci_vpd_wait(dev, true);
0197         if (ret < 0)
0198             break;
0199 
0200         ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
0201         if (ret < 0)
0202             break;
0203 
0204         skip = pos & 3;
0205         for (i = 0;  i < sizeof(u32); i++) {
0206             if (i >= skip) {
0207                 *buf++ = val;
0208                 if (++pos == end)
0209                     break;
0210             }
0211             val >>= 8;
0212         }
0213     }
0214 
0215     mutex_unlock(&vpd->lock);
0216     return ret ? ret : count;
0217 }
0218 
0219 static ssize_t pci_vpd_write(struct pci_dev *dev, loff_t pos, size_t count,
0220                  const void *arg, bool check_size)
0221 {
0222     struct pci_vpd *vpd = &dev->vpd;
0223     unsigned int max_len;
0224     const u8 *buf = arg;
0225     loff_t end = pos + count;
0226     int ret = 0;
0227 
0228     if (!pci_vpd_available(dev, check_size))
0229         return -ENODEV;
0230 
0231     if (pos < 0 || (pos & 3) || (count & 3))
0232         return -EINVAL;
0233 
0234     max_len = check_size ? vpd->len : PCI_VPD_MAX_SIZE;
0235 
0236     if (end > max_len)
0237         return -EINVAL;
0238 
0239     if (mutex_lock_killable(&vpd->lock))
0240         return -EINTR;
0241 
0242     while (pos < end) {
0243         ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA,
0244                           get_unaligned_le32(buf));
0245         if (ret < 0)
0246             break;
0247         ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
0248                          pos | PCI_VPD_ADDR_F);
0249         if (ret < 0)
0250             break;
0251 
0252         ret = pci_vpd_wait(dev, false);
0253         if (ret < 0)
0254             break;
0255 
0256         buf += sizeof(u32);
0257         pos += sizeof(u32);
0258     }
0259 
0260     mutex_unlock(&vpd->lock);
0261     return ret ? ret : count;
0262 }
0263 
0264 void pci_vpd_init(struct pci_dev *dev)
0265 {
0266     if (dev->vpd.len == PCI_VPD_SZ_INVALID)
0267         return;
0268 
0269     dev->vpd.cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
0270     mutex_init(&dev->vpd.lock);
0271 }
0272 
0273 static ssize_t vpd_read(struct file *filp, struct kobject *kobj,
0274             struct bin_attribute *bin_attr, char *buf, loff_t off,
0275             size_t count)
0276 {
0277     struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
0278 
0279     return pci_read_vpd(dev, off, count, buf);
0280 }
0281 
0282 static ssize_t vpd_write(struct file *filp, struct kobject *kobj,
0283              struct bin_attribute *bin_attr, char *buf, loff_t off,
0284              size_t count)
0285 {
0286     struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
0287 
0288     return pci_write_vpd(dev, off, count, buf);
0289 }
0290 static BIN_ATTR(vpd, 0600, vpd_read, vpd_write, 0);
0291 
0292 static struct bin_attribute *vpd_attrs[] = {
0293     &bin_attr_vpd,
0294     NULL,
0295 };
0296 
0297 static umode_t vpd_attr_is_visible(struct kobject *kobj,
0298                    struct bin_attribute *a, int n)
0299 {
0300     struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
0301 
0302     if (!pdev->vpd.cap)
0303         return 0;
0304 
0305     return a->attr.mode;
0306 }
0307 
0308 const struct attribute_group pci_dev_vpd_attr_group = {
0309     .bin_attrs = vpd_attrs,
0310     .is_bin_visible = vpd_attr_is_visible,
0311 };
0312 
0313 void *pci_vpd_alloc(struct pci_dev *dev, unsigned int *size)
0314 {
0315     unsigned int len;
0316     void *buf;
0317     int cnt;
0318 
0319     if (!pci_vpd_available(dev, true))
0320         return ERR_PTR(-ENODEV);
0321 
0322     len = dev->vpd.len;
0323     buf = kmalloc(len, GFP_KERNEL);
0324     if (!buf)
0325         return ERR_PTR(-ENOMEM);
0326 
0327     cnt = pci_read_vpd(dev, 0, len, buf);
0328     if (cnt != len) {
0329         kfree(buf);
0330         return ERR_PTR(-EIO);
0331     }
0332 
0333     if (size)
0334         *size = len;
0335 
0336     return buf;
0337 }
0338 EXPORT_SYMBOL_GPL(pci_vpd_alloc);
0339 
0340 static int pci_vpd_find_tag(const u8 *buf, unsigned int len, u8 rdt, unsigned int *size)
0341 {
0342     int i = 0;
0343 
0344     /* look for LRDT tags only, end tag is the only SRDT tag */
0345     while (i + PCI_VPD_LRDT_TAG_SIZE <= len && buf[i] & PCI_VPD_LRDT) {
0346         unsigned int lrdt_len = pci_vpd_lrdt_size(buf + i);
0347         u8 tag = buf[i];
0348 
0349         i += PCI_VPD_LRDT_TAG_SIZE;
0350         if (tag == rdt) {
0351             if (i + lrdt_len > len)
0352                 lrdt_len = len - i;
0353             if (size)
0354                 *size = lrdt_len;
0355             return i;
0356         }
0357 
0358         i += lrdt_len;
0359     }
0360 
0361     return -ENOENT;
0362 }
0363 
0364 int pci_vpd_find_id_string(const u8 *buf, unsigned int len, unsigned int *size)
0365 {
0366     return pci_vpd_find_tag(buf, len, PCI_VPD_LRDT_ID_STRING, size);
0367 }
0368 EXPORT_SYMBOL_GPL(pci_vpd_find_id_string);
0369 
0370 static int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
0371                   unsigned int len, const char *kw)
0372 {
0373     int i;
0374 
0375     for (i = off; i + PCI_VPD_INFO_FLD_HDR_SIZE <= off + len;) {
0376         if (buf[i + 0] == kw[0] &&
0377             buf[i + 1] == kw[1])
0378             return i;
0379 
0380         i += PCI_VPD_INFO_FLD_HDR_SIZE +
0381              pci_vpd_info_field_size(&buf[i]);
0382     }
0383 
0384     return -ENOENT;
0385 }
0386 
0387 static ssize_t __pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf,
0388                   bool check_size)
0389 {
0390     ssize_t ret;
0391 
0392     if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
0393         dev = pci_get_func0_dev(dev);
0394         if (!dev)
0395             return -ENODEV;
0396 
0397         ret = pci_vpd_read(dev, pos, count, buf, check_size);
0398         pci_dev_put(dev);
0399         return ret;
0400     }
0401 
0402     return pci_vpd_read(dev, pos, count, buf, check_size);
0403 }
0404 
0405 /**
0406  * pci_read_vpd - Read one entry from Vital Product Data
0407  * @dev:    PCI device struct
0408  * @pos:    offset in VPD space
0409  * @count:  number of bytes to read
0410  * @buf:    pointer to where to store result
0411  */
0412 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
0413 {
0414     return __pci_read_vpd(dev, pos, count, buf, true);
0415 }
0416 EXPORT_SYMBOL(pci_read_vpd);
0417 
0418 /* Same, but allow to access any address */
0419 ssize_t pci_read_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
0420 {
0421     return __pci_read_vpd(dev, pos, count, buf, false);
0422 }
0423 EXPORT_SYMBOL(pci_read_vpd_any);
0424 
0425 static ssize_t __pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count,
0426                    const void *buf, bool check_size)
0427 {
0428     ssize_t ret;
0429 
0430     if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0) {
0431         dev = pci_get_func0_dev(dev);
0432         if (!dev)
0433             return -ENODEV;
0434 
0435         ret = pci_vpd_write(dev, pos, count, buf, check_size);
0436         pci_dev_put(dev);
0437         return ret;
0438     }
0439 
0440     return pci_vpd_write(dev, pos, count, buf, check_size);
0441 }
0442 
0443 /**
0444  * pci_write_vpd - Write entry to Vital Product Data
0445  * @dev:    PCI device struct
0446  * @pos:    offset in VPD space
0447  * @count:  number of bytes to write
0448  * @buf:    buffer containing write data
0449  */
0450 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
0451 {
0452     return __pci_write_vpd(dev, pos, count, buf, true);
0453 }
0454 EXPORT_SYMBOL(pci_write_vpd);
0455 
0456 /* Same, but allow to access any address */
0457 ssize_t pci_write_vpd_any(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
0458 {
0459     return __pci_write_vpd(dev, pos, count, buf, false);
0460 }
0461 EXPORT_SYMBOL(pci_write_vpd_any);
0462 
0463 int pci_vpd_find_ro_info_keyword(const void *buf, unsigned int len,
0464                  const char *kw, unsigned int *size)
0465 {
0466     int ro_start, infokw_start;
0467     unsigned int ro_len, infokw_size;
0468 
0469     ro_start = pci_vpd_find_tag(buf, len, PCI_VPD_LRDT_RO_DATA, &ro_len);
0470     if (ro_start < 0)
0471         return ro_start;
0472 
0473     infokw_start = pci_vpd_find_info_keyword(buf, ro_start, ro_len, kw);
0474     if (infokw_start < 0)
0475         return infokw_start;
0476 
0477     infokw_size = pci_vpd_info_field_size(buf + infokw_start);
0478     infokw_start += PCI_VPD_INFO_FLD_HDR_SIZE;
0479 
0480     if (infokw_start + infokw_size > len)
0481         return -EINVAL;
0482 
0483     if (size)
0484         *size = infokw_size;
0485 
0486     return infokw_start;
0487 }
0488 EXPORT_SYMBOL_GPL(pci_vpd_find_ro_info_keyword);
0489 
0490 int pci_vpd_check_csum(const void *buf, unsigned int len)
0491 {
0492     const u8 *vpd = buf;
0493     unsigned int size;
0494     u8 csum = 0;
0495     int rv_start;
0496 
0497     rv_start = pci_vpd_find_ro_info_keyword(buf, len, PCI_VPD_RO_KEYWORD_CHKSUM, &size);
0498     if (rv_start == -ENOENT) /* no checksum in VPD */
0499         return 1;
0500     else if (rv_start < 0)
0501         return rv_start;
0502 
0503     if (!size)
0504         return -EINVAL;
0505 
0506     while (rv_start >= 0)
0507         csum += vpd[rv_start--];
0508 
0509     return csum ? -EILSEQ : 0;
0510 }
0511 EXPORT_SYMBOL_GPL(pci_vpd_check_csum);
0512 
0513 #ifdef CONFIG_PCI_QUIRKS
0514 /*
0515  * Quirk non-zero PCI functions to route VPD access through function 0 for
0516  * devices that share VPD resources between functions.  The functions are
0517  * expected to be identical devices.
0518  */
0519 static void quirk_f0_vpd_link(struct pci_dev *dev)
0520 {
0521     struct pci_dev *f0;
0522 
0523     if (!PCI_FUNC(dev->devfn))
0524         return;
0525 
0526     f0 = pci_get_func0_dev(dev);
0527     if (!f0)
0528         return;
0529 
0530     if (f0->vpd.cap && dev->class == f0->class &&
0531         dev->vendor == f0->vendor && dev->device == f0->device)
0532         dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
0533 
0534     pci_dev_put(f0);
0535 }
0536 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
0537                   PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
0538 
0539 /*
0540  * If a device follows the VPD format spec, the PCI core will not read or
0541  * write past the VPD End Tag.  But some vendors do not follow the VPD
0542  * format spec, so we can't tell how much data is safe to access.  Devices
0543  * may behave unpredictably if we access too much.  Blacklist these devices
0544  * so we don't touch VPD at all.
0545  */
0546 static void quirk_blacklist_vpd(struct pci_dev *dev)
0547 {
0548     dev->vpd.len = PCI_VPD_SZ_INVALID;
0549     pci_warn(dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
0550 }
0551 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd);
0552 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd);
0553 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd);
0554 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd);
0555 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd);
0556 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd);
0557 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd);
0558 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd);
0559 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd);
0560 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd);
0561 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
0562 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID, quirk_blacklist_vpd);
0563 /*
0564  * The Amazon Annapurna Labs 0x0031 device id is reused for other non Root Port
0565  * device types, so the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
0566  */
0567 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
0568                    PCI_CLASS_BRIDGE_PCI, 8, quirk_blacklist_vpd);
0569 
0570 static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
0571 {
0572     int chip = (dev->device & 0xf000) >> 12;
0573     int func = (dev->device & 0x0f00) >>  8;
0574     int prod = (dev->device & 0x00ff) >>  0;
0575 
0576     /*
0577      * If this is a T3-based adapter, there's a 1KB VPD area at offset
0578      * 0xc00 which contains the preferred VPD values.  If this is a T4 or
0579      * later based adapter, the special VPD is at offset 0x400 for the
0580      * Physical Functions (the SR-IOV Virtual Functions have no VPD
0581      * Capabilities).  The PCI VPD Access core routines will normally
0582      * compute the size of the VPD by parsing the VPD Data Structure at
0583      * offset 0x000.  This will result in silent failures when attempting
0584      * to accesses these other VPD areas which are beyond those computed
0585      * limits.
0586      */
0587     if (chip == 0x0 && prod >= 0x20)
0588         dev->vpd.len = 8192;
0589     else if (chip >= 0x4 && func < 0x8)
0590         dev->vpd.len = 2048;
0591 }
0592 
0593 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
0594              quirk_chelsio_extend_vpd);
0595 
0596 #endif
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