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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Support routines for initializing a PCI subsystem
0004  *
0005  * Extruded from code written by
0006  *      Dave Rusling (david.rusling@reo.mts.dec.com)
0007  *      David Mosberger (davidm@cs.arizona.edu)
0008  *  David Miller (davem@redhat.com)
0009  *
0010  * Fixed for multiple PCI buses, 1999 Andrea Arcangeli <andrea@suse.de>
0011  *
0012  * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
0013  *       Resource sorting
0014  */
0015 
0016 #include <linux/kernel.h>
0017 #include <linux/export.h>
0018 #include <linux/pci.h>
0019 #include <linux/errno.h>
0020 #include <linux/ioport.h>
0021 #include <linux/cache.h>
0022 #include <linux/slab.h>
0023 #include "pci.h"
0024 
0025 static void pci_std_update_resource(struct pci_dev *dev, int resno)
0026 {
0027     struct pci_bus_region region;
0028     bool disable;
0029     u16 cmd;
0030     u32 new, check, mask;
0031     int reg;
0032     struct resource *res = dev->resource + resno;
0033 
0034     /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */
0035     if (dev->is_virtfn)
0036         return;
0037 
0038     /*
0039      * Ignore resources for unimplemented BARs and unused resource slots
0040      * for 64 bit BARs.
0041      */
0042     if (!res->flags)
0043         return;
0044 
0045     if (res->flags & IORESOURCE_UNSET)
0046         return;
0047 
0048     /*
0049      * Ignore non-moveable resources.  This might be legacy resources for
0050      * which no functional BAR register exists or another important
0051      * system resource we shouldn't move around.
0052      */
0053     if (res->flags & IORESOURCE_PCI_FIXED)
0054         return;
0055 
0056     pcibios_resource_to_bus(dev->bus, &region, res);
0057     new = region.start;
0058 
0059     if (res->flags & IORESOURCE_IO) {
0060         mask = (u32)PCI_BASE_ADDRESS_IO_MASK;
0061         new |= res->flags & ~PCI_BASE_ADDRESS_IO_MASK;
0062     } else if (resno == PCI_ROM_RESOURCE) {
0063         mask = PCI_ROM_ADDRESS_MASK;
0064     } else {
0065         mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
0066         new |= res->flags & ~PCI_BASE_ADDRESS_MEM_MASK;
0067     }
0068 
0069     if (resno < PCI_ROM_RESOURCE) {
0070         reg = PCI_BASE_ADDRESS_0 + 4 * resno;
0071     } else if (resno == PCI_ROM_RESOURCE) {
0072 
0073         /*
0074          * Apparently some Matrox devices have ROM BARs that read
0075          * as zero when disabled, so don't update ROM BARs unless
0076          * they're enabled.  See
0077          * https://lore.kernel.org/r/43147B3D.1030309@vc.cvut.cz/
0078          * But we must update ROM BAR for buggy devices where even a
0079          * disabled ROM can conflict with other BARs.
0080          */
0081         if (!(res->flags & IORESOURCE_ROM_ENABLE) &&
0082             !dev->rom_bar_overlap)
0083             return;
0084 
0085         reg = dev->rom_base_reg;
0086         if (res->flags & IORESOURCE_ROM_ENABLE)
0087             new |= PCI_ROM_ADDRESS_ENABLE;
0088     } else
0089         return;
0090 
0091     /*
0092      * We can't update a 64-bit BAR atomically, so when possible,
0093      * disable decoding so that a half-updated BAR won't conflict
0094      * with another device.
0095      */
0096     disable = (res->flags & IORESOURCE_MEM_64) && !dev->mmio_always_on;
0097     if (disable) {
0098         pci_read_config_word(dev, PCI_COMMAND, &cmd);
0099         pci_write_config_word(dev, PCI_COMMAND,
0100                       cmd & ~PCI_COMMAND_MEMORY);
0101     }
0102 
0103     pci_write_config_dword(dev, reg, new);
0104     pci_read_config_dword(dev, reg, &check);
0105 
0106     if ((new ^ check) & mask) {
0107         pci_err(dev, "BAR %d: error updating (%#08x != %#08x)\n",
0108             resno, new, check);
0109     }
0110 
0111     if (res->flags & IORESOURCE_MEM_64) {
0112         new = region.start >> 16 >> 16;
0113         pci_write_config_dword(dev, reg + 4, new);
0114         pci_read_config_dword(dev, reg + 4, &check);
0115         if (check != new) {
0116             pci_err(dev, "BAR %d: error updating (high %#08x != %#08x)\n",
0117                 resno, new, check);
0118         }
0119     }
0120 
0121     if (disable)
0122         pci_write_config_word(dev, PCI_COMMAND, cmd);
0123 }
0124 
0125 void pci_update_resource(struct pci_dev *dev, int resno)
0126 {
0127     if (resno <= PCI_ROM_RESOURCE)
0128         pci_std_update_resource(dev, resno);
0129 #ifdef CONFIG_PCI_IOV
0130     else if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
0131         pci_iov_update_resource(dev, resno);
0132 #endif
0133 }
0134 
0135 int pci_claim_resource(struct pci_dev *dev, int resource)
0136 {
0137     struct resource *res = &dev->resource[resource];
0138     struct resource *root, *conflict;
0139 
0140     if (res->flags & IORESOURCE_UNSET) {
0141         pci_info(dev, "can't claim BAR %d %pR: no address assigned\n",
0142              resource, res);
0143         return -EINVAL;
0144     }
0145 
0146     /*
0147      * If we have a shadow copy in RAM, the PCI device doesn't respond
0148      * to the shadow range, so we don't need to claim it, and upstream
0149      * bridges don't need to route the range to the device.
0150      */
0151     if (res->flags & IORESOURCE_ROM_SHADOW)
0152         return 0;
0153 
0154     root = pci_find_parent_resource(dev, res);
0155     if (!root) {
0156         pci_info(dev, "can't claim BAR %d %pR: no compatible bridge window\n",
0157              resource, res);
0158         res->flags |= IORESOURCE_UNSET;
0159         return -EINVAL;
0160     }
0161 
0162     conflict = request_resource_conflict(root, res);
0163     if (conflict) {
0164         pci_info(dev, "can't claim BAR %d %pR: address conflict with %s %pR\n",
0165              resource, res, conflict->name, conflict);
0166         res->flags |= IORESOURCE_UNSET;
0167         return -EBUSY;
0168     }
0169 
0170     return 0;
0171 }
0172 EXPORT_SYMBOL(pci_claim_resource);
0173 
0174 void pci_disable_bridge_window(struct pci_dev *dev)
0175 {
0176     /* MMIO Base/Limit */
0177     pci_write_config_dword(dev, PCI_MEMORY_BASE, 0x0000fff0);
0178 
0179     /* Prefetchable MMIO Base/Limit */
0180     pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
0181     pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, 0x0000fff0);
0182     pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, 0xffffffff);
0183 }
0184 
0185 /*
0186  * Generic function that returns a value indicating that the device's
0187  * original BIOS BAR address was not saved and so is not available for
0188  * reinstatement.
0189  *
0190  * Can be over-ridden by architecture specific code that implements
0191  * reinstatement functionality rather than leaving it disabled when
0192  * normal allocation attempts fail.
0193  */
0194 resource_size_t __weak pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx)
0195 {
0196     return 0;
0197 }
0198 
0199 static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
0200         int resno, resource_size_t size)
0201 {
0202     struct resource *root, *conflict;
0203     resource_size_t fw_addr, start, end;
0204 
0205     fw_addr = pcibios_retrieve_fw_addr(dev, resno);
0206     if (!fw_addr)
0207         return -ENOMEM;
0208 
0209     start = res->start;
0210     end = res->end;
0211     res->start = fw_addr;
0212     res->end = res->start + size - 1;
0213     res->flags &= ~IORESOURCE_UNSET;
0214 
0215     root = pci_find_parent_resource(dev, res);
0216     if (!root) {
0217         if (res->flags & IORESOURCE_IO)
0218             root = &ioport_resource;
0219         else
0220             root = &iomem_resource;
0221     }
0222 
0223     pci_info(dev, "BAR %d: trying firmware assignment %pR\n",
0224          resno, res);
0225     conflict = request_resource_conflict(root, res);
0226     if (conflict) {
0227         pci_info(dev, "BAR %d: %pR conflicts with %s %pR\n",
0228              resno, res, conflict->name, conflict);
0229         res->start = start;
0230         res->end = end;
0231         res->flags |= IORESOURCE_UNSET;
0232         return -EBUSY;
0233     }
0234     return 0;
0235 }
0236 
0237 /*
0238  * We don't have to worry about legacy ISA devices, so nothing to do here.
0239  * This is marked as __weak because multiple architectures define it; it should
0240  * eventually go away.
0241  */
0242 resource_size_t __weak pcibios_align_resource(void *data,
0243                           const struct resource *res,
0244                           resource_size_t size,
0245                           resource_size_t align)
0246 {
0247        return res->start;
0248 }
0249 
0250 static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
0251         int resno, resource_size_t size, resource_size_t align)
0252 {
0253     struct resource *res = dev->resource + resno;
0254     resource_size_t min;
0255     int ret;
0256 
0257     min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
0258 
0259     /*
0260      * First, try exact prefetching match.  Even if a 64-bit
0261      * prefetchable bridge window is below 4GB, we can't put a 32-bit
0262      * prefetchable resource in it because pbus_size_mem() assumes a
0263      * 64-bit window will contain no 32-bit resources.  If we assign
0264      * things differently than they were sized, not everything will fit.
0265      */
0266     ret = pci_bus_alloc_resource(bus, res, size, align, min,
0267                      IORESOURCE_PREFETCH | IORESOURCE_MEM_64,
0268                      pcibios_align_resource, dev);
0269     if (ret == 0)
0270         return 0;
0271 
0272     /*
0273      * If the prefetchable window is only 32 bits wide, we can put
0274      * 64-bit prefetchable resources in it.
0275      */
0276     if ((res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) ==
0277          (IORESOURCE_PREFETCH | IORESOURCE_MEM_64)) {
0278         ret = pci_bus_alloc_resource(bus, res, size, align, min,
0279                          IORESOURCE_PREFETCH,
0280                          pcibios_align_resource, dev);
0281         if (ret == 0)
0282             return 0;
0283     }
0284 
0285     /*
0286      * If we didn't find a better match, we can put any memory resource
0287      * in a non-prefetchable window.  If this resource is 32 bits and
0288      * non-prefetchable, the first call already tried the only possibility
0289      * so we don't need to try again.
0290      */
0291     if (res->flags & (IORESOURCE_PREFETCH | IORESOURCE_MEM_64))
0292         ret = pci_bus_alloc_resource(bus, res, size, align, min, 0,
0293                          pcibios_align_resource, dev);
0294 
0295     return ret;
0296 }
0297 
0298 static int _pci_assign_resource(struct pci_dev *dev, int resno,
0299                 resource_size_t size, resource_size_t min_align)
0300 {
0301     struct pci_bus *bus;
0302     int ret;
0303 
0304     bus = dev->bus;
0305     while ((ret = __pci_assign_resource(bus, dev, resno, size, min_align))) {
0306         if (!bus->parent || !bus->self->transparent)
0307             break;
0308         bus = bus->parent;
0309     }
0310 
0311     return ret;
0312 }
0313 
0314 int pci_assign_resource(struct pci_dev *dev, int resno)
0315 {
0316     struct resource *res = dev->resource + resno;
0317     resource_size_t align, size;
0318     int ret;
0319 
0320     if (res->flags & IORESOURCE_PCI_FIXED)
0321         return 0;
0322 
0323     res->flags |= IORESOURCE_UNSET;
0324     align = pci_resource_alignment(dev, res);
0325     if (!align) {
0326         pci_info(dev, "BAR %d: can't assign %pR (bogus alignment)\n",
0327              resno, res);
0328         return -EINVAL;
0329     }
0330 
0331     size = resource_size(res);
0332     ret = _pci_assign_resource(dev, resno, size, align);
0333 
0334     /*
0335      * If we failed to assign anything, let's try the address
0336      * where firmware left it.  That at least has a chance of
0337      * working, which is better than just leaving it disabled.
0338      */
0339     if (ret < 0) {
0340         pci_info(dev, "BAR %d: no space for %pR\n", resno, res);
0341         ret = pci_revert_fw_address(res, dev, resno, size);
0342     }
0343 
0344     if (ret < 0) {
0345         pci_info(dev, "BAR %d: failed to assign %pR\n", resno, res);
0346         return ret;
0347     }
0348 
0349     res->flags &= ~IORESOURCE_UNSET;
0350     res->flags &= ~IORESOURCE_STARTALIGN;
0351     pci_info(dev, "BAR %d: assigned %pR\n", resno, res);
0352     if (resno < PCI_BRIDGE_RESOURCES)
0353         pci_update_resource(dev, resno);
0354 
0355     return 0;
0356 }
0357 EXPORT_SYMBOL(pci_assign_resource);
0358 
0359 int pci_reassign_resource(struct pci_dev *dev, int resno, resource_size_t addsize,
0360             resource_size_t min_align)
0361 {
0362     struct resource *res = dev->resource + resno;
0363     unsigned long flags;
0364     resource_size_t new_size;
0365     int ret;
0366 
0367     if (res->flags & IORESOURCE_PCI_FIXED)
0368         return 0;
0369 
0370     flags = res->flags;
0371     res->flags |= IORESOURCE_UNSET;
0372     if (!res->parent) {
0373         pci_info(dev, "BAR %d: can't reassign an unassigned resource %pR\n",
0374              resno, res);
0375         return -EINVAL;
0376     }
0377 
0378     /* already aligned with min_align */
0379     new_size = resource_size(res) + addsize;
0380     ret = _pci_assign_resource(dev, resno, new_size, min_align);
0381     if (ret) {
0382         res->flags = flags;
0383         pci_info(dev, "BAR %d: %pR (failed to expand by %#llx)\n",
0384              resno, res, (unsigned long long) addsize);
0385         return ret;
0386     }
0387 
0388     res->flags &= ~IORESOURCE_UNSET;
0389     res->flags &= ~IORESOURCE_STARTALIGN;
0390     pci_info(dev, "BAR %d: reassigned %pR (expanded by %#llx)\n",
0391          resno, res, (unsigned long long) addsize);
0392     if (resno < PCI_BRIDGE_RESOURCES)
0393         pci_update_resource(dev, resno);
0394 
0395     return 0;
0396 }
0397 
0398 void pci_release_resource(struct pci_dev *dev, int resno)
0399 {
0400     struct resource *res = dev->resource + resno;
0401 
0402     pci_info(dev, "BAR %d: releasing %pR\n", resno, res);
0403 
0404     if (!res->parent)
0405         return;
0406 
0407     release_resource(res);
0408     res->end = resource_size(res) - 1;
0409     res->start = 0;
0410     res->flags |= IORESOURCE_UNSET;
0411 }
0412 EXPORT_SYMBOL(pci_release_resource);
0413 
0414 int pci_resize_resource(struct pci_dev *dev, int resno, int size)
0415 {
0416     struct resource *res = dev->resource + resno;
0417     struct pci_host_bridge *host;
0418     int old, ret;
0419     u32 sizes;
0420     u16 cmd;
0421 
0422     /* Check if we must preserve the firmware's resource assignment */
0423     host = pci_find_host_bridge(dev->bus);
0424     if (host->preserve_config)
0425         return -ENOTSUPP;
0426 
0427     /* Make sure the resource isn't assigned before resizing it. */
0428     if (!(res->flags & IORESOURCE_UNSET))
0429         return -EBUSY;
0430 
0431     pci_read_config_word(dev, PCI_COMMAND, &cmd);
0432     if (cmd & PCI_COMMAND_MEMORY)
0433         return -EBUSY;
0434 
0435     sizes = pci_rebar_get_possible_sizes(dev, resno);
0436     if (!sizes)
0437         return -ENOTSUPP;
0438 
0439     if (!(sizes & BIT(size)))
0440         return -EINVAL;
0441 
0442     old = pci_rebar_get_current_size(dev, resno);
0443     if (old < 0)
0444         return old;
0445 
0446     ret = pci_rebar_set_size(dev, resno, size);
0447     if (ret)
0448         return ret;
0449 
0450     res->end = res->start + pci_rebar_size_to_bytes(size) - 1;
0451 
0452     /* Check if the new config works by trying to assign everything. */
0453     if (dev->bus->self) {
0454         ret = pci_reassign_bridge_resources(dev->bus->self, res->flags);
0455         if (ret)
0456             goto error_resize;
0457     }
0458     return 0;
0459 
0460 error_resize:
0461     pci_rebar_set_size(dev, resno, old);
0462     res->end = res->start + pci_rebar_size_to_bytes(old) - 1;
0463     return ret;
0464 }
0465 EXPORT_SYMBOL(pci_resize_resource);
0466 
0467 int pci_enable_resources(struct pci_dev *dev, int mask)
0468 {
0469     u16 cmd, old_cmd;
0470     int i;
0471     struct resource *r;
0472 
0473     pci_read_config_word(dev, PCI_COMMAND, &cmd);
0474     old_cmd = cmd;
0475 
0476     for (i = 0; i < PCI_NUM_RESOURCES; i++) {
0477         if (!(mask & (1 << i)))
0478             continue;
0479 
0480         r = &dev->resource[i];
0481 
0482         if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
0483             continue;
0484         if ((i == PCI_ROM_RESOURCE) &&
0485                 (!(r->flags & IORESOURCE_ROM_ENABLE)))
0486             continue;
0487 
0488         if (r->flags & IORESOURCE_UNSET) {
0489             pci_err(dev, "can't enable device: BAR %d %pR not assigned\n",
0490                 i, r);
0491             return -EINVAL;
0492         }
0493 
0494         if (!r->parent) {
0495             pci_err(dev, "can't enable device: BAR %d %pR not claimed\n",
0496                 i, r);
0497             return -EINVAL;
0498         }
0499 
0500         if (r->flags & IORESOURCE_IO)
0501             cmd |= PCI_COMMAND_IO;
0502         if (r->flags & IORESOURCE_MEM)
0503             cmd |= PCI_COMMAND_MEMORY;
0504     }
0505 
0506     if (cmd != old_cmd) {
0507         pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
0508         pci_write_config_word(dev, PCI_COMMAND, cmd);
0509     }
0510     return 0;
0511 }
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