drivers/pci/proc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Procfs interface for the PCI bus
0004  *
0005  * Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
0006  */
0007
0008 #include <linux/init.h>
0009 #include <linux/pci.h>
0010 #include <linux/slab.h>
0011 #include <linux/module.h>
0012 #include <linux/proc_fs.h>
0013 #include <linux/seq_file.h>
0014 #include <linux/capability.h>
0015 #include <linux/uaccess.h>
0016 #include <linux/security.h>
0017 #include <asm/byteorder.h>
0018 #include "pci.h"
0019
0020 static int proc_initialized;    /* = 0 */
0021
0022 static loff_t proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
0023 {
0024     struct pci_dev *dev = pde_data(file_inode(file));
0025     return fixed_size_llseek(file, off, whence, dev->cfg_size);
0026 }
0027
0028 static ssize_t proc_bus_pci_read(struct file *file, char __user *buf,
0029                  size_t nbytes, loff_t *ppos)
0030 {
0031     struct pci_dev *dev = pde_data(file_inode(file));
0032     unsigned int pos = *ppos;
0033     unsigned int cnt, size;
0034
0035     /*
0036      * Normal users can read only the standardized portion of the
0037      * configuration space as several chips lock up when trying to read
0038      * undefined locations (think of Intel PIIX4 as a typical example).
0039      */
0040
0041     if (capable(CAP_SYS_ADMIN))
0042         size = dev->cfg_size;
0043     else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
0044         size = 128;
0045     else
0046         size = 64;
0047
0048     if (pos >= size)
0049         return 0;
0050     if (nbytes >= size)
0051         nbytes = size;
0052     if (pos + nbytes > size)
0053         nbytes = size - pos;
0054     cnt = nbytes;
0055
0056     if (!access_ok(buf, cnt))
0057         return -EINVAL;
0058
0059     pci_config_pm_runtime_get(dev);
0060
0061     if ((pos & 1) && cnt) {
0062         unsigned char val;
0063         pci_user_read_config_byte(dev, pos, &val);
0064         __put_user(val, buf);
0065         buf++;
0066         pos++;
0067         cnt--;
0068     }
0069
0070     if ((pos & 3) && cnt > 2) {
0071         unsigned short val;
0072         pci_user_read_config_word(dev, pos, &val);
0073         __put_user(cpu_to_le16(val), (__le16 __user *) buf);
0074         buf += 2;
0075         pos += 2;
0076         cnt -= 2;
0077     }
0078
0079     while (cnt >= 4) {
0080         unsigned int val;
0081         pci_user_read_config_dword(dev, pos, &val);
0082         __put_user(cpu_to_le32(val), (__le32 __user *) buf);
0083         buf += 4;
0084         pos += 4;
0085         cnt -= 4;
0086         cond_resched();
0087     }
0088
0089     if (cnt >= 2) {
0090         unsigned short val;
0091         pci_user_read_config_word(dev, pos, &val);
0092         __put_user(cpu_to_le16(val), (__le16 __user *) buf);
0093         buf += 2;
0094         pos += 2;
0095         cnt -= 2;
0096     }
0097
0098     if (cnt) {
0099         unsigned char val;
0100         pci_user_read_config_byte(dev, pos, &val);
0101         __put_user(val, buf);
0102         pos++;
0103     }
0104
0105     pci_config_pm_runtime_put(dev);
0106
0107     *ppos = pos;
0108     return nbytes;
0109 }
0110
0111 static ssize_t proc_bus_pci_write(struct file *file, const char __user *buf,
0112                   size_t nbytes, loff_t *ppos)
0113 {
0114     struct inode *ino = file_inode(file);
0115     struct pci_dev *dev = pde_data(ino);
0116     int pos = *ppos;
0117     int size = dev->cfg_size;
0118     int cnt, ret;
0119
0120     ret = security_locked_down(LOCKDOWN_PCI_ACCESS);
0121     if (ret)
0122         return ret;
0123
0124     if (pos >= size)
0125         return 0;
0126     if (nbytes >= size)
0127         nbytes = size;
0128     if (pos + nbytes > size)
0129         nbytes = size - pos;
0130     cnt = nbytes;
0131
0132     if (!access_ok(buf, cnt))
0133         return -EINVAL;
0134
0135     pci_config_pm_runtime_get(dev);
0136
0137     if ((pos & 1) && cnt) {
0138         unsigned char val;
0139         __get_user(val, buf);
0140         pci_user_write_config_byte(dev, pos, val);
0141         buf++;
0142         pos++;
0143         cnt--;
0144     }
0145
0146     if ((pos & 3) && cnt > 2) {
0147         __le16 val;
0148         __get_user(val, (__le16 __user *) buf);
0149         pci_user_write_config_word(dev, pos, le16_to_cpu(val));
0150         buf += 2;
0151         pos += 2;
0152         cnt -= 2;
0153     }
0154
0155     while (cnt >= 4) {
0156         __le32 val;
0157         __get_user(val, (__le32 __user *) buf);
0158         pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
0159         buf += 4;
0160         pos += 4;
0161         cnt -= 4;
0162     }
0163
0164     if (cnt >= 2) {
0165         __le16 val;
0166         __get_user(val, (__le16 __user *) buf);
0167         pci_user_write_config_word(dev, pos, le16_to_cpu(val));
0168         buf += 2;
0169         pos += 2;
0170         cnt -= 2;
0171     }
0172
0173     if (cnt) {
0174         unsigned char val;
0175         __get_user(val, buf);
0176         pci_user_write_config_byte(dev, pos, val);
0177         pos++;
0178     }
0179
0180     pci_config_pm_runtime_put(dev);
0181
0182     *ppos = pos;
0183     i_size_write(ino, dev->cfg_size);
0184     return nbytes;
0185 }
0186
0187 #ifdef HAVE_PCI_MMAP
0188 struct pci_filp_private {
0189     enum pci_mmap_state mmap_state;
0190     int write_combine;
0191 };
0192 #endif /* HAVE_PCI_MMAP */
0193
0194 static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
0195                    unsigned long arg)
0196 {
0197     struct pci_dev *dev = pde_data(file_inode(file));
0198 #ifdef HAVE_PCI_MMAP
0199     struct pci_filp_private *fpriv = file->private_data;
0200 #endif /* HAVE_PCI_MMAP */
0201     int ret = 0;
0202
0203     ret = security_locked_down(LOCKDOWN_PCI_ACCESS);
0204     if (ret)
0205         return ret;
0206
0207     switch (cmd) {
0208     case PCIIOC_CONTROLLER:
0209         ret = pci_domain_nr(dev->bus);
0210         break;
0211
0212 #ifdef HAVE_PCI_MMAP
0213     case PCIIOC_MMAP_IS_IO:
0214         if (!arch_can_pci_mmap_io())
0215             return -EINVAL;
0216         fpriv->mmap_state = pci_mmap_io;
0217         break;
0218
0219     case PCIIOC_MMAP_IS_MEM:
0220         fpriv->mmap_state = pci_mmap_mem;
0221         break;
0222
0223     case PCIIOC_WRITE_COMBINE:
0224         if (arch_can_pci_mmap_wc()) {
0225             if (arg)
0226                 fpriv->write_combine = 1;
0227             else
0228                 fpriv->write_combine = 0;
0229             break;
0230         }
0231         /* If arch decided it can't, fall through... */
0232         fallthrough;
0233 #endif /* HAVE_PCI_MMAP */
0234     default:
0235         ret = -EINVAL;
0236         break;
0237     }
0238
0239     return ret;
0240 }
0241
0242 #ifdef HAVE_PCI_MMAP
0243 static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma)
0244 {
0245     struct pci_dev *dev = pde_data(file_inode(file));
0246     struct pci_filp_private *fpriv = file->private_data;
0247     resource_size_t start, end;
0248     int i, ret, write_combine = 0, res_bit = IORESOURCE_MEM;
0249
0250     if (!capable(CAP_SYS_RAWIO) ||
0251         security_locked_down(LOCKDOWN_PCI_ACCESS))
0252         return -EPERM;
0253
0254     if (fpriv->mmap_state == pci_mmap_io) {
0255         if (!arch_can_pci_mmap_io())
0256             return -EINVAL;
0257         res_bit = IORESOURCE_IO;
0258     }
0259
0260     /* Make sure the caller is mapping a real resource for this device */
0261     for (i = 0; i < PCI_STD_NUM_BARS; i++) {
0262         if (dev->resource[i].flags & res_bit &&
0263             pci_mmap_fits(dev, i, vma,  PCI_MMAP_PROCFS))
0264             break;
0265     }
0266
0267     if (i >= PCI_STD_NUM_BARS)
0268         return -ENODEV;
0269
0270     if (fpriv->mmap_state == pci_mmap_mem &&
0271         fpriv->write_combine) {
0272         if (dev->resource[i].flags & IORESOURCE_PREFETCH)
0273             write_combine = 1;
0274         else
0275             return -EINVAL;
0276     }
0277
0278     if (dev->resource[i].flags & IORESOURCE_MEM &&
0279         iomem_is_exclusive(dev->resource[i].start))
0280         return -EINVAL;
0281
0282     pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
0283
0284     /* Adjust vm_pgoff to be the offset within the resource */
0285     vma->vm_pgoff -= start >> PAGE_SHIFT;
0286     ret = pci_mmap_resource_range(dev, i, vma,
0287                   fpriv->mmap_state, write_combine);
0288     if (ret < 0)
0289         return ret;
0290
0291     return 0;
0292 }
0293
0294 static int proc_bus_pci_open(struct inode *inode, struct file *file)
0295 {
0296     struct pci_filp_private *fpriv = kmalloc(sizeof(*fpriv), GFP_KERNEL);
0297
0298     if (!fpriv)
0299         return -ENOMEM;
0300
0301     fpriv->mmap_state = pci_mmap_io;
0302     fpriv->write_combine = 0;
0303
0304     file->private_data = fpriv;
0305     file->f_mapping = iomem_get_mapping();
0306
0307     return 0;
0308 }
0309
0310 static int proc_bus_pci_release(struct inode *inode, struct file *file)
0311 {
0312     kfree(file->private_data);
0313     file->private_data = NULL;
0314
0315     return 0;
0316 }
0317 #endif /* HAVE_PCI_MMAP */
0318
0319 static const struct proc_ops proc_bus_pci_ops = {
0320     .proc_lseek = proc_bus_pci_lseek,
0321     .proc_read  = proc_bus_pci_read,
0322     .proc_write = proc_bus_pci_write,
0323     .proc_ioctl = proc_bus_pci_ioctl,
0324 #ifdef CONFIG_COMPAT
0325     .proc_compat_ioctl = proc_bus_pci_ioctl,
0326 #endif
0327 #ifdef HAVE_PCI_MMAP
0328     .proc_open  = proc_bus_pci_open,
0329     .proc_release   = proc_bus_pci_release,
0330     .proc_mmap  = proc_bus_pci_mmap,
0331 #ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
0332     .proc_get_unmapped_area = get_pci_unmapped_area,
0333 #endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
0334 #endif /* HAVE_PCI_MMAP */
0335 };
0336
0337 /* iterator */
0338 static void *pci_seq_start(struct seq_file *m, loff_t *pos)
0339 {
0340     struct pci_dev *dev = NULL;
0341     loff_t n = *pos;
0342
0343     for_each_pci_dev(dev) {
0344         if (!n--)
0345             break;
0346     }
0347     return dev;
0348 }
0349
0350 static void *pci_seq_next(struct seq_file *m, void *v, loff_t *pos)
0351 {
0352     struct pci_dev *dev = v;
0353
0354     (*pos)++;
0355     dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
0356     return dev;
0357 }
0358
0359 static void pci_seq_stop(struct seq_file *m, void *v)
0360 {
0361     if (v) {
0362         struct pci_dev *dev = v;
0363         pci_dev_put(dev);
0364     }
0365 }
0366
0367 static int show_device(struct seq_file *m, void *v)
0368 {
0369     const struct pci_dev *dev = v;
0370     const struct pci_driver *drv;
0371     int i;
0372
0373     if (dev == NULL)
0374         return 0;
0375
0376     drv = pci_dev_driver(dev);
0377     seq_printf(m, "%02x%02x\t%04x%04x\t%x",
0378             dev->bus->number,
0379             dev->devfn,
0380             dev->vendor,
0381             dev->device,
0382             dev->irq);
0383
0384     /* only print standard and ROM resources to preserve compatibility */
0385     for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
0386         resource_size_t start, end;
0387         pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
0388         seq_printf(m, "\t%16llx",
0389             (unsigned long long)(start |
0390             (dev->resource[i].flags & PCI_REGION_FLAG_MASK)));
0391     }
0392     for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
0393         resource_size_t start, end;
0394         pci_resource_to_user(dev, i, &dev->resource[i], &start, &end);
0395         seq_printf(m, "\t%16llx",
0396             dev->resource[i].start < dev->resource[i].end ?
0397             (unsigned long long)(end - start) + 1 : 0);
0398     }
0399     seq_putc(m, '\t');
0400     if (drv)
0401         seq_puts(m, drv->name);
0402     seq_putc(m, '\n');
0403     return 0;
0404 }
0405
0406 static const struct seq_operations proc_bus_pci_devices_op = {
0407     .start  = pci_seq_start,
0408     .next   = pci_seq_next,
0409     .stop   = pci_seq_stop,
0410     .show   = show_device
0411 };
0412
0413 static struct proc_dir_entry *proc_bus_pci_dir;
0414
0415 int pci_proc_attach_device(struct pci_dev *dev)
0416 {
0417     struct pci_bus *bus = dev->bus;
0418     struct proc_dir_entry *e;
0419     char name[16];
0420
0421     if (!proc_initialized)
0422         return -EACCES;
0423
0424     if (!bus->procdir) {
0425         if (pci_proc_domain(bus)) {
0426             sprintf(name, "%04x:%02x", pci_domain_nr(bus),
0427                     bus->number);
0428         } else {
0429             sprintf(name, "%02x", bus->number);
0430         }
0431         bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
0432         if (!bus->procdir)
0433             return -ENOMEM;
0434     }
0435
0436     sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
0437     e = proc_create_data(name, S_IFREG | S_IRUGO | S_IWUSR, bus->procdir,
0438                  &proc_bus_pci_ops, dev);
0439     if (!e)
0440         return -ENOMEM;
0441     proc_set_size(e, dev->cfg_size);
0442     dev->procent = e;
0443
0444     return 0;
0445 }
0446
0447 int pci_proc_detach_device(struct pci_dev *dev)
0448 {
0449     proc_remove(dev->procent);
0450     dev->procent = NULL;
0451     return 0;
0452 }
0453
0454 int pci_proc_detach_bus(struct pci_bus *bus)
0455 {
0456     proc_remove(bus->procdir);
0457     return 0;
0458 }
0459
0460 static int __init pci_proc_init(void)
0461 {
0462     struct pci_dev *dev = NULL;
0463     proc_bus_pci_dir = proc_mkdir("bus/pci", NULL);
0464     proc_create_seq("devices", 0, proc_bus_pci_dir,
0465             &proc_bus_pci_devices_op);
0466     proc_initialized = 1;
0467     for_each_pci_dev(dev)
0468         pci_proc_attach_device(dev);
0469
0470     return 0;
0471 }
0472 device_initcall(pci_proc_init);