pci/pcie/portdrv.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Purpose: PCI Express Port Bus Driver's Internal Data Structures
0004  *
0005  * Copyright (C) 2004 Intel
0006  * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
0007  */
0008
0009 #ifndef _PORTDRV_H_
0010 #define _PORTDRV_H_
0011
0012 #include <linux/compiler.h>
0013
0014 /* Service Type */
0015 #define PCIE_PORT_SERVICE_PME_SHIFT 0   /* Power Management Event */
0016 #define PCIE_PORT_SERVICE_PME       (1 << PCIE_PORT_SERVICE_PME_SHIFT)
0017 #define PCIE_PORT_SERVICE_AER_SHIFT 1   /* Advanced Error Reporting */
0018 #define PCIE_PORT_SERVICE_AER       (1 << PCIE_PORT_SERVICE_AER_SHIFT)
0019 #define PCIE_PORT_SERVICE_HP_SHIFT  2   /* Native Hotplug */
0020 #define PCIE_PORT_SERVICE_HP        (1 << PCIE_PORT_SERVICE_HP_SHIFT)
0021 #define PCIE_PORT_SERVICE_DPC_SHIFT 3   /* Downstream Port Containment */
0022 #define PCIE_PORT_SERVICE_DPC       (1 << PCIE_PORT_SERVICE_DPC_SHIFT)
0023 #define PCIE_PORT_SERVICE_BWNOTIF_SHIFT 4   /* Bandwidth notification */
0024 #define PCIE_PORT_SERVICE_BWNOTIF   (1 << PCIE_PORT_SERVICE_BWNOTIF_SHIFT)
0025
0026 #define PCIE_PORT_DEVICE_MAXSERVICES   5
0027
0028 extern bool pcie_ports_dpc_native;
0029
0030 #ifdef CONFIG_PCIEAER
0031 int pcie_aer_init(void);
0032 int pcie_aer_is_native(struct pci_dev *dev);
0033 #else
0034 static inline int pcie_aer_init(void) { return 0; }
0035 static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; }
0036 #endif
0037
0038 #ifdef CONFIG_HOTPLUG_PCI_PCIE
0039 int pcie_hp_init(void);
0040 #else
0041 static inline int pcie_hp_init(void) { return 0; }
0042 #endif
0043
0044 #ifdef CONFIG_PCIE_PME
0045 int pcie_pme_init(void);
0046 #else
0047 static inline int pcie_pme_init(void) { return 0; }
0048 #endif
0049
0050 #ifdef CONFIG_PCIE_DPC
0051 int pcie_dpc_init(void);
0052 #else
0053 static inline int pcie_dpc_init(void) { return 0; }
0054 #endif
0055
0056 /* Port Type */
0057 #define PCIE_ANY_PORT           (~0)
0058
0059 struct pcie_device {
0060     int     irq;        /* Service IRQ/MSI/MSI-X Vector */
0061     struct pci_dev *port;       /* Root/Upstream/Downstream Port */
0062     u32     service;    /* Port service this device represents */
0063     void        *priv_data; /* Service Private Data */
0064     struct device   device;     /* Generic Device Interface */
0065 };
0066 #define to_pcie_device(d) container_of(d, struct pcie_device, device)
0067
0068 static inline void set_service_data(struct pcie_device *dev, void *data)
0069 {
0070     dev->priv_data = data;
0071 }
0072
0073 static inline void *get_service_data(struct pcie_device *dev)
0074 {
0075     return dev->priv_data;
0076 }
0077
0078 struct pcie_port_service_driver {
0079     const char *name;
0080     int (*probe)(struct pcie_device *dev);
0081     void (*remove)(struct pcie_device *dev);
0082     int (*suspend)(struct pcie_device *dev);
0083     int (*resume_noirq)(struct pcie_device *dev);
0084     int (*resume)(struct pcie_device *dev);
0085     int (*runtime_suspend)(struct pcie_device *dev);
0086     int (*runtime_resume)(struct pcie_device *dev);
0087
0088     int (*slot_reset)(struct pcie_device *dev);
0089
0090     int port_type;  /* Type of the port this driver can handle */
0091     u32 service;    /* Port service this device represents */
0092
0093     struct device_driver driver;
0094 };
0095 #define to_service_driver(d) \
0096     container_of(d, struct pcie_port_service_driver, driver)
0097
0098 int pcie_port_service_register(struct pcie_port_service_driver *new);
0099 void pcie_port_service_unregister(struct pcie_port_service_driver *new);
0100
0101 /*
0102  * The PCIe Capability Interrupt Message Number (PCIe r3.1, sec 7.8.2) must
0103  * be one of the first 32 MSI-X entries.  Per PCI r3.0, sec 6.8.3.1, MSI
0104  * supports a maximum of 32 vectors per function.
0105  */
0106 #define PCIE_PORT_MAX_MSI_ENTRIES   32
0107
0108 #define get_descriptor_id(type, service) (((type - 4) << 8) | service)
0109
0110 extern struct bus_type pcie_port_bus_type;
0111 int pcie_port_device_register(struct pci_dev *dev);
0112 int pcie_port_device_iter(struct device *dev, void *data);
0113 #ifdef CONFIG_PM
0114 int pcie_port_device_suspend(struct device *dev);
0115 int pcie_port_device_resume_noirq(struct device *dev);
0116 int pcie_port_device_resume(struct device *dev);
0117 int pcie_port_device_runtime_suspend(struct device *dev);
0118 int pcie_port_device_runtime_resume(struct device *dev);
0119 #endif
0120 void pcie_port_device_remove(struct pci_dev *dev);
0121
0122 struct pci_dev;
0123
0124 #ifdef CONFIG_PCIE_PME
0125 extern bool pcie_pme_msi_disabled;
0126
0127 static inline void pcie_pme_disable_msi(void)
0128 {
0129     pcie_pme_msi_disabled = true;
0130 }
0131
0132 static inline bool pcie_pme_no_msi(void)
0133 {
0134     return pcie_pme_msi_disabled;
0135 }
0136
0137 void pcie_pme_interrupt_enable(struct pci_dev *dev, bool enable);
0138 #else /* !CONFIG_PCIE_PME */
0139 static inline void pcie_pme_disable_msi(void) {}
0140 static inline bool pcie_pme_no_msi(void) { return false; }
0141 static inline void pcie_pme_interrupt_enable(struct pci_dev *dev, bool en) {}
0142 #endif /* !CONFIG_PCIE_PME */
0143
0144 struct device *pcie_port_find_device(struct pci_dev *dev, u32 service);
0145 #endif /* _PORTDRV_H_ */