pci/pcie/dpc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * PCI Express Downstream Port Containment services driver
0004  * Author: Keith Busch <keith.busch@intel.com>
0005  *
0006  * Copyright (C) 2016 Intel Corp.
0007  */
0008
0009 #define dev_fmt(fmt) "DPC: " fmt
0010
0011 #include <linux/aer.h>
0012 #include <linux/delay.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/init.h>
0015 #include <linux/pci.h>
0016
0017 #include "portdrv.h"
0018 #include "../pci.h"
0019
0020 static const char * const rp_pio_error_string[] = {
0021     "Configuration Request received UR Completion",  /* Bit Position 0  */
0022     "Configuration Request received CA Completion",  /* Bit Position 1  */
0023     "Configuration Request Completion Timeout",  /* Bit Position 2  */
0024     NULL,
0025     NULL,
0026     NULL,
0027     NULL,
0028     NULL,
0029     "I/O Request received UR Completion",        /* Bit Position 8  */
0030     "I/O Request received CA Completion",        /* Bit Position 9  */
0031     "I/O Request Completion Timeout",        /* Bit Position 10 */
0032     NULL,
0033     NULL,
0034     NULL,
0035     NULL,
0036     NULL,
0037     "Memory Request received UR Completion",     /* Bit Position 16 */
0038     "Memory Request received CA Completion",     /* Bit Position 17 */
0039     "Memory Request Completion Timeout",         /* Bit Position 18 */
0040 };
0041
0042 void pci_save_dpc_state(struct pci_dev *dev)
0043 {
0044     struct pci_cap_saved_state *save_state;
0045     u16 *cap;
0046
0047     if (!pci_is_pcie(dev))
0048         return;
0049
0050     save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_DPC);
0051     if (!save_state)
0052         return;
0053
0054     cap = (u16 *)&save_state->cap.data[0];
0055     pci_read_config_word(dev, dev->dpc_cap + PCI_EXP_DPC_CTL, cap);
0056 }
0057
0058 void pci_restore_dpc_state(struct pci_dev *dev)
0059 {
0060     struct pci_cap_saved_state *save_state;
0061     u16 *cap;
0062
0063     if (!pci_is_pcie(dev))
0064         return;
0065
0066     save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_DPC);
0067     if (!save_state)
0068         return;
0069
0070     cap = (u16 *)&save_state->cap.data[0];
0071     pci_write_config_word(dev, dev->dpc_cap + PCI_EXP_DPC_CTL, *cap);
0072 }
0073
0074 static DECLARE_WAIT_QUEUE_HEAD(dpc_completed_waitqueue);
0075
0076 #ifdef CONFIG_HOTPLUG_PCI_PCIE
0077 static bool dpc_completed(struct pci_dev *pdev)
0078 {
0079     u16 status;
0080
0081     pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_STATUS, &status);
0082     if ((!PCI_POSSIBLE_ERROR(status)) && (status & PCI_EXP_DPC_STATUS_TRIGGER))
0083         return false;
0084
0085     if (test_bit(PCI_DPC_RECOVERING, &pdev->priv_flags))
0086         return false;
0087
0088     return true;
0089 }
0090
0091 /**
0092  * pci_dpc_recovered - whether DPC triggered and has recovered successfully
0093  * @pdev: PCI device
0094  *
0095  * Return true if DPC was triggered for @pdev and has recovered successfully.
0096  * Wait for recovery if it hasn't completed yet.  Called from the PCIe hotplug
0097  * driver to recognize and ignore Link Down/Up events caused by DPC.
0098  */
0099 bool pci_dpc_recovered(struct pci_dev *pdev)
0100 {
0101     struct pci_host_bridge *host;
0102
0103     if (!pdev->dpc_cap)
0104         return false;
0105
0106     /*
0107      * Synchronization between hotplug and DPC is not supported
0108      * if DPC is owned by firmware and EDR is not enabled.
0109      */
0110     host = pci_find_host_bridge(pdev->bus);
0111     if (!host->native_dpc && !IS_ENABLED(CONFIG_PCIE_EDR))
0112         return false;
0113
0114     /*
0115      * Need a timeout in case DPC never completes due to failure of
0116      * dpc_wait_rp_inactive().  The spec doesn't mandate a time limit,
0117      * but reports indicate that DPC completes within 4 seconds.
0118      */
0119     wait_event_timeout(dpc_completed_waitqueue, dpc_completed(pdev),
0120                msecs_to_jiffies(4000));
0121
0122     return test_and_clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
0123 }
0124 #endif /* CONFIG_HOTPLUG_PCI_PCIE */
0125
0126 static int dpc_wait_rp_inactive(struct pci_dev *pdev)
0127 {
0128     unsigned long timeout = jiffies + HZ;
0129     u16 cap = pdev->dpc_cap, status;
0130
0131     pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
0132     while (status & PCI_EXP_DPC_RP_BUSY &&
0133                     !time_after(jiffies, timeout)) {
0134         msleep(10);
0135         pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
0136     }
0137     if (status & PCI_EXP_DPC_RP_BUSY) {
0138         pci_warn(pdev, "root port still busy\n");
0139         return -EBUSY;
0140     }
0141     return 0;
0142 }
0143
0144 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev)
0145 {
0146     pci_ers_result_t ret;
0147     u16 cap;
0148
0149     set_bit(PCI_DPC_RECOVERING, &pdev->priv_flags);
0150
0151     /*
0152      * DPC disables the Link automatically in hardware, so it has
0153      * already been reset by the time we get here.
0154      */
0155     cap = pdev->dpc_cap;
0156
0157     /*
0158      * Wait until the Link is inactive, then clear DPC Trigger Status
0159      * to allow the Port to leave DPC.
0160      */
0161     if (!pcie_wait_for_link(pdev, false))
0162         pci_info(pdev, "Data Link Layer Link Active not cleared in 1000 msec\n");
0163
0164     if (pdev->dpc_rp_extensions && dpc_wait_rp_inactive(pdev)) {
0165         clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
0166         ret = PCI_ERS_RESULT_DISCONNECT;
0167         goto out;
0168     }
0169
0170     pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
0171                   PCI_EXP_DPC_STATUS_TRIGGER);
0172
0173     if (!pcie_wait_for_link(pdev, true)) {
0174         pci_info(pdev, "Data Link Layer Link Active not set in 1000 msec\n");
0175         clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
0176         ret = PCI_ERS_RESULT_DISCONNECT;
0177     } else {
0178         set_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
0179         ret = PCI_ERS_RESULT_RECOVERED;
0180     }
0181 out:
0182     clear_bit(PCI_DPC_RECOVERING, &pdev->priv_flags);
0183     wake_up_all(&dpc_completed_waitqueue);
0184     return ret;
0185 }
0186
0187 static void dpc_process_rp_pio_error(struct pci_dev *pdev)
0188 {
0189     u16 cap = pdev->dpc_cap, dpc_status, first_error;
0190     u32 status, mask, sev, syserr, exc, dw0, dw1, dw2, dw3, log, prefix;
0191     int i;
0192
0193     pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);
0194     pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask);
0195     pci_err(pdev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
0196         status, mask);
0197
0198     pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev);
0199     pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr);
0200     pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc);
0201     pci_err(pdev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
0202         sev, syserr, exc);
0203
0204     /* Get First Error Pointer */
0205     pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status);
0206     first_error = (dpc_status & 0x1f00) >> 8;
0207
0208     for (i = 0; i < ARRAY_SIZE(rp_pio_error_string); i++) {
0209         if ((status & ~mask) & (1 << i))
0210             pci_err(pdev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
0211                 first_error == i ? " (First)" : "");
0212     }
0213
0214     if (pdev->dpc_rp_log_size < 4)
0215         goto clear_status;
0216     pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
0217                   &dw0);
0218     pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
0219                   &dw1);
0220     pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
0221                   &dw2);
0222     pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
0223                   &dw3);
0224     pci_err(pdev, "TLP Header: %#010x %#010x %#010x %#010x\n",
0225         dw0, dw1, dw2, dw3);
0226
0227     if (pdev->dpc_rp_log_size < 5)
0228         goto clear_status;
0229     pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log);
0230     pci_err(pdev, "RP PIO ImpSpec Log %#010x\n", log);
0231
0232     for (i = 0; i < pdev->dpc_rp_log_size - 5; i++) {
0233         pci_read_config_dword(pdev,
0234             cap + PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG, &prefix);
0235         pci_err(pdev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix);
0236     }
0237  clear_status:
0238     pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, status);
0239 }
0240
0241 static int dpc_get_aer_uncorrect_severity(struct pci_dev *dev,
0242                       struct aer_err_info *info)
0243 {
0244     int pos = dev->aer_cap;
0245     u32 status, mask, sev;
0246
0247     pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
0248     pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &mask);
0249     status &= ~mask;
0250     if (!status)
0251         return 0;
0252
0253     pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &sev);
0254     status &= sev;
0255     if (status)
0256         info->severity = AER_FATAL;
0257     else
0258         info->severity = AER_NONFATAL;
0259
0260     return 1;
0261 }
0262
0263 void dpc_process_error(struct pci_dev *pdev)
0264 {
0265     u16 cap = pdev->dpc_cap, status, source, reason, ext_reason;
0266     struct aer_err_info info;
0267
0268     pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
0269     pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID, &source);
0270
0271     pci_info(pdev, "containment event, status:%#06x source:%#06x\n",
0272          status, source);
0273
0274     reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN) >> 1;
0275     ext_reason = (status & PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT) >> 5;
0276     pci_warn(pdev, "%s detected\n",
0277          (reason == 0) ? "unmasked uncorrectable error" :
0278          (reason == 1) ? "ERR_NONFATAL" :
0279          (reason == 2) ? "ERR_FATAL" :
0280          (ext_reason == 0) ? "RP PIO error" :
0281          (ext_reason == 1) ? "software trigger" :
0282                      "reserved error");
0283
0284     /* show RP PIO error detail information */
0285     if (pdev->dpc_rp_extensions && reason == 3 && ext_reason == 0)
0286         dpc_process_rp_pio_error(pdev);
0287     else if (reason == 0 &&
0288          dpc_get_aer_uncorrect_severity(pdev, &info) &&
0289          aer_get_device_error_info(pdev, &info)) {
0290         aer_print_error(pdev, &info);
0291         pci_aer_clear_nonfatal_status(pdev);
0292         pci_aer_clear_fatal_status(pdev);
0293     }
0294 }
0295
0296 static irqreturn_t dpc_handler(int irq, void *context)
0297 {
0298     struct pci_dev *pdev = context;
0299
0300     dpc_process_error(pdev);
0301
0302     /* We configure DPC so it only triggers on ERR_FATAL */
0303     pcie_do_recovery(pdev, pci_channel_io_frozen, dpc_reset_link);
0304
0305     return IRQ_HANDLED;
0306 }
0307
0308 static irqreturn_t dpc_irq(int irq, void *context)
0309 {
0310     struct pci_dev *pdev = context;
0311     u16 cap = pdev->dpc_cap, status;
0312
0313     pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
0314
0315     if (!(status & PCI_EXP_DPC_STATUS_INTERRUPT) || PCI_POSSIBLE_ERROR(status))
0316         return IRQ_NONE;
0317
0318     pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
0319                   PCI_EXP_DPC_STATUS_INTERRUPT);
0320     if (status & PCI_EXP_DPC_STATUS_TRIGGER)
0321         return IRQ_WAKE_THREAD;
0322     return IRQ_HANDLED;
0323 }
0324
0325 void pci_dpc_init(struct pci_dev *pdev)
0326 {
0327     u16 cap;
0328
0329     pdev->dpc_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
0330     if (!pdev->dpc_cap)
0331         return;
0332
0333     pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
0334     if (!(cap & PCI_EXP_DPC_CAP_RP_EXT))
0335         return;
0336
0337     pdev->dpc_rp_extensions = true;
0338     pdev->dpc_rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
0339     if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
0340         pci_err(pdev, "RP PIO log size %u is invalid\n",
0341             pdev->dpc_rp_log_size);
0342         pdev->dpc_rp_log_size = 0;
0343     }
0344 }
0345
0346 #define FLAG(x, y) (((x) & (y)) ? '+' : '-')
0347 static int dpc_probe(struct pcie_device *dev)
0348 {
0349     struct pci_dev *pdev = dev->port;
0350     struct device *device = &dev->device;
0351     int status;
0352     u16 ctl, cap;
0353
0354     if (!pcie_aer_is_native(pdev) && !pcie_ports_dpc_native)
0355         return -ENOTSUPP;
0356
0357     status = devm_request_threaded_irq(device, dev->irq, dpc_irq,
0358                        dpc_handler, IRQF_SHARED,
0359                        "pcie-dpc", pdev);
0360     if (status) {
0361         pci_warn(pdev, "request IRQ%d failed: %d\n", dev->irq,
0362              status);
0363         return status;
0364     }
0365
0366     pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
0367     pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl);
0368
0369     ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN;
0370     pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl);
0371     pci_info(pdev, "enabled with IRQ %d\n", dev->irq);
0372
0373     pci_info(pdev, "error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
0374          cap & PCI_EXP_DPC_IRQ, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
0375          FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),
0376          FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), pdev->dpc_rp_log_size,
0377          FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE));
0378
0379     pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_DPC, sizeof(u16));
0380     return status;
0381 }
0382
0383 static void dpc_remove(struct pcie_device *dev)
0384 {
0385     struct pci_dev *pdev = dev->port;
0386     u16 ctl;
0387
0388     pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl);
0389     ctl &= ~(PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN);
0390     pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl);
0391 }
0392
0393 static struct pcie_port_service_driver dpcdriver = {
0394     .name       = "dpc",
0395     .port_type  = PCIE_ANY_PORT,
0396     .service    = PCIE_PORT_SERVICE_DPC,
0397     .probe      = dpc_probe,
0398     .remove     = dpc_remove,
0399 };
0400
0401 int __init pcie_dpc_init(void)
0402 {
0403     return pcie_port_service_register(&dpcdriver);
0404 }