Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Enable PCIe link L0s/L1 state and Clock Power Management
0004  *
0005  * Copyright (C) 2007 Intel
0006  * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
0007  * Copyright (C) Shaohua Li (shaohua.li@intel.com)
0008  */
0009 
0010 #include <linux/kernel.h>
0011 #include <linux/module.h>
0012 #include <linux/moduleparam.h>
0013 #include <linux/pci.h>
0014 #include <linux/pci_regs.h>
0015 #include <linux/errno.h>
0016 #include <linux/pm.h>
0017 #include <linux/init.h>
0018 #include <linux/slab.h>
0019 #include <linux/jiffies.h>
0020 #include <linux/delay.h>
0021 #include "../pci.h"
0022 
0023 #ifdef MODULE_PARAM_PREFIX
0024 #undef MODULE_PARAM_PREFIX
0025 #endif
0026 #define MODULE_PARAM_PREFIX "pcie_aspm."
0027 
0028 /* Note: those are not register definitions */
0029 #define ASPM_STATE_L0S_UP   (1) /* Upstream direction L0s state */
0030 #define ASPM_STATE_L0S_DW   (2) /* Downstream direction L0s state */
0031 #define ASPM_STATE_L1       (4) /* L1 state */
0032 #define ASPM_STATE_L1_1     (8) /* ASPM L1.1 state */
0033 #define ASPM_STATE_L1_2     (0x10)  /* ASPM L1.2 state */
0034 #define ASPM_STATE_L1_1_PCIPM   (0x20)  /* PCI PM L1.1 state */
0035 #define ASPM_STATE_L1_2_PCIPM   (0x40)  /* PCI PM L1.2 state */
0036 #define ASPM_STATE_L1_SS_PCIPM  (ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1_2_PCIPM)
0037 #define ASPM_STATE_L1_2_MASK    (ASPM_STATE_L1_2 | ASPM_STATE_L1_2_PCIPM)
0038 #define ASPM_STATE_L1SS     (ASPM_STATE_L1_1 | ASPM_STATE_L1_1_PCIPM |\
0039                  ASPM_STATE_L1_2_MASK)
0040 #define ASPM_STATE_L0S      (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
0041 #define ASPM_STATE_ALL      (ASPM_STATE_L0S | ASPM_STATE_L1 |   \
0042                  ASPM_STATE_L1SS)
0043 
0044 struct pcie_link_state {
0045     struct pci_dev *pdev;       /* Upstream component of the Link */
0046     struct pci_dev *downstream; /* Downstream component, function 0 */
0047     struct pcie_link_state *root;   /* pointer to the root port link */
0048     struct pcie_link_state *parent; /* pointer to the parent Link state */
0049     struct list_head sibling;   /* node in link_list */
0050 
0051     /* ASPM state */
0052     u32 aspm_support:7;     /* Supported ASPM state */
0053     u32 aspm_enabled:7;     /* Enabled ASPM state */
0054     u32 aspm_capable:7;     /* Capable ASPM state with latency */
0055     u32 aspm_default:7;     /* Default ASPM state by BIOS */
0056     u32 aspm_disable:7;     /* Disabled ASPM state */
0057 
0058     /* Clock PM state */
0059     u32 clkpm_capable:1;        /* Clock PM capable? */
0060     u32 clkpm_enabled:1;        /* Current Clock PM state */
0061     u32 clkpm_default:1;        /* Default Clock PM state by BIOS */
0062     u32 clkpm_disable:1;        /* Clock PM disabled */
0063 };
0064 
0065 static int aspm_disabled, aspm_force;
0066 static bool aspm_support_enabled = true;
0067 static DEFINE_MUTEX(aspm_lock);
0068 static LIST_HEAD(link_list);
0069 
0070 #define POLICY_DEFAULT 0    /* BIOS default setting */
0071 #define POLICY_PERFORMANCE 1    /* high performance */
0072 #define POLICY_POWERSAVE 2  /* high power saving */
0073 #define POLICY_POWER_SUPERSAVE 3 /* possibly even more power saving */
0074 
0075 #ifdef CONFIG_PCIEASPM_PERFORMANCE
0076 static int aspm_policy = POLICY_PERFORMANCE;
0077 #elif defined CONFIG_PCIEASPM_POWERSAVE
0078 static int aspm_policy = POLICY_POWERSAVE;
0079 #elif defined CONFIG_PCIEASPM_POWER_SUPERSAVE
0080 static int aspm_policy = POLICY_POWER_SUPERSAVE;
0081 #else
0082 static int aspm_policy;
0083 #endif
0084 
0085 static const char *policy_str[] = {
0086     [POLICY_DEFAULT] = "default",
0087     [POLICY_PERFORMANCE] = "performance",
0088     [POLICY_POWERSAVE] = "powersave",
0089     [POLICY_POWER_SUPERSAVE] = "powersupersave"
0090 };
0091 
0092 #define LINK_RETRAIN_TIMEOUT HZ
0093 
0094 /*
0095  * The L1 PM substate capability is only implemented in function 0 in a
0096  * multi function device.
0097  */
0098 static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
0099 {
0100     struct pci_dev *child;
0101 
0102     list_for_each_entry(child, &linkbus->devices, bus_list)
0103         if (PCI_FUNC(child->devfn) == 0)
0104             return child;
0105     return NULL;
0106 }
0107 
0108 static int policy_to_aspm_state(struct pcie_link_state *link)
0109 {
0110     switch (aspm_policy) {
0111     case POLICY_PERFORMANCE:
0112         /* Disable ASPM and Clock PM */
0113         return 0;
0114     case POLICY_POWERSAVE:
0115         /* Enable ASPM L0s/L1 */
0116         return (ASPM_STATE_L0S | ASPM_STATE_L1);
0117     case POLICY_POWER_SUPERSAVE:
0118         /* Enable Everything */
0119         return ASPM_STATE_ALL;
0120     case POLICY_DEFAULT:
0121         return link->aspm_default;
0122     }
0123     return 0;
0124 }
0125 
0126 static int policy_to_clkpm_state(struct pcie_link_state *link)
0127 {
0128     switch (aspm_policy) {
0129     case POLICY_PERFORMANCE:
0130         /* Disable ASPM and Clock PM */
0131         return 0;
0132     case POLICY_POWERSAVE:
0133     case POLICY_POWER_SUPERSAVE:
0134         /* Enable Clock PM */
0135         return 1;
0136     case POLICY_DEFAULT:
0137         return link->clkpm_default;
0138     }
0139     return 0;
0140 }
0141 
0142 static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
0143 {
0144     struct pci_dev *child;
0145     struct pci_bus *linkbus = link->pdev->subordinate;
0146     u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
0147 
0148     list_for_each_entry(child, &linkbus->devices, bus_list)
0149         pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
0150                            PCI_EXP_LNKCTL_CLKREQ_EN,
0151                            val);
0152     link->clkpm_enabled = !!enable;
0153 }
0154 
0155 static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
0156 {
0157     /*
0158      * Don't enable Clock PM if the link is not Clock PM capable
0159      * or Clock PM is disabled
0160      */
0161     if (!link->clkpm_capable || link->clkpm_disable)
0162         enable = 0;
0163     /* Need nothing if the specified equals to current state */
0164     if (link->clkpm_enabled == enable)
0165         return;
0166     pcie_set_clkpm_nocheck(link, enable);
0167 }
0168 
0169 static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
0170 {
0171     int capable = 1, enabled = 1;
0172     u32 reg32;
0173     u16 reg16;
0174     struct pci_dev *child;
0175     struct pci_bus *linkbus = link->pdev->subordinate;
0176 
0177     /* All functions should have the same cap and state, take the worst */
0178     list_for_each_entry(child, &linkbus->devices, bus_list) {
0179         pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &reg32);
0180         if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
0181             capable = 0;
0182             enabled = 0;
0183             break;
0184         }
0185         pcie_capability_read_word(child, PCI_EXP_LNKCTL, &reg16);
0186         if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
0187             enabled = 0;
0188     }
0189     link->clkpm_enabled = enabled;
0190     link->clkpm_default = enabled;
0191     link->clkpm_capable = capable;
0192     link->clkpm_disable = blacklist ? 1 : 0;
0193 }
0194 
0195 static bool pcie_retrain_link(struct pcie_link_state *link)
0196 {
0197     struct pci_dev *parent = link->pdev;
0198     unsigned long end_jiffies;
0199     u16 reg16;
0200 
0201     pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &reg16);
0202     reg16 |= PCI_EXP_LNKCTL_RL;
0203     pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
0204     if (parent->clear_retrain_link) {
0205         /*
0206          * Due to an erratum in some devices the Retrain Link bit
0207          * needs to be cleared again manually to allow the link
0208          * training to succeed.
0209          */
0210         reg16 &= ~PCI_EXP_LNKCTL_RL;
0211         pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
0212     }
0213 
0214     /* Wait for link training end. Break out after waiting for timeout */
0215     end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT;
0216     do {
0217         pcie_capability_read_word(parent, PCI_EXP_LNKSTA, &reg16);
0218         if (!(reg16 & PCI_EXP_LNKSTA_LT))
0219             break;
0220         msleep(1);
0221     } while (time_before(jiffies, end_jiffies));
0222     return !(reg16 & PCI_EXP_LNKSTA_LT);
0223 }
0224 
0225 /*
0226  * pcie_aspm_configure_common_clock: check if the 2 ends of a link
0227  *   could use common clock. If they are, configure them to use the
0228  *   common clock. That will reduce the ASPM state exit latency.
0229  */
0230 static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
0231 {
0232     int same_clock = 1;
0233     u16 reg16, parent_reg, child_reg[8];
0234     struct pci_dev *child, *parent = link->pdev;
0235     struct pci_bus *linkbus = parent->subordinate;
0236     /*
0237      * All functions of a slot should have the same Slot Clock
0238      * Configuration, so just check one function
0239      */
0240     child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
0241     BUG_ON(!pci_is_pcie(child));
0242 
0243     /* Check downstream component if bit Slot Clock Configuration is 1 */
0244     pcie_capability_read_word(child, PCI_EXP_LNKSTA, &reg16);
0245     if (!(reg16 & PCI_EXP_LNKSTA_SLC))
0246         same_clock = 0;
0247 
0248     /* Check upstream component if bit Slot Clock Configuration is 1 */
0249     pcie_capability_read_word(parent, PCI_EXP_LNKSTA, &reg16);
0250     if (!(reg16 & PCI_EXP_LNKSTA_SLC))
0251         same_clock = 0;
0252 
0253     /* Port might be already in common clock mode */
0254     pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &reg16);
0255     if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) {
0256         bool consistent = true;
0257 
0258         list_for_each_entry(child, &linkbus->devices, bus_list) {
0259             pcie_capability_read_word(child, PCI_EXP_LNKCTL,
0260                           &reg16);
0261             if (!(reg16 & PCI_EXP_LNKCTL_CCC)) {
0262                 consistent = false;
0263                 break;
0264             }
0265         }
0266         if (consistent)
0267             return;
0268         pci_info(parent, "ASPM: current common clock configuration is inconsistent, reconfiguring\n");
0269     }
0270 
0271     /* Configure downstream component, all functions */
0272     list_for_each_entry(child, &linkbus->devices, bus_list) {
0273         pcie_capability_read_word(child, PCI_EXP_LNKCTL, &reg16);
0274         child_reg[PCI_FUNC(child->devfn)] = reg16;
0275         if (same_clock)
0276             reg16 |= PCI_EXP_LNKCTL_CCC;
0277         else
0278             reg16 &= ~PCI_EXP_LNKCTL_CCC;
0279         pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
0280     }
0281 
0282     /* Configure upstream component */
0283     pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &reg16);
0284     parent_reg = reg16;
0285     if (same_clock)
0286         reg16 |= PCI_EXP_LNKCTL_CCC;
0287     else
0288         reg16 &= ~PCI_EXP_LNKCTL_CCC;
0289     pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
0290 
0291     if (pcie_retrain_link(link))
0292         return;
0293 
0294     /* Training failed. Restore common clock configurations */
0295     pci_err(parent, "ASPM: Could not configure common clock\n");
0296     list_for_each_entry(child, &linkbus->devices, bus_list)
0297         pcie_capability_write_word(child, PCI_EXP_LNKCTL,
0298                        child_reg[PCI_FUNC(child->devfn)]);
0299     pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
0300 }
0301 
0302 /* Convert L0s latency encoding to ns */
0303 static u32 calc_l0s_latency(u32 lnkcap)
0304 {
0305     u32 encoding = (lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12;
0306 
0307     if (encoding == 0x7)
0308         return (5 * 1000);  /* > 4us */
0309     return (64 << encoding);
0310 }
0311 
0312 /* Convert L0s acceptable latency encoding to ns */
0313 static u32 calc_l0s_acceptable(u32 encoding)
0314 {
0315     if (encoding == 0x7)
0316         return -1U;
0317     return (64 << encoding);
0318 }
0319 
0320 /* Convert L1 latency encoding to ns */
0321 static u32 calc_l1_latency(u32 lnkcap)
0322 {
0323     u32 encoding = (lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15;
0324 
0325     if (encoding == 0x7)
0326         return (65 * 1000); /* > 64us */
0327     return (1000 << encoding);
0328 }
0329 
0330 /* Convert L1 acceptable latency encoding to ns */
0331 static u32 calc_l1_acceptable(u32 encoding)
0332 {
0333     if (encoding == 0x7)
0334         return -1U;
0335     return (1000 << encoding);
0336 }
0337 
0338 /* Convert L1SS T_pwr encoding to usec */
0339 static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val)
0340 {
0341     switch (scale) {
0342     case 0:
0343         return val * 2;
0344     case 1:
0345         return val * 10;
0346     case 2:
0347         return val * 100;
0348     }
0349     pci_err(pdev, "%s: Invalid T_PwrOn scale: %u\n", __func__, scale);
0350     return 0;
0351 }
0352 
0353 static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
0354 {
0355     u32 threshold_ns = threshold_us * 1000;
0356 
0357     /* See PCIe r3.1, sec 7.33.3 and sec 6.18 */
0358     if (threshold_ns < 32) {
0359         *scale = 0;
0360         *value = threshold_ns;
0361     } else if (threshold_ns < 1024) {
0362         *scale = 1;
0363         *value = threshold_ns >> 5;
0364     } else if (threshold_ns < 32768) {
0365         *scale = 2;
0366         *value = threshold_ns >> 10;
0367     } else if (threshold_ns < 1048576) {
0368         *scale = 3;
0369         *value = threshold_ns >> 15;
0370     } else if (threshold_ns < 33554432) {
0371         *scale = 4;
0372         *value = threshold_ns >> 20;
0373     } else {
0374         *scale = 5;
0375         *value = threshold_ns >> 25;
0376     }
0377 }
0378 
0379 static void pcie_aspm_check_latency(struct pci_dev *endpoint)
0380 {
0381     u32 latency, encoding, lnkcap_up, lnkcap_dw;
0382     u32 l1_switch_latency = 0, latency_up_l0s;
0383     u32 latency_up_l1, latency_dw_l0s, latency_dw_l1;
0384     u32 acceptable_l0s, acceptable_l1;
0385     struct pcie_link_state *link;
0386 
0387     /* Device not in D0 doesn't need latency check */
0388     if ((endpoint->current_state != PCI_D0) &&
0389         (endpoint->current_state != PCI_UNKNOWN))
0390         return;
0391 
0392     link = endpoint->bus->self->link_state;
0393 
0394     /* Calculate endpoint L0s acceptable latency */
0395     encoding = (endpoint->devcap & PCI_EXP_DEVCAP_L0S) >> 6;
0396     acceptable_l0s = calc_l0s_acceptable(encoding);
0397 
0398     /* Calculate endpoint L1 acceptable latency */
0399     encoding = (endpoint->devcap & PCI_EXP_DEVCAP_L1) >> 9;
0400     acceptable_l1 = calc_l1_acceptable(encoding);
0401 
0402     while (link) {
0403         struct pci_dev *dev = pci_function_0(link->pdev->subordinate);
0404 
0405         /* Read direction exit latencies */
0406         pcie_capability_read_dword(link->pdev, PCI_EXP_LNKCAP,
0407                        &lnkcap_up);
0408         pcie_capability_read_dword(dev, PCI_EXP_LNKCAP,
0409                        &lnkcap_dw);
0410         latency_up_l0s = calc_l0s_latency(lnkcap_up);
0411         latency_up_l1 = calc_l1_latency(lnkcap_up);
0412         latency_dw_l0s = calc_l0s_latency(lnkcap_dw);
0413         latency_dw_l1 = calc_l1_latency(lnkcap_dw);
0414 
0415         /* Check upstream direction L0s latency */
0416         if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
0417             (latency_up_l0s > acceptable_l0s))
0418             link->aspm_capable &= ~ASPM_STATE_L0S_UP;
0419 
0420         /* Check downstream direction L0s latency */
0421         if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
0422             (latency_dw_l0s > acceptable_l0s))
0423             link->aspm_capable &= ~ASPM_STATE_L0S_DW;
0424         /*
0425          * Check L1 latency.
0426          * Every switch on the path to root complex need 1
0427          * more microsecond for L1. Spec doesn't mention L0s.
0428          *
0429          * The exit latencies for L1 substates are not advertised
0430          * by a device.  Since the spec also doesn't mention a way
0431          * to determine max latencies introduced by enabling L1
0432          * substates on the components, it is not clear how to do
0433          * a L1 substate exit latency check.  We assume that the
0434          * L1 exit latencies advertised by a device include L1
0435          * substate latencies (and hence do not do any check).
0436          */
0437         latency = max_t(u32, latency_up_l1, latency_dw_l1);
0438         if ((link->aspm_capable & ASPM_STATE_L1) &&
0439             (latency + l1_switch_latency > acceptable_l1))
0440             link->aspm_capable &= ~ASPM_STATE_L1;
0441         l1_switch_latency += 1000;
0442 
0443         link = link->parent;
0444     }
0445 }
0446 
0447 static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
0448                     u32 clear, u32 set)
0449 {
0450     u32 val;
0451 
0452     pci_read_config_dword(pdev, pos, &val);
0453     val &= ~clear;
0454     val |= set;
0455     pci_write_config_dword(pdev, pos, val);
0456 }
0457 
0458 /* Calculate L1.2 PM substate timing parameters */
0459 static void aspm_calc_l1ss_info(struct pcie_link_state *link,
0460                 u32 parent_l1ss_cap, u32 child_l1ss_cap)
0461 {
0462     struct pci_dev *child = link->downstream, *parent = link->pdev;
0463     u32 val1, val2, scale1, scale2;
0464     u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
0465     u32 ctl1 = 0, ctl2 = 0;
0466     u32 pctl1, pctl2, cctl1, cctl2;
0467     u32 pl1_2_enables, cl1_2_enables;
0468 
0469     if (!(link->aspm_support & ASPM_STATE_L1_2_MASK))
0470         return;
0471 
0472     /* Choose the greater of the two Port Common_Mode_Restore_Times */
0473     val1 = (parent_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
0474     val2 = (child_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
0475     t_common_mode = max(val1, val2);
0476 
0477     /* Choose the greater of the two Port T_POWER_ON times */
0478     val1   = (parent_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
0479     scale1 = (parent_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
0480     val2   = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
0481     scale2 = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
0482 
0483     if (calc_l1ss_pwron(parent, scale1, val1) >
0484         calc_l1ss_pwron(child, scale2, val2)) {
0485         ctl2 |= scale1 | (val1 << 3);
0486         t_power_on = calc_l1ss_pwron(parent, scale1, val1);
0487     } else {
0488         ctl2 |= scale2 | (val2 << 3);
0489         t_power_on = calc_l1ss_pwron(child, scale2, val2);
0490     }
0491 
0492     /*
0493      * Set LTR_L1.2_THRESHOLD to the time required to transition the
0494      * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if
0495      * downstream devices report (via LTR) that they can tolerate at
0496      * least that much latency.
0497      *
0498      * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and
0499      * Table 5-11.  T(POWER_OFF) is at most 2us and T(L1.2) is at
0500      * least 4us.
0501      */
0502     l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
0503     encode_l12_threshold(l1_2_threshold, &scale, &value);
0504     ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
0505 
0506     /* Some broken devices only support dword access to L1 SS */
0507     pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, &pctl1);
0508     pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, &pctl2);
0509     pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, &cctl1);
0510     pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL2, &cctl2);
0511 
0512     if (ctl1 == pctl1 && ctl1 == cctl1 &&
0513         ctl2 == pctl2 && ctl2 == cctl2)
0514         return;
0515 
0516     /* Disable L1.2 while updating.  See PCIe r5.0, sec 5.5.4, 7.8.3.3 */
0517     pl1_2_enables = pctl1 & PCI_L1SS_CTL1_L1_2_MASK;
0518     cl1_2_enables = cctl1 & PCI_L1SS_CTL1_L1_2_MASK;
0519 
0520     if (pl1_2_enables || cl1_2_enables) {
0521         pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
0522                     PCI_L1SS_CTL1_L1_2_MASK, 0);
0523         pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
0524                     PCI_L1SS_CTL1_L1_2_MASK, 0);
0525     }
0526 
0527     /* Program T_POWER_ON times in both ports */
0528     pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2);
0529     pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2);
0530 
0531     /* Program Common_Mode_Restore_Time in upstream device */
0532     pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
0533                 PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1);
0534 
0535     /* Program LTR_L1.2_THRESHOLD time in both ports */
0536     pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
0537                 PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
0538                 PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
0539     pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
0540                 PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
0541                 PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
0542 
0543     if (pl1_2_enables || cl1_2_enables) {
0544         pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, 0,
0545                     pl1_2_enables);
0546         pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, 0,
0547                     cl1_2_enables);
0548     }
0549 }
0550 
0551 static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
0552 {
0553     struct pci_dev *child = link->downstream, *parent = link->pdev;
0554     u32 parent_lnkcap, child_lnkcap;
0555     u16 parent_lnkctl, child_lnkctl;
0556     u32 parent_l1ss_cap, child_l1ss_cap;
0557     u32 parent_l1ss_ctl1 = 0, child_l1ss_ctl1 = 0;
0558     struct pci_bus *linkbus = parent->subordinate;
0559 
0560     if (blacklist) {
0561         /* Set enabled/disable so that we will disable ASPM later */
0562         link->aspm_enabled = ASPM_STATE_ALL;
0563         link->aspm_disable = ASPM_STATE_ALL;
0564         return;
0565     }
0566 
0567     /*
0568      * If ASPM not supported, don't mess with the clocks and link,
0569      * bail out now.
0570      */
0571     pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap);
0572     pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
0573     if (!(parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPMS))
0574         return;
0575 
0576     /* Configure common clock before checking latencies */
0577     pcie_aspm_configure_common_clock(link);
0578 
0579     /*
0580      * Re-read upstream/downstream components' register state after
0581      * clock configuration.  L0s & L1 exit latencies in the otherwise
0582      * read-only Link Capabilities may change depending on common clock
0583      * configuration (PCIe r5.0, sec 7.5.3.6).
0584      */
0585     pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap);
0586     pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
0587     pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl);
0588     pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl);
0589 
0590     /*
0591      * Setup L0s state
0592      *
0593      * Note that we must not enable L0s in either direction on a
0594      * given link unless components on both sides of the link each
0595      * support L0s.
0596      */
0597     if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L0S)
0598         link->aspm_support |= ASPM_STATE_L0S;
0599 
0600     if (child_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
0601         link->aspm_enabled |= ASPM_STATE_L0S_UP;
0602     if (parent_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
0603         link->aspm_enabled |= ASPM_STATE_L0S_DW;
0604 
0605     /* Setup L1 state */
0606     if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L1)
0607         link->aspm_support |= ASPM_STATE_L1;
0608 
0609     if (parent_lnkctl & child_lnkctl & PCI_EXP_LNKCTL_ASPM_L1)
0610         link->aspm_enabled |= ASPM_STATE_L1;
0611 
0612     /* Setup L1 substate */
0613     pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP,
0614                   &parent_l1ss_cap);
0615     pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP,
0616                   &child_l1ss_cap);
0617 
0618     if (!(parent_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))
0619         parent_l1ss_cap = 0;
0620     if (!(child_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))
0621         child_l1ss_cap = 0;
0622 
0623     /*
0624      * If we don't have LTR for the entire path from the Root Complex
0625      * to this device, we can't use ASPM L1.2 because it relies on the
0626      * LTR_L1.2_THRESHOLD.  See PCIe r4.0, secs 5.5.4, 6.18.
0627      */
0628     if (!child->ltr_path)
0629         child_l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2;
0630 
0631     if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
0632         link->aspm_support |= ASPM_STATE_L1_1;
0633     if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)
0634         link->aspm_support |= ASPM_STATE_L1_2;
0635     if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)
0636         link->aspm_support |= ASPM_STATE_L1_1_PCIPM;
0637     if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
0638         link->aspm_support |= ASPM_STATE_L1_2_PCIPM;
0639 
0640     if (parent_l1ss_cap)
0641         pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
0642                       &parent_l1ss_ctl1);
0643     if (child_l1ss_cap)
0644         pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
0645                       &child_l1ss_ctl1);
0646 
0647     if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
0648         link->aspm_enabled |= ASPM_STATE_L1_1;
0649     if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
0650         link->aspm_enabled |= ASPM_STATE_L1_2;
0651     if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
0652         link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
0653     if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
0654         link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
0655 
0656     if (link->aspm_support & ASPM_STATE_L1SS)
0657         aspm_calc_l1ss_info(link, parent_l1ss_cap, child_l1ss_cap);
0658 
0659     /* Save default state */
0660     link->aspm_default = link->aspm_enabled;
0661 
0662     /* Setup initial capable state. Will be updated later */
0663     link->aspm_capable = link->aspm_support;
0664 
0665     /* Get and check endpoint acceptable latencies */
0666     list_for_each_entry(child, &linkbus->devices, bus_list) {
0667         if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
0668             pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
0669             continue;
0670 
0671         pcie_aspm_check_latency(child);
0672     }
0673 }
0674 
0675 /* Configure the ASPM L1 substates */
0676 static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
0677 {
0678     u32 val, enable_req;
0679     struct pci_dev *child = link->downstream, *parent = link->pdev;
0680 
0681     enable_req = (link->aspm_enabled ^ state) & state;
0682 
0683     /*
0684      * Here are the rules specified in the PCIe spec for enabling L1SS:
0685      * - When enabling L1.x, enable bit at parent first, then at child
0686      * - When disabling L1.x, disable bit at child first, then at parent
0687      * - When enabling ASPM L1.x, need to disable L1
0688      *   (at child followed by parent).
0689      * - The ASPM/PCIPM L1.2 must be disabled while programming timing
0690      *   parameters
0691      *
0692      * To keep it simple, disable all L1SS bits first, and later enable
0693      * what is needed.
0694      */
0695 
0696     /* Disable all L1 substates */
0697     pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
0698                 PCI_L1SS_CTL1_L1SS_MASK, 0);
0699     pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
0700                 PCI_L1SS_CTL1_L1SS_MASK, 0);
0701     /*
0702      * If needed, disable L1, and it gets enabled later
0703      * in pcie_config_aspm_link().
0704      */
0705     if (enable_req & (ASPM_STATE_L1_1 | ASPM_STATE_L1_2)) {
0706         pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
0707                            PCI_EXP_LNKCTL_ASPM_L1, 0);
0708         pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
0709                            PCI_EXP_LNKCTL_ASPM_L1, 0);
0710     }
0711 
0712     val = 0;
0713     if (state & ASPM_STATE_L1_1)
0714         val |= PCI_L1SS_CTL1_ASPM_L1_1;
0715     if (state & ASPM_STATE_L1_2)
0716         val |= PCI_L1SS_CTL1_ASPM_L1_2;
0717     if (state & ASPM_STATE_L1_1_PCIPM)
0718         val |= PCI_L1SS_CTL1_PCIPM_L1_1;
0719     if (state & ASPM_STATE_L1_2_PCIPM)
0720         val |= PCI_L1SS_CTL1_PCIPM_L1_2;
0721 
0722     /* Enable what we need to enable */
0723     pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
0724                 PCI_L1SS_CTL1_L1SS_MASK, val);
0725     pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
0726                 PCI_L1SS_CTL1_L1SS_MASK, val);
0727 }
0728 
0729 static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
0730 {
0731     pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
0732                        PCI_EXP_LNKCTL_ASPMC, val);
0733 }
0734 
0735 static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
0736 {
0737     u32 upstream = 0, dwstream = 0;
0738     struct pci_dev *child = link->downstream, *parent = link->pdev;
0739     struct pci_bus *linkbus = parent->subordinate;
0740 
0741     /* Enable only the states that were not explicitly disabled */
0742     state &= (link->aspm_capable & ~link->aspm_disable);
0743 
0744     /* Can't enable any substates if L1 is not enabled */
0745     if (!(state & ASPM_STATE_L1))
0746         state &= ~ASPM_STATE_L1SS;
0747 
0748     /* Spec says both ports must be in D0 before enabling PCI PM substates*/
0749     if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) {
0750         state &= ~ASPM_STATE_L1_SS_PCIPM;
0751         state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM);
0752     }
0753 
0754     /* Nothing to do if the link is already in the requested state */
0755     if (link->aspm_enabled == state)
0756         return;
0757     /* Convert ASPM state to upstream/downstream ASPM register state */
0758     if (state & ASPM_STATE_L0S_UP)
0759         dwstream |= PCI_EXP_LNKCTL_ASPM_L0S;
0760     if (state & ASPM_STATE_L0S_DW)
0761         upstream |= PCI_EXP_LNKCTL_ASPM_L0S;
0762     if (state & ASPM_STATE_L1) {
0763         upstream |= PCI_EXP_LNKCTL_ASPM_L1;
0764         dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
0765     }
0766 
0767     if (link->aspm_capable & ASPM_STATE_L1SS)
0768         pcie_config_aspm_l1ss(link, state);
0769 
0770     /*
0771      * Spec 2.0 suggests all functions should be configured the
0772      * same setting for ASPM. Enabling ASPM L1 should be done in
0773      * upstream component first and then downstream, and vice
0774      * versa for disabling ASPM L1. Spec doesn't mention L0S.
0775      */
0776     if (state & ASPM_STATE_L1)
0777         pcie_config_aspm_dev(parent, upstream);
0778     list_for_each_entry(child, &linkbus->devices, bus_list)
0779         pcie_config_aspm_dev(child, dwstream);
0780     if (!(state & ASPM_STATE_L1))
0781         pcie_config_aspm_dev(parent, upstream);
0782 
0783     link->aspm_enabled = state;
0784 }
0785 
0786 static void pcie_config_aspm_path(struct pcie_link_state *link)
0787 {
0788     while (link) {
0789         pcie_config_aspm_link(link, policy_to_aspm_state(link));
0790         link = link->parent;
0791     }
0792 }
0793 
0794 static void free_link_state(struct pcie_link_state *link)
0795 {
0796     link->pdev->link_state = NULL;
0797     kfree(link);
0798 }
0799 
0800 static int pcie_aspm_sanity_check(struct pci_dev *pdev)
0801 {
0802     struct pci_dev *child;
0803     u32 reg32;
0804 
0805     /*
0806      * Some functions in a slot might not all be PCIe functions,
0807      * very strange. Disable ASPM for the whole slot
0808      */
0809     list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
0810         if (!pci_is_pcie(child))
0811             return -EINVAL;
0812 
0813         /*
0814          * If ASPM is disabled then we're not going to change
0815          * the BIOS state. It's safe to continue even if it's a
0816          * pre-1.1 device
0817          */
0818 
0819         if (aspm_disabled)
0820             continue;
0821 
0822         /*
0823          * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
0824          * RBER bit to determine if a function is 1.1 version device
0825          */
0826         pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32);
0827         if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
0828             pci_info(child, "disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'\n");
0829             return -EINVAL;
0830         }
0831     }
0832     return 0;
0833 }
0834 
0835 static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
0836 {
0837     struct pcie_link_state *link;
0838 
0839     link = kzalloc(sizeof(*link), GFP_KERNEL);
0840     if (!link)
0841         return NULL;
0842 
0843     INIT_LIST_HEAD(&link->sibling);
0844     link->pdev = pdev;
0845     link->downstream = pci_function_0(pdev->subordinate);
0846 
0847     /*
0848      * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe
0849      * hierarchies.  Note that some PCIe host implementations omit
0850      * the root ports entirely, in which case a downstream port on
0851      * a switch may become the root of the link state chain for all
0852      * its subordinate endpoints.
0853      */
0854     if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
0855         pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE ||
0856         !pdev->bus->parent->self) {
0857         link->root = link;
0858     } else {
0859         struct pcie_link_state *parent;
0860 
0861         parent = pdev->bus->parent->self->link_state;
0862         if (!parent) {
0863             kfree(link);
0864             return NULL;
0865         }
0866 
0867         link->parent = parent;
0868         link->root = link->parent->root;
0869     }
0870 
0871     list_add(&link->sibling, &link_list);
0872     pdev->link_state = link;
0873     return link;
0874 }
0875 
0876 static void pcie_aspm_update_sysfs_visibility(struct pci_dev *pdev)
0877 {
0878     struct pci_dev *child;
0879 
0880     list_for_each_entry(child, &pdev->subordinate->devices, bus_list)
0881         sysfs_update_group(&child->dev.kobj, &aspm_ctrl_attr_group);
0882 }
0883 
0884 /*
0885  * pcie_aspm_init_link_state: Initiate PCI express link state.
0886  * It is called after the pcie and its children devices are scanned.
0887  * @pdev: the root port or switch downstream port
0888  */
0889 void pcie_aspm_init_link_state(struct pci_dev *pdev)
0890 {
0891     struct pcie_link_state *link;
0892     int blacklist = !!pcie_aspm_sanity_check(pdev);
0893 
0894     if (!aspm_support_enabled)
0895         return;
0896 
0897     if (pdev->link_state)
0898         return;
0899 
0900     /*
0901      * We allocate pcie_link_state for the component on the upstream
0902      * end of a Link, so there's nothing to do unless this device is
0903      * downstream port.
0904      */
0905     if (!pcie_downstream_port(pdev))
0906         return;
0907 
0908     /* VIA has a strange chipset, root port is under a bridge */
0909     if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT &&
0910         pdev->bus->self)
0911         return;
0912 
0913     down_read(&pci_bus_sem);
0914     if (list_empty(&pdev->subordinate->devices))
0915         goto out;
0916 
0917     mutex_lock(&aspm_lock);
0918     link = alloc_pcie_link_state(pdev);
0919     if (!link)
0920         goto unlock;
0921     /*
0922      * Setup initial ASPM state. Note that we need to configure
0923      * upstream links also because capable state of them can be
0924      * update through pcie_aspm_cap_init().
0925      */
0926     pcie_aspm_cap_init(link, blacklist);
0927 
0928     /* Setup initial Clock PM state */
0929     pcie_clkpm_cap_init(link, blacklist);
0930 
0931     /*
0932      * At this stage drivers haven't had an opportunity to change the
0933      * link policy setting. Enabling ASPM on broken hardware can cripple
0934      * it even before the driver has had a chance to disable ASPM, so
0935      * default to a safe level right now. If we're enabling ASPM beyond
0936      * the BIOS's expectation, we'll do so once pci_enable_device() is
0937      * called.
0938      */
0939     if (aspm_policy != POLICY_POWERSAVE &&
0940         aspm_policy != POLICY_POWER_SUPERSAVE) {
0941         pcie_config_aspm_path(link);
0942         pcie_set_clkpm(link, policy_to_clkpm_state(link));
0943     }
0944 
0945     pcie_aspm_update_sysfs_visibility(pdev);
0946 
0947 unlock:
0948     mutex_unlock(&aspm_lock);
0949 out:
0950     up_read(&pci_bus_sem);
0951 }
0952 
0953 /* Recheck latencies and update aspm_capable for links under the root */
0954 static void pcie_update_aspm_capable(struct pcie_link_state *root)
0955 {
0956     struct pcie_link_state *link;
0957     BUG_ON(root->parent);
0958     list_for_each_entry(link, &link_list, sibling) {
0959         if (link->root != root)
0960             continue;
0961         link->aspm_capable = link->aspm_support;
0962     }
0963     list_for_each_entry(link, &link_list, sibling) {
0964         struct pci_dev *child;
0965         struct pci_bus *linkbus = link->pdev->subordinate;
0966         if (link->root != root)
0967             continue;
0968         list_for_each_entry(child, &linkbus->devices, bus_list) {
0969             if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) &&
0970                 (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END))
0971                 continue;
0972             pcie_aspm_check_latency(child);
0973         }
0974     }
0975 }
0976 
0977 /* @pdev: the endpoint device */
0978 void pcie_aspm_exit_link_state(struct pci_dev *pdev)
0979 {
0980     struct pci_dev *parent = pdev->bus->self;
0981     struct pcie_link_state *link, *root, *parent_link;
0982 
0983     if (!parent || !parent->link_state)
0984         return;
0985 
0986     down_read(&pci_bus_sem);
0987     mutex_lock(&aspm_lock);
0988     /*
0989      * All PCIe functions are in one slot, remove one function will remove
0990      * the whole slot, so just wait until we are the last function left.
0991      */
0992     if (!list_empty(&parent->subordinate->devices))
0993         goto out;
0994 
0995     link = parent->link_state;
0996     root = link->root;
0997     parent_link = link->parent;
0998 
0999     /* All functions are removed, so just disable ASPM for the link */
1000     pcie_config_aspm_link(link, 0);
1001     list_del(&link->sibling);
1002     /* Clock PM is for endpoint device */
1003     free_link_state(link);
1004 
1005     /* Recheck latencies and configure upstream links */
1006     if (parent_link) {
1007         pcie_update_aspm_capable(root);
1008         pcie_config_aspm_path(parent_link);
1009     }
1010 out:
1011     mutex_unlock(&aspm_lock);
1012     up_read(&pci_bus_sem);
1013 }
1014 
1015 void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
1016 {
1017     struct pcie_link_state *link = pdev->link_state;
1018 
1019     if (aspm_disabled || !link)
1020         return;
1021 
1022     if (aspm_policy != POLICY_POWERSAVE &&
1023         aspm_policy != POLICY_POWER_SUPERSAVE)
1024         return;
1025 
1026     down_read(&pci_bus_sem);
1027     mutex_lock(&aspm_lock);
1028     pcie_config_aspm_path(link);
1029     pcie_set_clkpm(link, policy_to_clkpm_state(link));
1030     mutex_unlock(&aspm_lock);
1031     up_read(&pci_bus_sem);
1032 }
1033 
1034 static struct pcie_link_state *pcie_aspm_get_link(struct pci_dev *pdev)
1035 {
1036     struct pci_dev *bridge;
1037 
1038     if (!pci_is_pcie(pdev))
1039         return NULL;
1040 
1041     bridge = pci_upstream_bridge(pdev);
1042     if (!bridge || !pci_is_pcie(bridge))
1043         return NULL;
1044 
1045     return bridge->link_state;
1046 }
1047 
1048 static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
1049 {
1050     struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1051 
1052     if (!link)
1053         return -EINVAL;
1054     /*
1055      * A driver requested that ASPM be disabled on this device, but
1056      * if we don't have permission to manage ASPM (e.g., on ACPI
1057      * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
1058      * the _OSC method), we can't honor that request.  Windows has
1059      * a similar mechanism using "PciASPMOptOut", which is also
1060      * ignored in this situation.
1061      */
1062     if (aspm_disabled) {
1063         pci_warn(pdev, "can't disable ASPM; OS doesn't have ASPM control\n");
1064         return -EPERM;
1065     }
1066 
1067     if (sem)
1068         down_read(&pci_bus_sem);
1069     mutex_lock(&aspm_lock);
1070     if (state & PCIE_LINK_STATE_L0S)
1071         link->aspm_disable |= ASPM_STATE_L0S;
1072     if (state & PCIE_LINK_STATE_L1)
1073         /* L1 PM substates require L1 */
1074         link->aspm_disable |= ASPM_STATE_L1 | ASPM_STATE_L1SS;
1075     if (state & PCIE_LINK_STATE_L1_1)
1076         link->aspm_disable |= ASPM_STATE_L1_1;
1077     if (state & PCIE_LINK_STATE_L1_2)
1078         link->aspm_disable |= ASPM_STATE_L1_2;
1079     if (state & PCIE_LINK_STATE_L1_1_PCIPM)
1080         link->aspm_disable |= ASPM_STATE_L1_1_PCIPM;
1081     if (state & PCIE_LINK_STATE_L1_2_PCIPM)
1082         link->aspm_disable |= ASPM_STATE_L1_2_PCIPM;
1083     pcie_config_aspm_link(link, policy_to_aspm_state(link));
1084 
1085     if (state & PCIE_LINK_STATE_CLKPM)
1086         link->clkpm_disable = 1;
1087     pcie_set_clkpm(link, policy_to_clkpm_state(link));
1088     mutex_unlock(&aspm_lock);
1089     if (sem)
1090         up_read(&pci_bus_sem);
1091 
1092     return 0;
1093 }
1094 
1095 int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1096 {
1097     return __pci_disable_link_state(pdev, state, false);
1098 }
1099 EXPORT_SYMBOL(pci_disable_link_state_locked);
1100 
1101 /**
1102  * pci_disable_link_state - Disable device's link state, so the link will
1103  * never enter specific states.  Note that if the BIOS didn't grant ASPM
1104  * control to the OS, this does nothing because we can't touch the LNKCTL
1105  * register. Returns 0 or a negative errno.
1106  *
1107  * @pdev: PCI device
1108  * @state: ASPM link state to disable
1109  */
1110 int pci_disable_link_state(struct pci_dev *pdev, int state)
1111 {
1112     return __pci_disable_link_state(pdev, state, true);
1113 }
1114 EXPORT_SYMBOL(pci_disable_link_state);
1115 
1116 static int pcie_aspm_set_policy(const char *val,
1117                 const struct kernel_param *kp)
1118 {
1119     int i;
1120     struct pcie_link_state *link;
1121 
1122     if (aspm_disabled)
1123         return -EPERM;
1124     i = sysfs_match_string(policy_str, val);
1125     if (i < 0)
1126         return i;
1127     if (i == aspm_policy)
1128         return 0;
1129 
1130     down_read(&pci_bus_sem);
1131     mutex_lock(&aspm_lock);
1132     aspm_policy = i;
1133     list_for_each_entry(link, &link_list, sibling) {
1134         pcie_config_aspm_link(link, policy_to_aspm_state(link));
1135         pcie_set_clkpm(link, policy_to_clkpm_state(link));
1136     }
1137     mutex_unlock(&aspm_lock);
1138     up_read(&pci_bus_sem);
1139     return 0;
1140 }
1141 
1142 static int pcie_aspm_get_policy(char *buffer, const struct kernel_param *kp)
1143 {
1144     int i, cnt = 0;
1145     for (i = 0; i < ARRAY_SIZE(policy_str); i++)
1146         if (i == aspm_policy)
1147             cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
1148         else
1149             cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
1150     cnt += sprintf(buffer + cnt, "\n");
1151     return cnt;
1152 }
1153 
1154 module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
1155     NULL, 0644);
1156 
1157 /**
1158  * pcie_aspm_enabled - Check if PCIe ASPM has been enabled for a device.
1159  * @pdev: Target device.
1160  *
1161  * Relies on the upstream bridge's link_state being valid.  The link_state
1162  * is deallocated only when the last child of the bridge (i.e., @pdev or a
1163  * sibling) is removed, and the caller should be holding a reference to
1164  * @pdev, so this should be safe.
1165  */
1166 bool pcie_aspm_enabled(struct pci_dev *pdev)
1167 {
1168     struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1169 
1170     if (!link)
1171         return false;
1172 
1173     return link->aspm_enabled;
1174 }
1175 EXPORT_SYMBOL_GPL(pcie_aspm_enabled);
1176 
1177 static ssize_t aspm_attr_show_common(struct device *dev,
1178                      struct device_attribute *attr,
1179                      char *buf, u8 state)
1180 {
1181     struct pci_dev *pdev = to_pci_dev(dev);
1182     struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1183 
1184     return sysfs_emit(buf, "%d\n", (link->aspm_enabled & state) ? 1 : 0);
1185 }
1186 
1187 static ssize_t aspm_attr_store_common(struct device *dev,
1188                       struct device_attribute *attr,
1189                       const char *buf, size_t len, u8 state)
1190 {
1191     struct pci_dev *pdev = to_pci_dev(dev);
1192     struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1193     bool state_enable;
1194 
1195     if (kstrtobool(buf, &state_enable) < 0)
1196         return -EINVAL;
1197 
1198     down_read(&pci_bus_sem);
1199     mutex_lock(&aspm_lock);
1200 
1201     if (state_enable) {
1202         link->aspm_disable &= ~state;
1203         /* need to enable L1 for substates */
1204         if (state & ASPM_STATE_L1SS)
1205             link->aspm_disable &= ~ASPM_STATE_L1;
1206     } else {
1207         link->aspm_disable |= state;
1208     }
1209 
1210     pcie_config_aspm_link(link, policy_to_aspm_state(link));
1211 
1212     mutex_unlock(&aspm_lock);
1213     up_read(&pci_bus_sem);
1214 
1215     return len;
1216 }
1217 
1218 #define ASPM_ATTR(_f, _s)                       \
1219 static ssize_t _f##_show(struct device *dev,                \
1220              struct device_attribute *attr, char *buf)  \
1221 { return aspm_attr_show_common(dev, attr, buf, ASPM_STATE_##_s); }  \
1222                                     \
1223 static ssize_t _f##_store(struct device *dev,               \
1224               struct device_attribute *attr,        \
1225               const char *buf, size_t len)          \
1226 { return aspm_attr_store_common(dev, attr, buf, len, ASPM_STATE_##_s); }
1227 
1228 ASPM_ATTR(l0s_aspm, L0S)
1229 ASPM_ATTR(l1_aspm, L1)
1230 ASPM_ATTR(l1_1_aspm, L1_1)
1231 ASPM_ATTR(l1_2_aspm, L1_2)
1232 ASPM_ATTR(l1_1_pcipm, L1_1_PCIPM)
1233 ASPM_ATTR(l1_2_pcipm, L1_2_PCIPM)
1234 
1235 static ssize_t clkpm_show(struct device *dev,
1236               struct device_attribute *attr, char *buf)
1237 {
1238     struct pci_dev *pdev = to_pci_dev(dev);
1239     struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1240 
1241     return sysfs_emit(buf, "%d\n", link->clkpm_enabled);
1242 }
1243 
1244 static ssize_t clkpm_store(struct device *dev,
1245                struct device_attribute *attr,
1246                const char *buf, size_t len)
1247 {
1248     struct pci_dev *pdev = to_pci_dev(dev);
1249     struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1250     bool state_enable;
1251 
1252     if (kstrtobool(buf, &state_enable) < 0)
1253         return -EINVAL;
1254 
1255     down_read(&pci_bus_sem);
1256     mutex_lock(&aspm_lock);
1257 
1258     link->clkpm_disable = !state_enable;
1259     pcie_set_clkpm(link, policy_to_clkpm_state(link));
1260 
1261     mutex_unlock(&aspm_lock);
1262     up_read(&pci_bus_sem);
1263 
1264     return len;
1265 }
1266 
1267 static DEVICE_ATTR_RW(clkpm);
1268 static DEVICE_ATTR_RW(l0s_aspm);
1269 static DEVICE_ATTR_RW(l1_aspm);
1270 static DEVICE_ATTR_RW(l1_1_aspm);
1271 static DEVICE_ATTR_RW(l1_2_aspm);
1272 static DEVICE_ATTR_RW(l1_1_pcipm);
1273 static DEVICE_ATTR_RW(l1_2_pcipm);
1274 
1275 static struct attribute *aspm_ctrl_attrs[] = {
1276     &dev_attr_clkpm.attr,
1277     &dev_attr_l0s_aspm.attr,
1278     &dev_attr_l1_aspm.attr,
1279     &dev_attr_l1_1_aspm.attr,
1280     &dev_attr_l1_2_aspm.attr,
1281     &dev_attr_l1_1_pcipm.attr,
1282     &dev_attr_l1_2_pcipm.attr,
1283     NULL
1284 };
1285 
1286 static umode_t aspm_ctrl_attrs_are_visible(struct kobject *kobj,
1287                        struct attribute *a, int n)
1288 {
1289     struct device *dev = kobj_to_dev(kobj);
1290     struct pci_dev *pdev = to_pci_dev(dev);
1291     struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1292     static const u8 aspm_state_map[] = {
1293         ASPM_STATE_L0S,
1294         ASPM_STATE_L1,
1295         ASPM_STATE_L1_1,
1296         ASPM_STATE_L1_2,
1297         ASPM_STATE_L1_1_PCIPM,
1298         ASPM_STATE_L1_2_PCIPM,
1299     };
1300 
1301     if (aspm_disabled || !link)
1302         return 0;
1303 
1304     if (n == 0)
1305         return link->clkpm_capable ? a->mode : 0;
1306 
1307     return link->aspm_capable & aspm_state_map[n - 1] ? a->mode : 0;
1308 }
1309 
1310 const struct attribute_group aspm_ctrl_attr_group = {
1311     .name = "link",
1312     .attrs = aspm_ctrl_attrs,
1313     .is_visible = aspm_ctrl_attrs_are_visible,
1314 };
1315 
1316 static int __init pcie_aspm_disable(char *str)
1317 {
1318     if (!strcmp(str, "off")) {
1319         aspm_policy = POLICY_DEFAULT;
1320         aspm_disabled = 1;
1321         aspm_support_enabled = false;
1322         printk(KERN_INFO "PCIe ASPM is disabled\n");
1323     } else if (!strcmp(str, "force")) {
1324         aspm_force = 1;
1325         printk(KERN_INFO "PCIe ASPM is forcibly enabled\n");
1326     }
1327     return 1;
1328 }
1329 
1330 __setup("pcie_aspm=", pcie_aspm_disable);
1331 
1332 void pcie_no_aspm(void)
1333 {
1334     /*
1335      * Disabling ASPM is intended to prevent the kernel from modifying
1336      * existing hardware state, not to clear existing state. To that end:
1337      * (a) set policy to POLICY_DEFAULT in order to avoid changing state
1338      * (b) prevent userspace from changing policy
1339      */
1340     if (!aspm_force) {
1341         aspm_policy = POLICY_DEFAULT;
1342         aspm_disabled = 1;
1343     }
1344 }
1345 
1346 bool pcie_aspm_support_enabled(void)
1347 {
1348     return aspm_support_enabled;
1349 }
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!