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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * PCIe AER software error injection support.
0004  *
0005  * Debugging PCIe AER code is quite difficult because it is hard to
0006  * trigger various real hardware errors. Software based error
0007  * injection can fake almost all kinds of errors with the help of a
0008  * user space helper tool aer-inject, which can be gotten from:
0009  *   https://git.kernel.org/cgit/linux/kernel/git/gong.chen/aer-inject.git/
0010  *
0011  * Copyright 2009 Intel Corporation.
0012  *     Huang Ying <ying.huang@intel.com>
0013  */
0014 
0015 #define dev_fmt(fmt) "aer_inject: " fmt
0016 
0017 #include <linux/module.h>
0018 #include <linux/init.h>
0019 #include <linux/interrupt.h>
0020 #include <linux/miscdevice.h>
0021 #include <linux/pci.h>
0022 #include <linux/slab.h>
0023 #include <linux/fs.h>
0024 #include <linux/uaccess.h>
0025 #include <linux/stddef.h>
0026 #include <linux/device.h>
0027 
0028 #include "portdrv.h"
0029 
0030 /* Override the existing corrected and uncorrected error masks */
0031 static bool aer_mask_override;
0032 module_param(aer_mask_override, bool, 0);
0033 
0034 struct aer_error_inj {
0035     u8 bus;
0036     u8 dev;
0037     u8 fn;
0038     u32 uncor_status;
0039     u32 cor_status;
0040     u32 header_log0;
0041     u32 header_log1;
0042     u32 header_log2;
0043     u32 header_log3;
0044     u32 domain;
0045 };
0046 
0047 struct aer_error {
0048     struct list_head list;
0049     u32 domain;
0050     unsigned int bus;
0051     unsigned int devfn;
0052     int pos_cap_err;
0053 
0054     u32 uncor_status;
0055     u32 cor_status;
0056     u32 header_log0;
0057     u32 header_log1;
0058     u32 header_log2;
0059     u32 header_log3;
0060     u32 root_status;
0061     u32 source_id;
0062 };
0063 
0064 struct pci_bus_ops {
0065     struct list_head list;
0066     struct pci_bus *bus;
0067     struct pci_ops *ops;
0068 };
0069 
0070 static LIST_HEAD(einjected);
0071 
0072 static LIST_HEAD(pci_bus_ops_list);
0073 
0074 /* Protect einjected and pci_bus_ops_list */
0075 static DEFINE_SPINLOCK(inject_lock);
0076 
0077 static void aer_error_init(struct aer_error *err, u32 domain,
0078                unsigned int bus, unsigned int devfn,
0079                int pos_cap_err)
0080 {
0081     INIT_LIST_HEAD(&err->list);
0082     err->domain = domain;
0083     err->bus = bus;
0084     err->devfn = devfn;
0085     err->pos_cap_err = pos_cap_err;
0086 }
0087 
0088 /* inject_lock must be held before calling */
0089 static struct aer_error *__find_aer_error(u32 domain, unsigned int bus,
0090                       unsigned int devfn)
0091 {
0092     struct aer_error *err;
0093 
0094     list_for_each_entry(err, &einjected, list) {
0095         if (domain == err->domain &&
0096             bus == err->bus &&
0097             devfn == err->devfn)
0098             return err;
0099     }
0100     return NULL;
0101 }
0102 
0103 /* inject_lock must be held before calling */
0104 static struct aer_error *__find_aer_error_by_dev(struct pci_dev *dev)
0105 {
0106     int domain = pci_domain_nr(dev->bus);
0107     if (domain < 0)
0108         return NULL;
0109     return __find_aer_error(domain, dev->bus->number, dev->devfn);
0110 }
0111 
0112 /* inject_lock must be held before calling */
0113 static struct pci_ops *__find_pci_bus_ops(struct pci_bus *bus)
0114 {
0115     struct pci_bus_ops *bus_ops;
0116 
0117     list_for_each_entry(bus_ops, &pci_bus_ops_list, list) {
0118         if (bus_ops->bus == bus)
0119             return bus_ops->ops;
0120     }
0121     return NULL;
0122 }
0123 
0124 static struct pci_bus_ops *pci_bus_ops_pop(void)
0125 {
0126     unsigned long flags;
0127     struct pci_bus_ops *bus_ops;
0128 
0129     spin_lock_irqsave(&inject_lock, flags);
0130     bus_ops = list_first_entry_or_null(&pci_bus_ops_list,
0131                        struct pci_bus_ops, list);
0132     if (bus_ops)
0133         list_del(&bus_ops->list);
0134     spin_unlock_irqrestore(&inject_lock, flags);
0135     return bus_ops;
0136 }
0137 
0138 static u32 *find_pci_config_dword(struct aer_error *err, int where,
0139                   int *prw1cs)
0140 {
0141     int rw1cs = 0;
0142     u32 *target = NULL;
0143 
0144     if (err->pos_cap_err == -1)
0145         return NULL;
0146 
0147     switch (where - err->pos_cap_err) {
0148     case PCI_ERR_UNCOR_STATUS:
0149         target = &err->uncor_status;
0150         rw1cs = 1;
0151         break;
0152     case PCI_ERR_COR_STATUS:
0153         target = &err->cor_status;
0154         rw1cs = 1;
0155         break;
0156     case PCI_ERR_HEADER_LOG:
0157         target = &err->header_log0;
0158         break;
0159     case PCI_ERR_HEADER_LOG+4:
0160         target = &err->header_log1;
0161         break;
0162     case PCI_ERR_HEADER_LOG+8:
0163         target = &err->header_log2;
0164         break;
0165     case PCI_ERR_HEADER_LOG+12:
0166         target = &err->header_log3;
0167         break;
0168     case PCI_ERR_ROOT_STATUS:
0169         target = &err->root_status;
0170         rw1cs = 1;
0171         break;
0172     case PCI_ERR_ROOT_ERR_SRC:
0173         target = &err->source_id;
0174         break;
0175     }
0176     if (prw1cs)
0177         *prw1cs = rw1cs;
0178     return target;
0179 }
0180 
0181 static int aer_inj_read(struct pci_bus *bus, unsigned int devfn, int where,
0182             int size, u32 *val)
0183 {
0184     struct pci_ops *ops, *my_ops;
0185     int rv;
0186 
0187     ops = __find_pci_bus_ops(bus);
0188     if (!ops)
0189         return -1;
0190 
0191     my_ops = bus->ops;
0192     bus->ops = ops;
0193     rv = ops->read(bus, devfn, where, size, val);
0194     bus->ops = my_ops;
0195 
0196     return rv;
0197 }
0198 
0199 static int aer_inj_write(struct pci_bus *bus, unsigned int devfn, int where,
0200              int size, u32 val)
0201 {
0202     struct pci_ops *ops, *my_ops;
0203     int rv;
0204 
0205     ops = __find_pci_bus_ops(bus);
0206     if (!ops)
0207         return -1;
0208 
0209     my_ops = bus->ops;
0210     bus->ops = ops;
0211     rv = ops->write(bus, devfn, where, size, val);
0212     bus->ops = my_ops;
0213 
0214     return rv;
0215 }
0216 
0217 static int aer_inj_read_config(struct pci_bus *bus, unsigned int devfn,
0218                    int where, int size, u32 *val)
0219 {
0220     u32 *sim;
0221     struct aer_error *err;
0222     unsigned long flags;
0223     int domain;
0224     int rv;
0225 
0226     spin_lock_irqsave(&inject_lock, flags);
0227     if (size != sizeof(u32))
0228         goto out;
0229     domain = pci_domain_nr(bus);
0230     if (domain < 0)
0231         goto out;
0232     err = __find_aer_error(domain, bus->number, devfn);
0233     if (!err)
0234         goto out;
0235 
0236     sim = find_pci_config_dword(err, where, NULL);
0237     if (sim) {
0238         *val = *sim;
0239         spin_unlock_irqrestore(&inject_lock, flags);
0240         return 0;
0241     }
0242 out:
0243     rv = aer_inj_read(bus, devfn, where, size, val);
0244     spin_unlock_irqrestore(&inject_lock, flags);
0245     return rv;
0246 }
0247 
0248 static int aer_inj_write_config(struct pci_bus *bus, unsigned int devfn,
0249                 int where, int size, u32 val)
0250 {
0251     u32 *sim;
0252     struct aer_error *err;
0253     unsigned long flags;
0254     int rw1cs;
0255     int domain;
0256     int rv;
0257 
0258     spin_lock_irqsave(&inject_lock, flags);
0259     if (size != sizeof(u32))
0260         goto out;
0261     domain = pci_domain_nr(bus);
0262     if (domain < 0)
0263         goto out;
0264     err = __find_aer_error(domain, bus->number, devfn);
0265     if (!err)
0266         goto out;
0267 
0268     sim = find_pci_config_dword(err, where, &rw1cs);
0269     if (sim) {
0270         if (rw1cs)
0271             *sim ^= val;
0272         else
0273             *sim = val;
0274         spin_unlock_irqrestore(&inject_lock, flags);
0275         return 0;
0276     }
0277 out:
0278     rv = aer_inj_write(bus, devfn, where, size, val);
0279     spin_unlock_irqrestore(&inject_lock, flags);
0280     return rv;
0281 }
0282 
0283 static struct pci_ops aer_inj_pci_ops = {
0284     .read = aer_inj_read_config,
0285     .write = aer_inj_write_config,
0286 };
0287 
0288 static void pci_bus_ops_init(struct pci_bus_ops *bus_ops,
0289                  struct pci_bus *bus,
0290                  struct pci_ops *ops)
0291 {
0292     INIT_LIST_HEAD(&bus_ops->list);
0293     bus_ops->bus = bus;
0294     bus_ops->ops = ops;
0295 }
0296 
0297 static int pci_bus_set_aer_ops(struct pci_bus *bus)
0298 {
0299     struct pci_ops *ops;
0300     struct pci_bus_ops *bus_ops;
0301     unsigned long flags;
0302 
0303     bus_ops = kmalloc(sizeof(*bus_ops), GFP_KERNEL);
0304     if (!bus_ops)
0305         return -ENOMEM;
0306     ops = pci_bus_set_ops(bus, &aer_inj_pci_ops);
0307     spin_lock_irqsave(&inject_lock, flags);
0308     if (ops == &aer_inj_pci_ops)
0309         goto out;
0310     pci_bus_ops_init(bus_ops, bus, ops);
0311     list_add(&bus_ops->list, &pci_bus_ops_list);
0312     bus_ops = NULL;
0313 out:
0314     spin_unlock_irqrestore(&inject_lock, flags);
0315     kfree(bus_ops);
0316     return 0;
0317 }
0318 
0319 static int aer_inject(struct aer_error_inj *einj)
0320 {
0321     struct aer_error *err, *rperr;
0322     struct aer_error *err_alloc = NULL, *rperr_alloc = NULL;
0323     struct pci_dev *dev, *rpdev;
0324     struct pcie_device *edev;
0325     struct device *device;
0326     unsigned long flags;
0327     unsigned int devfn = PCI_DEVFN(einj->dev, einj->fn);
0328     int pos_cap_err, rp_pos_cap_err;
0329     u32 sever, cor_mask, uncor_mask, cor_mask_orig = 0, uncor_mask_orig = 0;
0330     int ret = 0;
0331 
0332     dev = pci_get_domain_bus_and_slot(einj->domain, einj->bus, devfn);
0333     if (!dev)
0334         return -ENODEV;
0335     rpdev = pcie_find_root_port(dev);
0336     /* If Root Port not found, try to find an RCEC */
0337     if (!rpdev)
0338         rpdev = dev->rcec;
0339     if (!rpdev) {
0340         pci_err(dev, "Neither Root Port nor RCEC found\n");
0341         ret = -ENODEV;
0342         goto out_put;
0343     }
0344 
0345     pos_cap_err = dev->aer_cap;
0346     if (!pos_cap_err) {
0347         pci_err(dev, "Device doesn't support AER\n");
0348         ret = -EPROTONOSUPPORT;
0349         goto out_put;
0350     }
0351     pci_read_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_SEVER, &sever);
0352     pci_read_config_dword(dev, pos_cap_err + PCI_ERR_COR_MASK, &cor_mask);
0353     pci_read_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_MASK,
0354                   &uncor_mask);
0355 
0356     rp_pos_cap_err = rpdev->aer_cap;
0357     if (!rp_pos_cap_err) {
0358         pci_err(rpdev, "Root port doesn't support AER\n");
0359         ret = -EPROTONOSUPPORT;
0360         goto out_put;
0361     }
0362 
0363     err_alloc =  kzalloc(sizeof(struct aer_error), GFP_KERNEL);
0364     if (!err_alloc) {
0365         ret = -ENOMEM;
0366         goto out_put;
0367     }
0368     rperr_alloc =  kzalloc(sizeof(struct aer_error), GFP_KERNEL);
0369     if (!rperr_alloc) {
0370         ret = -ENOMEM;
0371         goto out_put;
0372     }
0373 
0374     if (aer_mask_override) {
0375         cor_mask_orig = cor_mask;
0376         cor_mask &= !(einj->cor_status);
0377         pci_write_config_dword(dev, pos_cap_err + PCI_ERR_COR_MASK,
0378                        cor_mask);
0379 
0380         uncor_mask_orig = uncor_mask;
0381         uncor_mask &= !(einj->uncor_status);
0382         pci_write_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_MASK,
0383                        uncor_mask);
0384     }
0385 
0386     spin_lock_irqsave(&inject_lock, flags);
0387 
0388     err = __find_aer_error_by_dev(dev);
0389     if (!err) {
0390         err = err_alloc;
0391         err_alloc = NULL;
0392         aer_error_init(err, einj->domain, einj->bus, devfn,
0393                    pos_cap_err);
0394         list_add(&err->list, &einjected);
0395     }
0396     err->uncor_status |= einj->uncor_status;
0397     err->cor_status |= einj->cor_status;
0398     err->header_log0 = einj->header_log0;
0399     err->header_log1 = einj->header_log1;
0400     err->header_log2 = einj->header_log2;
0401     err->header_log3 = einj->header_log3;
0402 
0403     if (!aer_mask_override && einj->cor_status &&
0404         !(einj->cor_status & ~cor_mask)) {
0405         ret = -EINVAL;
0406         pci_warn(dev, "The correctable error(s) is masked by device\n");
0407         spin_unlock_irqrestore(&inject_lock, flags);
0408         goto out_put;
0409     }
0410     if (!aer_mask_override && einj->uncor_status &&
0411         !(einj->uncor_status & ~uncor_mask)) {
0412         ret = -EINVAL;
0413         pci_warn(dev, "The uncorrectable error(s) is masked by device\n");
0414         spin_unlock_irqrestore(&inject_lock, flags);
0415         goto out_put;
0416     }
0417 
0418     rperr = __find_aer_error_by_dev(rpdev);
0419     if (!rperr) {
0420         rperr = rperr_alloc;
0421         rperr_alloc = NULL;
0422         aer_error_init(rperr, pci_domain_nr(rpdev->bus),
0423                    rpdev->bus->number, rpdev->devfn,
0424                    rp_pos_cap_err);
0425         list_add(&rperr->list, &einjected);
0426     }
0427     if (einj->cor_status) {
0428         if (rperr->root_status & PCI_ERR_ROOT_COR_RCV)
0429             rperr->root_status |= PCI_ERR_ROOT_MULTI_COR_RCV;
0430         else
0431             rperr->root_status |= PCI_ERR_ROOT_COR_RCV;
0432         rperr->source_id &= 0xffff0000;
0433         rperr->source_id |= (einj->bus << 8) | devfn;
0434     }
0435     if (einj->uncor_status) {
0436         if (rperr->root_status & PCI_ERR_ROOT_UNCOR_RCV)
0437             rperr->root_status |= PCI_ERR_ROOT_MULTI_UNCOR_RCV;
0438         if (sever & einj->uncor_status) {
0439             rperr->root_status |= PCI_ERR_ROOT_FATAL_RCV;
0440             if (!(rperr->root_status & PCI_ERR_ROOT_UNCOR_RCV))
0441                 rperr->root_status |= PCI_ERR_ROOT_FIRST_FATAL;
0442         } else
0443             rperr->root_status |= PCI_ERR_ROOT_NONFATAL_RCV;
0444         rperr->root_status |= PCI_ERR_ROOT_UNCOR_RCV;
0445         rperr->source_id &= 0x0000ffff;
0446         rperr->source_id |= ((einj->bus << 8) | devfn) << 16;
0447     }
0448     spin_unlock_irqrestore(&inject_lock, flags);
0449 
0450     if (aer_mask_override) {
0451         pci_write_config_dword(dev, pos_cap_err + PCI_ERR_COR_MASK,
0452                        cor_mask_orig);
0453         pci_write_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_MASK,
0454                        uncor_mask_orig);
0455     }
0456 
0457     ret = pci_bus_set_aer_ops(dev->bus);
0458     if (ret)
0459         goto out_put;
0460     ret = pci_bus_set_aer_ops(rpdev->bus);
0461     if (ret)
0462         goto out_put;
0463 
0464     device = pcie_port_find_device(rpdev, PCIE_PORT_SERVICE_AER);
0465     if (device) {
0466         edev = to_pcie_device(device);
0467         if (!get_service_data(edev)) {
0468             pci_warn(edev->port, "AER service is not initialized\n");
0469             ret = -EPROTONOSUPPORT;
0470             goto out_put;
0471         }
0472         pci_info(edev->port, "Injecting errors %08x/%08x into device %s\n",
0473              einj->cor_status, einj->uncor_status, pci_name(dev));
0474         ret = irq_inject_interrupt(edev->irq);
0475     } else {
0476         pci_err(rpdev, "AER device not found\n");
0477         ret = -ENODEV;
0478     }
0479 out_put:
0480     kfree(err_alloc);
0481     kfree(rperr_alloc);
0482     pci_dev_put(dev);
0483     return ret;
0484 }
0485 
0486 static ssize_t aer_inject_write(struct file *filp, const char __user *ubuf,
0487                 size_t usize, loff_t *off)
0488 {
0489     struct aer_error_inj einj;
0490     int ret;
0491 
0492     if (!capable(CAP_SYS_ADMIN))
0493         return -EPERM;
0494     if (usize < offsetof(struct aer_error_inj, domain) ||
0495         usize > sizeof(einj))
0496         return -EINVAL;
0497 
0498     memset(&einj, 0, sizeof(einj));
0499     if (copy_from_user(&einj, ubuf, usize))
0500         return -EFAULT;
0501 
0502     ret = aer_inject(&einj);
0503     return ret ? ret : usize;
0504 }
0505 
0506 static const struct file_operations aer_inject_fops = {
0507     .write = aer_inject_write,
0508     .owner = THIS_MODULE,
0509     .llseek = noop_llseek,
0510 };
0511 
0512 static struct miscdevice aer_inject_device = {
0513     .minor = MISC_DYNAMIC_MINOR,
0514     .name = "aer_inject",
0515     .fops = &aer_inject_fops,
0516 };
0517 
0518 static int __init aer_inject_init(void)
0519 {
0520     return misc_register(&aer_inject_device);
0521 }
0522 
0523 static void __exit aer_inject_exit(void)
0524 {
0525     struct aer_error *err, *err_next;
0526     unsigned long flags;
0527     struct pci_bus_ops *bus_ops;
0528 
0529     misc_deregister(&aer_inject_device);
0530 
0531     while ((bus_ops = pci_bus_ops_pop())) {
0532         pci_bus_set_ops(bus_ops->bus, bus_ops->ops);
0533         kfree(bus_ops);
0534     }
0535 
0536     spin_lock_irqsave(&inject_lock, flags);
0537     list_for_each_entry_safe(err, err_next, &einjected, list) {
0538         list_del(&err->list);
0539         kfree(err);
0540     }
0541     spin_unlock_irqrestore(&inject_lock, flags);
0542 }
0543 
0544 module_init(aer_inject_init);
0545 module_exit(aer_inject_exit);
0546 
0547 MODULE_DESCRIPTION("PCIe AER software error injector");
0548 MODULE_LICENSE("GPL");
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