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0001 # SPDX-License-Identifier: GPL-2.0
0002 #
0003 # PCI Express Port Bus Configuration
0004 #
0005 config PCIEPORTBUS
0006         bool "PCI Express Port Bus support"
0007         help
0008           This enables PCI Express Port Bus support. Users can then enable
0009           support for Native Hot-Plug, Advanced Error Reporting, Power
0010           Management Events, and Downstream Port Containment.
0011 
0012 #
0013 # Include service Kconfig here
0014 #
0015 config HOTPLUG_PCI_PCIE
0016         bool "PCI Express Hotplug driver"
0017         depends on HOTPLUG_PCI && PCIEPORTBUS
0018         help
0019           Say Y here if you have a motherboard that supports PCI Express Native
0020           Hotplug
0021 
0022           When in doubt, say N.
0023 
0024 config PCIEAER
0025         bool "PCI Express Advanced Error Reporting support"
0026         depends on PCIEPORTBUS
0027         select RAS
0028         help
0029           This enables PCI Express Root Port Advanced Error Reporting
0030           (AER) driver support. Error reporting messages sent to Root
0031           Port will be handled by PCI Express AER driver.
0032 
0033 config PCIEAER_INJECT
0034         tristate "PCI Express error injection support"
0035         depends on PCIEAER
0036         select GENERIC_IRQ_INJECTION
0037         help
0038           This enables PCI Express Root Port Advanced Error Reporting
0039           (AER) software error injector.
0040 
0041           Debugging AER code is quite difficult because it is hard
0042           to trigger various real hardware errors. Software-based
0043           error injection can fake almost all kinds of errors with the
0044           help of a user space helper tool aer-inject, which can be
0045           gotten from:
0046              https://git.kernel.org/cgit/linux/kernel/git/gong.chen/aer-inject.git/
0047 
0048 #
0049 # PCI Express ECRC
0050 #
0051 config PCIE_ECRC
0052         bool "PCI Express ECRC settings control"
0053         depends on PCIEAER
0054         help
0055           Used to override firmware/bios settings for PCI Express ECRC
0056           (transaction layer end-to-end CRC checking).
0057 
0058           When in doubt, say N.
0059 
0060 #
0061 # PCI Express ASPM
0062 #
0063 config PCIEASPM
0064         bool "PCI Express ASPM control" if EXPERT
0065         default y
0066         help
0067           This enables OS control over PCI Express ASPM (Active State
0068           Power Management) and Clock Power Management. ASPM supports
0069           state L0/L0s/L1.
0070 
0071           ASPM is initially set up by the firmware. With this option enabled,
0072           Linux can modify this state in order to disable ASPM on known-bad
0073           hardware or configurations and enable it when known-safe.
0074 
0075           ASPM can be disabled or enabled at runtime via
0076           /sys/module/pcie_aspm/parameters/policy
0077 
0078           When in doubt, say Y.
0079 
0080 choice
0081         prompt "Default ASPM policy"
0082         default PCIEASPM_DEFAULT
0083         depends on PCIEASPM
0084 
0085 config PCIEASPM_DEFAULT
0086         bool "BIOS default"
0087         depends on PCIEASPM
0088         help
0089           Use the BIOS defaults for PCI Express ASPM.
0090 
0091 config PCIEASPM_POWERSAVE
0092         bool "Powersave"
0093         depends on PCIEASPM
0094         help
0095           Enable PCI Express ASPM L0s and L1 where possible, even if the
0096           BIOS did not.
0097 
0098 config PCIEASPM_POWER_SUPERSAVE
0099         bool "Power Supersave"
0100         depends on PCIEASPM
0101         help
0102           Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where
0103           possible. This would result in higher power savings while staying in L1
0104           where the components support it.
0105 
0106 config PCIEASPM_PERFORMANCE
0107         bool "Performance"
0108         depends on PCIEASPM
0109         help
0110           Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them.
0111 endchoice
0112 
0113 config PCIE_PME
0114         def_bool y
0115         depends on PCIEPORTBUS && PM
0116 
0117 config PCIE_DPC
0118         bool "PCI Express Downstream Port Containment support"
0119         depends on PCIEPORTBUS && PCIEAER
0120         help
0121           This enables PCI Express Downstream Port Containment (DPC)
0122           driver support.  DPC events from Root and Downstream ports
0123           will be handled by the DPC driver.  If your system doesn't
0124           have this capability or you do not want to use this feature,
0125           it is safe to answer N.
0126 
0127 config PCIE_PTM
0128         bool "PCI Express Precision Time Measurement support"
0129         help
0130           This enables PCI Express Precision Time Measurement (PTM)
0131           support.
0132 
0133           This is only useful if you have devices that support PTM, but it
0134           is safe to enable even if you don't.
0135 
0136 config PCIE_EDR
0137         bool "PCI Express Error Disconnect Recover support"
0138         depends on PCIE_DPC && ACPI
0139         help
0140           This option adds Error Disconnect Recover support as specified
0141           in the Downstream Port Containment Related Enhancements ECN to
0142           the PCI Firmware Specification r3.2.  Enable this if you want to
0143           support hybrid DPC model which uses both firmware and OS to
0144           implement DPC.