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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef DRIVERS_PCI_H
0003 #define DRIVERS_PCI_H
0004 
0005 #include <linux/pci.h>
0006 
0007 /* Number of possible devfns: 0.0 to 1f.7 inclusive */
0008 #define MAX_NR_DEVFNS 256
0009 
0010 #define PCI_FIND_CAP_TTL    48
0011 
0012 #define PCI_VSEC_ID_INTEL_TBT   0x1234  /* Thunderbolt */
0013 
0014 extern const unsigned char pcie_link_speed[];
0015 extern bool pci_early_dump;
0016 
0017 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
0018 bool pcie_cap_has_rtctl(const struct pci_dev *dev);
0019 
0020 /* Functions internal to the PCI core code */
0021 
0022 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
0023 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
0024 void pci_cleanup_rom(struct pci_dev *dev);
0025 #ifdef CONFIG_DMI
0026 extern const struct attribute_group pci_dev_smbios_attr_group;
0027 #endif
0028 
0029 enum pci_mmap_api {
0030     PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
0031     PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
0032 };
0033 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
0034           enum pci_mmap_api mmap_api);
0035 
0036 bool pci_reset_supported(struct pci_dev *dev);
0037 void pci_init_reset_methods(struct pci_dev *dev);
0038 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
0039 int pci_bus_error_reset(struct pci_dev *dev);
0040 
0041 struct pci_cap_saved_data {
0042     u16     cap_nr;
0043     bool        cap_extended;
0044     unsigned int    size;
0045     u32     data[];
0046 };
0047 
0048 struct pci_cap_saved_state {
0049     struct hlist_node       next;
0050     struct pci_cap_saved_data   cap;
0051 };
0052 
0053 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
0054 void pci_free_cap_save_buffers(struct pci_dev *dev);
0055 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
0056 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
0057                 u16 cap, unsigned int size);
0058 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
0059 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
0060                            u16 cap);
0061 
0062 #define PCI_PM_D2_DELAY         200 /* usec; see PCIe r4.0, sec 5.9.1 */
0063 #define PCI_PM_D3HOT_WAIT       10  /* msec */
0064 #define PCI_PM_D3COLD_WAIT      100 /* msec */
0065 
0066 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
0067 void pci_refresh_power_state(struct pci_dev *dev);
0068 int pci_power_up(struct pci_dev *dev);
0069 void pci_disable_enabled_device(struct pci_dev *dev);
0070 int pci_finish_runtime_suspend(struct pci_dev *dev);
0071 void pcie_clear_device_status(struct pci_dev *dev);
0072 void pcie_clear_root_pme_status(struct pci_dev *dev);
0073 bool pci_check_pme_status(struct pci_dev *dev);
0074 void pci_pme_wakeup_bus(struct pci_bus *bus);
0075 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
0076 void pci_pme_restore(struct pci_dev *dev);
0077 bool pci_dev_need_resume(struct pci_dev *dev);
0078 void pci_dev_adjust_pme(struct pci_dev *dev);
0079 void pci_dev_complete_resume(struct pci_dev *pci_dev);
0080 void pci_config_pm_runtime_get(struct pci_dev *dev);
0081 void pci_config_pm_runtime_put(struct pci_dev *dev);
0082 void pci_pm_init(struct pci_dev *dev);
0083 void pci_ea_init(struct pci_dev *dev);
0084 void pci_msi_init(struct pci_dev *dev);
0085 void pci_msix_init(struct pci_dev *dev);
0086 bool pci_bridge_d3_possible(struct pci_dev *dev);
0087 void pci_bridge_d3_update(struct pci_dev *dev);
0088 void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev);
0089 void pci_bridge_reconfigure_ltr(struct pci_dev *dev);
0090 
0091 static inline void pci_wakeup_event(struct pci_dev *dev)
0092 {
0093     /* Wait 100 ms before the system can be put into a sleep state. */
0094     pm_wakeup_event(&dev->dev, 100);
0095 }
0096 
0097 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
0098 {
0099     return !!(pci_dev->subordinate);
0100 }
0101 
0102 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
0103 {
0104     /*
0105      * Currently we allow normal PCI devices and PCI bridges transition
0106      * into D3 if their bridge_d3 is set.
0107      */
0108     return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
0109 }
0110 
0111 static inline bool pcie_downstream_port(const struct pci_dev *dev)
0112 {
0113     int type = pci_pcie_type(dev);
0114 
0115     return type == PCI_EXP_TYPE_ROOT_PORT ||
0116            type == PCI_EXP_TYPE_DOWNSTREAM ||
0117            type == PCI_EXP_TYPE_PCIE_BRIDGE;
0118 }
0119 
0120 void pci_vpd_init(struct pci_dev *dev);
0121 void pci_vpd_release(struct pci_dev *dev);
0122 extern const struct attribute_group pci_dev_vpd_attr_group;
0123 
0124 /* PCI Virtual Channel */
0125 int pci_save_vc_state(struct pci_dev *dev);
0126 void pci_restore_vc_state(struct pci_dev *dev);
0127 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
0128 
0129 /* PCI /proc functions */
0130 #ifdef CONFIG_PROC_FS
0131 int pci_proc_attach_device(struct pci_dev *dev);
0132 int pci_proc_detach_device(struct pci_dev *dev);
0133 int pci_proc_detach_bus(struct pci_bus *bus);
0134 #else
0135 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
0136 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
0137 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
0138 #endif
0139 
0140 /* Functions for PCI Hotplug drivers to use */
0141 int pci_hp_add_bridge(struct pci_dev *dev);
0142 
0143 #ifdef HAVE_PCI_LEGACY
0144 void pci_create_legacy_files(struct pci_bus *bus);
0145 void pci_remove_legacy_files(struct pci_bus *bus);
0146 #else
0147 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
0148 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
0149 #endif
0150 
0151 /* Lock for read/write access to pci device and bus lists */
0152 extern struct rw_semaphore pci_bus_sem;
0153 extern struct mutex pci_slot_mutex;
0154 
0155 extern raw_spinlock_t pci_lock;
0156 
0157 extern unsigned int pci_pm_d3hot_delay;
0158 
0159 #ifdef CONFIG_PCI_MSI
0160 void pci_no_msi(void);
0161 #else
0162 static inline void pci_no_msi(void) { }
0163 #endif
0164 
0165 void pci_realloc_get_opt(char *);
0166 
0167 static inline int pci_no_d1d2(struct pci_dev *dev)
0168 {
0169     unsigned int parent_dstates = 0;
0170 
0171     if (dev->bus->self)
0172         parent_dstates = dev->bus->self->no_d1d2;
0173     return (dev->no_d1d2 || parent_dstates);
0174 
0175 }
0176 extern const struct attribute_group *pci_dev_groups[];
0177 extern const struct attribute_group *pcibus_groups[];
0178 extern const struct device_type pci_dev_type;
0179 extern const struct attribute_group *pci_bus_groups[];
0180 
0181 extern unsigned long pci_hotplug_io_size;
0182 extern unsigned long pci_hotplug_mmio_size;
0183 extern unsigned long pci_hotplug_mmio_pref_size;
0184 extern unsigned long pci_hotplug_bus_size;
0185 
0186 /**
0187  * pci_match_one_device - Tell if a PCI device structure has a matching
0188  *            PCI device id structure
0189  * @id: single PCI device id structure to match
0190  * @dev: the PCI device structure to match against
0191  *
0192  * Returns the matching pci_device_id structure or %NULL if there is no match.
0193  */
0194 static inline const struct pci_device_id *
0195 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
0196 {
0197     if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
0198         (id->device == PCI_ANY_ID || id->device == dev->device) &&
0199         (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
0200         (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
0201         !((id->class ^ dev->class) & id->class_mask))
0202         return id;
0203     return NULL;
0204 }
0205 
0206 /* PCI slot sysfs helper code */
0207 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
0208 
0209 extern struct kset *pci_slots_kset;
0210 
0211 struct pci_slot_attribute {
0212     struct attribute attr;
0213     ssize_t (*show)(struct pci_slot *, char *);
0214     ssize_t (*store)(struct pci_slot *, const char *, size_t);
0215 };
0216 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
0217 
0218 enum pci_bar_type {
0219     pci_bar_unknown,    /* Standard PCI BAR probe */
0220     pci_bar_io,     /* An I/O port BAR */
0221     pci_bar_mem32,      /* A 32-bit memory BAR */
0222     pci_bar_mem64,      /* A 64-bit memory BAR */
0223 };
0224 
0225 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
0226 void pci_put_host_bridge_device(struct device *dev);
0227 
0228 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
0229 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
0230                 int crs_timeout);
0231 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
0232                     int crs_timeout);
0233 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
0234 
0235 int pci_setup_device(struct pci_dev *dev);
0236 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
0237             struct resource *res, unsigned int reg);
0238 void pci_configure_ari(struct pci_dev *dev);
0239 void __pci_bus_size_bridges(struct pci_bus *bus,
0240             struct list_head *realloc_head);
0241 void __pci_bus_assign_resources(const struct pci_bus *bus,
0242                 struct list_head *realloc_head,
0243                 struct list_head *fail_head);
0244 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
0245 
0246 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
0247 void pci_disable_bridge_window(struct pci_dev *dev);
0248 struct pci_bus *pci_bus_get(struct pci_bus *bus);
0249 void pci_bus_put(struct pci_bus *bus);
0250 
0251 /* PCIe link information from Link Capabilities 2 */
0252 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
0253     ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
0254      (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
0255      (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
0256      (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
0257      (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
0258      (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
0259      PCI_SPEED_UNKNOWN)
0260 
0261 /* PCIe speed to Mb/s reduced by encoding overhead */
0262 #define PCIE_SPEED2MBS_ENC(speed) \
0263     ((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \
0264      (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
0265      (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
0266      (speed) == PCIE_SPEED_8_0GT  ?  8000*128/130 : \
0267      (speed) == PCIE_SPEED_5_0GT  ?  5000*8/10 : \
0268      (speed) == PCIE_SPEED_2_5GT  ?  2500*8/10 : \
0269      0)
0270 
0271 const char *pci_speed_string(enum pci_bus_speed speed);
0272 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
0273 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
0274 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
0275                enum pcie_link_width *width);
0276 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
0277 void pcie_report_downtraining(struct pci_dev *dev);
0278 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
0279 
0280 /* Single Root I/O Virtualization */
0281 struct pci_sriov {
0282     int     pos;        /* Capability position */
0283     int     nres;       /* Number of resources */
0284     u32     cap;        /* SR-IOV Capabilities */
0285     u16     ctrl;       /* SR-IOV Control */
0286     u16     total_VFs;  /* Total VFs associated with the PF */
0287     u16     initial_VFs;    /* Initial VFs associated with the PF */
0288     u16     num_VFs;    /* Number of VFs available */
0289     u16     offset;     /* First VF Routing ID offset */
0290     u16     stride;     /* Following VF stride */
0291     u16     vf_device;  /* VF device ID */
0292     u32     pgsz;       /* Page size for BAR alignment */
0293     u8      link;       /* Function Dependency Link */
0294     u8      max_VF_buses;   /* Max buses consumed by VFs */
0295     u16     driver_max_VFs; /* Max num VFs driver supports */
0296     struct pci_dev  *dev;       /* Lowest numbered PF */
0297     struct pci_dev  *self;      /* This PF */
0298     u32     class;      /* VF device */
0299     u8      hdr_type;   /* VF header type */
0300     u16     subsystem_vendor; /* VF subsystem vendor */
0301     u16     subsystem_device; /* VF subsystem device */
0302     resource_size_t barsz[PCI_SRIOV_NUM_BARS];  /* VF BAR size */
0303     bool        drivers_autoprobe; /* Auto probing of VFs by driver */
0304 };
0305 
0306 /**
0307  * pci_dev_set_io_state - Set the new error state if possible.
0308  *
0309  * @dev: PCI device to set new error_state
0310  * @new: the state we want dev to be in
0311  *
0312  * Must be called with device_lock held.
0313  *
0314  * Returns true if state has been changed to the requested state.
0315  */
0316 static inline bool pci_dev_set_io_state(struct pci_dev *dev,
0317                     pci_channel_state_t new)
0318 {
0319     bool changed = false;
0320 
0321     device_lock_assert(&dev->dev);
0322     switch (new) {
0323     case pci_channel_io_perm_failure:
0324         switch (dev->error_state) {
0325         case pci_channel_io_frozen:
0326         case pci_channel_io_normal:
0327         case pci_channel_io_perm_failure:
0328             changed = true;
0329             break;
0330         }
0331         break;
0332     case pci_channel_io_frozen:
0333         switch (dev->error_state) {
0334         case pci_channel_io_frozen:
0335         case pci_channel_io_normal:
0336             changed = true;
0337             break;
0338         }
0339         break;
0340     case pci_channel_io_normal:
0341         switch (dev->error_state) {
0342         case pci_channel_io_frozen:
0343         case pci_channel_io_normal:
0344             changed = true;
0345             break;
0346         }
0347         break;
0348     }
0349     if (changed)
0350         dev->error_state = new;
0351     return changed;
0352 }
0353 
0354 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
0355 {
0356     device_lock(&dev->dev);
0357     pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
0358     device_unlock(&dev->dev);
0359 
0360     return 0;
0361 }
0362 
0363 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
0364 {
0365     return dev->error_state == pci_channel_io_perm_failure;
0366 }
0367 
0368 /* pci_dev priv_flags */
0369 #define PCI_DEV_ADDED 0
0370 #define PCI_DPC_RECOVERED 1
0371 #define PCI_DPC_RECOVERING 2
0372 
0373 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
0374 {
0375     assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
0376 }
0377 
0378 static inline bool pci_dev_is_added(const struct pci_dev *dev)
0379 {
0380     return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
0381 }
0382 
0383 #ifdef CONFIG_PCIEAER
0384 #include <linux/aer.h>
0385 
0386 #define AER_MAX_MULTI_ERR_DEVICES   5   /* Not likely to have more */
0387 
0388 struct aer_err_info {
0389     struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
0390     int error_dev_num;
0391 
0392     unsigned int id:16;
0393 
0394     unsigned int severity:2;    /* 0:NONFATAL | 1:FATAL | 2:COR */
0395     unsigned int __pad1:5;
0396     unsigned int multi_error_valid:1;
0397 
0398     unsigned int first_error:5;
0399     unsigned int __pad2:2;
0400     unsigned int tlp_header_valid:1;
0401 
0402     unsigned int status;        /* COR/UNCOR Error Status */
0403     unsigned int mask;      /* COR/UNCOR Error Mask */
0404     struct aer_header_log_regs tlp; /* TLP Header */
0405 };
0406 
0407 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
0408 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
0409 #endif  /* CONFIG_PCIEAER */
0410 
0411 #ifdef CONFIG_PCIEPORTBUS
0412 /* Cached RCEC Endpoint Association */
0413 struct rcec_ea {
0414     u8      nextbusn;
0415     u8      lastbusn;
0416     u32     bitmap;
0417 };
0418 #endif
0419 
0420 #ifdef CONFIG_PCIE_DPC
0421 void pci_save_dpc_state(struct pci_dev *dev);
0422 void pci_restore_dpc_state(struct pci_dev *dev);
0423 void pci_dpc_init(struct pci_dev *pdev);
0424 void dpc_process_error(struct pci_dev *pdev);
0425 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
0426 bool pci_dpc_recovered(struct pci_dev *pdev);
0427 #else
0428 static inline void pci_save_dpc_state(struct pci_dev *dev) {}
0429 static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
0430 static inline void pci_dpc_init(struct pci_dev *pdev) {}
0431 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
0432 #endif
0433 
0434 #ifdef CONFIG_PCIEPORTBUS
0435 void pci_rcec_init(struct pci_dev *dev);
0436 void pci_rcec_exit(struct pci_dev *dev);
0437 void pcie_link_rcec(struct pci_dev *rcec);
0438 void pcie_walk_rcec(struct pci_dev *rcec,
0439             int (*cb)(struct pci_dev *, void *),
0440             void *userdata);
0441 #else
0442 static inline void pci_rcec_init(struct pci_dev *dev) {}
0443 static inline void pci_rcec_exit(struct pci_dev *dev) {}
0444 static inline void pcie_link_rcec(struct pci_dev *rcec) {}
0445 static inline void pcie_walk_rcec(struct pci_dev *rcec,
0446                   int (*cb)(struct pci_dev *, void *),
0447                   void *userdata) {}
0448 #endif
0449 
0450 #ifdef CONFIG_PCI_ATS
0451 /* Address Translation Service */
0452 void pci_ats_init(struct pci_dev *dev);
0453 void pci_restore_ats_state(struct pci_dev *dev);
0454 #else
0455 static inline void pci_ats_init(struct pci_dev *d) { }
0456 static inline void pci_restore_ats_state(struct pci_dev *dev) { }
0457 #endif /* CONFIG_PCI_ATS */
0458 
0459 #ifdef CONFIG_PCI_PRI
0460 void pci_pri_init(struct pci_dev *dev);
0461 void pci_restore_pri_state(struct pci_dev *pdev);
0462 #else
0463 static inline void pci_pri_init(struct pci_dev *dev) { }
0464 static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
0465 #endif
0466 
0467 #ifdef CONFIG_PCI_PASID
0468 void pci_pasid_init(struct pci_dev *dev);
0469 void pci_restore_pasid_state(struct pci_dev *pdev);
0470 #else
0471 static inline void pci_pasid_init(struct pci_dev *dev) { }
0472 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
0473 #endif
0474 
0475 #ifdef CONFIG_PCI_IOV
0476 int pci_iov_init(struct pci_dev *dev);
0477 void pci_iov_release(struct pci_dev *dev);
0478 void pci_iov_remove(struct pci_dev *dev);
0479 void pci_iov_update_resource(struct pci_dev *dev, int resno);
0480 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
0481 void pci_restore_iov_state(struct pci_dev *dev);
0482 int pci_iov_bus_range(struct pci_bus *bus);
0483 extern const struct attribute_group sriov_pf_dev_attr_group;
0484 extern const struct attribute_group sriov_vf_dev_attr_group;
0485 #else
0486 static inline int pci_iov_init(struct pci_dev *dev)
0487 {
0488     return -ENODEV;
0489 }
0490 static inline void pci_iov_release(struct pci_dev *dev)
0491 
0492 {
0493 }
0494 static inline void pci_iov_remove(struct pci_dev *dev)
0495 {
0496 }
0497 static inline void pci_restore_iov_state(struct pci_dev *dev)
0498 {
0499 }
0500 static inline int pci_iov_bus_range(struct pci_bus *bus)
0501 {
0502     return 0;
0503 }
0504 
0505 #endif /* CONFIG_PCI_IOV */
0506 
0507 #ifdef CONFIG_PCIE_PTM
0508 void pci_save_ptm_state(struct pci_dev *dev);
0509 void pci_restore_ptm_state(struct pci_dev *dev);
0510 void pci_disable_ptm(struct pci_dev *dev);
0511 #else
0512 static inline void pci_save_ptm_state(struct pci_dev *dev) { }
0513 static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
0514 static inline void pci_disable_ptm(struct pci_dev *dev) { }
0515 #endif
0516 
0517 unsigned long pci_cardbus_resource_alignment(struct resource *);
0518 
0519 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
0520                              struct resource *res)
0521 {
0522 #ifdef CONFIG_PCI_IOV
0523     int resno = res - dev->resource;
0524 
0525     if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
0526         return pci_sriov_resource_alignment(dev, resno);
0527 #endif
0528     if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
0529         return pci_cardbus_resource_alignment(res);
0530     return resource_alignment(res);
0531 }
0532 
0533 void pci_acs_init(struct pci_dev *dev);
0534 #ifdef CONFIG_PCI_QUIRKS
0535 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
0536 int pci_dev_specific_enable_acs(struct pci_dev *dev);
0537 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
0538 #else
0539 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
0540                            u16 acs_flags)
0541 {
0542     return -ENOTTY;
0543 }
0544 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
0545 {
0546     return -ENOTTY;
0547 }
0548 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
0549 {
0550     return -ENOTTY;
0551 }
0552 #endif
0553 
0554 /* PCI error reporting and recovery */
0555 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
0556         pci_channel_state_t state,
0557         pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
0558 
0559 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
0560 #ifdef CONFIG_PCIEASPM
0561 void pcie_aspm_init_link_state(struct pci_dev *pdev);
0562 void pcie_aspm_exit_link_state(struct pci_dev *pdev);
0563 void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
0564 #else
0565 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
0566 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
0567 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
0568 #endif
0569 
0570 #ifdef CONFIG_PCIE_ECRC
0571 void pcie_set_ecrc_checking(struct pci_dev *dev);
0572 void pcie_ecrc_get_policy(char *str);
0573 #else
0574 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
0575 static inline void pcie_ecrc_get_policy(char *str) { }
0576 #endif
0577 
0578 #ifdef CONFIG_PCIE_PTM
0579 void pci_ptm_init(struct pci_dev *dev);
0580 #else
0581 static inline void pci_ptm_init(struct pci_dev *dev) { }
0582 #endif
0583 
0584 struct pci_dev_reset_methods {
0585     u16 vendor;
0586     u16 device;
0587     int (*reset)(struct pci_dev *dev, bool probe);
0588 };
0589 
0590 struct pci_reset_fn_method {
0591     int (*reset_fn)(struct pci_dev *pdev, bool probe);
0592     char *name;
0593 };
0594 
0595 #ifdef CONFIG_PCI_QUIRKS
0596 int pci_dev_specific_reset(struct pci_dev *dev, bool probe);
0597 #else
0598 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
0599 {
0600     return -ENOTTY;
0601 }
0602 #endif
0603 
0604 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
0605 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
0606               struct resource *res);
0607 #else
0608 static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
0609                     u16 segment, struct resource *res)
0610 {
0611     return -ENODEV;
0612 }
0613 #endif
0614 
0615 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
0616 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
0617 static inline u64 pci_rebar_size_to_bytes(int size)
0618 {
0619     return 1ULL << (size + 20);
0620 }
0621 
0622 struct device_node;
0623 
0624 #ifdef CONFIG_OF
0625 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
0626 int of_get_pci_domain_nr(struct device_node *node);
0627 int of_pci_get_max_link_speed(struct device_node *node);
0628 u32 of_pci_get_slot_power_limit(struct device_node *node,
0629                 u8 *slot_power_limit_value,
0630                 u8 *slot_power_limit_scale);
0631 void pci_set_of_node(struct pci_dev *dev);
0632 void pci_release_of_node(struct pci_dev *dev);
0633 void pci_set_bus_of_node(struct pci_bus *bus);
0634 void pci_release_bus_of_node(struct pci_bus *bus);
0635 
0636 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
0637 
0638 #else
0639 static inline int
0640 of_pci_parse_bus_range(struct device_node *node, struct resource *res)
0641 {
0642     return -EINVAL;
0643 }
0644 
0645 static inline int
0646 of_get_pci_domain_nr(struct device_node *node)
0647 {
0648     return -1;
0649 }
0650 
0651 static inline int
0652 of_pci_get_max_link_speed(struct device_node *node)
0653 {
0654     return -EINVAL;
0655 }
0656 
0657 static inline u32
0658 of_pci_get_slot_power_limit(struct device_node *node,
0659                 u8 *slot_power_limit_value,
0660                 u8 *slot_power_limit_scale)
0661 {
0662     if (slot_power_limit_value)
0663         *slot_power_limit_value = 0;
0664     if (slot_power_limit_scale)
0665         *slot_power_limit_scale = 0;
0666     return 0;
0667 }
0668 
0669 static inline void pci_set_of_node(struct pci_dev *dev) { }
0670 static inline void pci_release_of_node(struct pci_dev *dev) { }
0671 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
0672 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
0673 
0674 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
0675 {
0676     return 0;
0677 }
0678 
0679 #endif /* CONFIG_OF */
0680 
0681 #ifdef CONFIG_PCIEAER
0682 void pci_no_aer(void);
0683 void pci_aer_init(struct pci_dev *dev);
0684 void pci_aer_exit(struct pci_dev *dev);
0685 extern const struct attribute_group aer_stats_attr_group;
0686 void pci_aer_clear_fatal_status(struct pci_dev *dev);
0687 int pci_aer_clear_status(struct pci_dev *dev);
0688 int pci_aer_raw_clear_status(struct pci_dev *dev);
0689 #else
0690 static inline void pci_no_aer(void) { }
0691 static inline void pci_aer_init(struct pci_dev *d) { }
0692 static inline void pci_aer_exit(struct pci_dev *d) { }
0693 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
0694 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
0695 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
0696 #endif
0697 
0698 #ifdef CONFIG_ACPI
0699 int pci_acpi_program_hp_params(struct pci_dev *dev);
0700 extern const struct attribute_group pci_dev_acpi_attr_group;
0701 void pci_set_acpi_fwnode(struct pci_dev *dev);
0702 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe);
0703 bool acpi_pci_power_manageable(struct pci_dev *dev);
0704 bool acpi_pci_bridge_d3(struct pci_dev *dev);
0705 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state);
0706 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev);
0707 void acpi_pci_refresh_power_state(struct pci_dev *dev);
0708 int acpi_pci_wakeup(struct pci_dev *dev, bool enable);
0709 bool acpi_pci_need_resume(struct pci_dev *dev);
0710 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev);
0711 #else
0712 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
0713 {
0714     return -ENOTTY;
0715 }
0716 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) {}
0717 static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
0718 {
0719     return -ENODEV;
0720 }
0721 static inline bool acpi_pci_power_manageable(struct pci_dev *dev)
0722 {
0723     return false;
0724 }
0725 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev)
0726 {
0727     return false;
0728 }
0729 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
0730 {
0731     return -ENODEV;
0732 }
0733 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
0734 {
0735     return PCI_UNKNOWN;
0736 }
0737 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) {}
0738 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
0739 {
0740     return -ENODEV;
0741 }
0742 static inline bool acpi_pci_need_resume(struct pci_dev *dev)
0743 {
0744     return false;
0745 }
0746 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
0747 {
0748     return PCI_POWER_ERROR;
0749 }
0750 #endif
0751 
0752 #ifdef CONFIG_PCIEASPM
0753 extern const struct attribute_group aspm_ctrl_attr_group;
0754 #endif
0755 
0756 extern const struct attribute_group pci_dev_reset_method_attr_group;
0757 
0758 #ifdef CONFIG_X86_INTEL_MID
0759 bool pci_use_mid_pm(void);
0760 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
0761 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev);
0762 #else
0763 static inline bool pci_use_mid_pm(void)
0764 {
0765     return false;
0766 }
0767 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
0768 {
0769     return -ENODEV;
0770 }
0771 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
0772 {
0773     return PCI_UNKNOWN;
0774 }
0775 #endif
0776 
0777 #endif /* DRIVERS_PCI_H */
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