drivers/pci/pci-bridge-emul.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __PCI_BRIDGE_EMUL_H__
0003 #define __PCI_BRIDGE_EMUL_H__
0004
0005 #include <linux/kernel.h>
0006
0007 /* PCI configuration space of a PCI-to-PCI bridge. */
0008 struct pci_bridge_emul_conf {
0009     __le16 vendor;
0010     __le16 device;
0011     __le16 command;
0012     __le16 status;
0013     __le32 class_revision;
0014     u8 cache_line_size;
0015     u8 latency_timer;
0016     u8 header_type;
0017     u8 bist;
0018     __le32 bar[2];
0019     u8 primary_bus;
0020     u8 secondary_bus;
0021     u8 subordinate_bus;
0022     u8 secondary_latency_timer;
0023     u8 iobase;
0024     u8 iolimit;
0025     __le16 secondary_status;
0026     __le16 membase;
0027     __le16 memlimit;
0028     __le16 pref_mem_base;
0029     __le16 pref_mem_limit;
0030     __le32 prefbaseupper;
0031     __le32 preflimitupper;
0032     __le16 iobaseupper;
0033     __le16 iolimitupper;
0034     u8 capabilities_pointer;
0035     u8 reserve[3];
0036     __le32 romaddr;
0037     u8 intline;
0038     u8 intpin;
0039     __le16 bridgectrl;
0040 };
0041
0042 /* PCI configuration space of the PCIe capabilities */
0043 struct pci_bridge_emul_pcie_conf {
0044     u8 cap_id;
0045     u8 next;
0046     __le16 cap;
0047     __le32 devcap;
0048     __le16 devctl;
0049     __le16 devsta;
0050     __le32 lnkcap;
0051     __le16 lnkctl;
0052     __le16 lnksta;
0053     __le32 slotcap;
0054     __le16 slotctl;
0055     __le16 slotsta;
0056     __le16 rootctl;
0057     __le16 rootcap;
0058     __le32 rootsta;
0059     __le32 devcap2;
0060     __le16 devctl2;
0061     __le16 devsta2;
0062     __le32 lnkcap2;
0063     __le16 lnkctl2;
0064     __le16 lnksta2;
0065     __le32 slotcap2;
0066     __le16 slotctl2;
0067     __le16 slotsta2;
0068 };
0069
0070 struct pci_bridge_emul;
0071
0072 typedef enum { PCI_BRIDGE_EMUL_HANDLED,
0073            PCI_BRIDGE_EMUL_NOT_HANDLED } pci_bridge_emul_read_status_t;
0074
0075 struct pci_bridge_emul_ops {
0076     /*
0077      * Called when reading from the regular PCI bridge
0078      * configuration space. Return PCI_BRIDGE_EMUL_HANDLED when the
0079      * operation has handled the read operation and filled in the
0080      * *value, or PCI_BRIDGE_EMUL_NOT_HANDLED when the read should
0081      * be emulated by the common code by reading from the
0082      * in-memory copy of the configuration space.
0083      */
0084     pci_bridge_emul_read_status_t (*read_base)(struct pci_bridge_emul *bridge,
0085                            int reg, u32 *value);
0086
0087     /*
0088      * Same as ->read_base(), except it is for reading from the
0089      * PCIe capability configuration space.
0090      */
0091     pci_bridge_emul_read_status_t (*read_pcie)(struct pci_bridge_emul *bridge,
0092                            int reg, u32 *value);
0093
0094     /*
0095      * Same as ->read_base(), except it is for reading from the
0096      * PCIe extended capability configuration space.
0097      */
0098     pci_bridge_emul_read_status_t (*read_ext)(struct pci_bridge_emul *bridge,
0099                           int reg, u32 *value);
0100
0101     /*
0102      * Called when writing to the regular PCI bridge configuration
0103      * space. old is the current value, new is the new value being
0104      * written, and mask indicates which parts of the value are
0105      * being changed.
0106      */
0107     void (*write_base)(struct pci_bridge_emul *bridge, int reg,
0108                u32 old, u32 new, u32 mask);
0109
0110     /*
0111      * Same as ->write_base(), except it is for writing from the
0112      * PCIe capability configuration space.
0113      */
0114     void (*write_pcie)(struct pci_bridge_emul *bridge, int reg,
0115                u32 old, u32 new, u32 mask);
0116
0117     /*
0118      * Same as ->write_base(), except it is for writing from the
0119      * PCIe extended capability configuration space.
0120      */
0121     void (*write_ext)(struct pci_bridge_emul *bridge, int reg,
0122               u32 old, u32 new, u32 mask);
0123 };
0124
0125 struct pci_bridge_reg_behavior;
0126
0127 struct pci_bridge_emul {
0128     struct pci_bridge_emul_conf conf;
0129     struct pci_bridge_emul_pcie_conf pcie_conf;
0130     const struct pci_bridge_emul_ops *ops;
0131     struct pci_bridge_reg_behavior *pci_regs_behavior;
0132     struct pci_bridge_reg_behavior *pcie_cap_regs_behavior;
0133     void *data;
0134     bool has_pcie;
0135     u16 subsystem_vendor_id;
0136     u16 subsystem_id;
0137 };
0138
0139 enum {
0140     /*
0141      * PCI bridge does not support forwarding of prefetchable memory
0142      * requests between primary and secondary buses.
0143      */
0144     PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD = BIT(0),
0145
0146     /*
0147      * PCI bridge does not support forwarding of IO requests between
0148      * primary and secondary buses.
0149      */
0150     PCI_BRIDGE_EMUL_NO_IO_FORWARD = BIT(1),
0151 };
0152
0153 int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
0154              unsigned int flags);
0155 void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge);
0156
0157 int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
0158                   int size, u32 *value);
0159 int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
0160                    int size, u32 value);
0161
0162 #endif /* __PCI_BRIDGE_EMUL_H__ */