drivers/pci/pci-bridge-emul.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2018 Marvell
0004  *
0005  * Author: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
0006  *
0007  * This file helps PCI controller drivers implement a fake root port
0008  * PCI bridge when the HW doesn't provide such a root port PCI
0009  * bridge.
0010  *
0011  * It emulates a PCI bridge by providing a fake PCI configuration
0012  * space (and optionally a PCIe capability configuration space) in
0013  * memory. By default the read/write operations simply read and update
0014  * this fake configuration space in memory. However, PCI controller
0015  * drivers can provide through the 'struct pci_sw_bridge_ops'
0016  * structure a set of operations to override or complement this
0017  * default behavior.
0018  */
0019
0020 #include <linux/pci.h>
0021 #include "pci-bridge-emul.h"
0022
0023 #define PCI_BRIDGE_CONF_END PCI_STD_HEADER_SIZEOF
0024 #define PCI_CAP_SSID_SIZEOF (PCI_SSVID_DEVICE_ID + 2)
0025 #define PCI_CAP_SSID_START  PCI_BRIDGE_CONF_END
0026 #define PCI_CAP_SSID_END    (PCI_CAP_SSID_START + PCI_CAP_SSID_SIZEOF)
0027 #define PCI_CAP_PCIE_SIZEOF (PCI_EXP_SLTSTA2 + 2)
0028 #define PCI_CAP_PCIE_START  PCI_CAP_SSID_END
0029 #define PCI_CAP_PCIE_END    (PCI_CAP_PCIE_START + PCI_CAP_PCIE_SIZEOF)
0030
0031 /**
0032  * struct pci_bridge_reg_behavior - register bits behaviors
0033  * @ro:     Read-Only bits
0034  * @rw:     Read-Write bits
0035  * @w1c:    Write-1-to-Clear bits
0036  *
0037  * Reads and Writes will be filtered by specified behavior. All other bits not
0038  * declared are assumed 'Reserved' and will return 0 on reads, per PCIe 5.0:
0039  * "Reserved register fields must be read only and must return 0 (all 0's for
0040  * multi-bit fields) when read".
0041  */
0042 struct pci_bridge_reg_behavior {
0043     /* Read-only bits */
0044     u32 ro;
0045
0046     /* Read-write bits */
0047     u32 rw;
0048
0049     /* Write-1-to-clear bits */
0050     u32 w1c;
0051 };
0052
0053 static const
0054 struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = {
0055     [PCI_VENDOR_ID / 4] = { .ro = ~0 },
0056     [PCI_COMMAND / 4] = {
0057         .rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
0058                PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
0059                PCI_COMMAND_SERR),
0060         .ro = ((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
0061             PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT |
0062             PCI_COMMAND_FAST_BACK) |
0063                (PCI_STATUS_CAP_LIST | PCI_STATUS_66MHZ |
0064             PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MASK) << 16),
0065         .w1c = PCI_STATUS_ERROR_BITS << 16,
0066     },
0067     [PCI_CLASS_REVISION / 4] = { .ro = ~0 },
0068
0069     /*
0070      * Cache Line Size register: implement as read-only, we do not
0071      * pretend implementing "Memory Write and Invalidate"
0072      * transactions"
0073      *
0074      * Latency Timer Register: implemented as read-only, as "A
0075      * bridge that is not capable of a burst transfer of more than
0076      * two data phases on its primary interface is permitted to
0077      * hardwire the Latency Timer to a value of 16 or less"
0078      *
0079      * Header Type: always read-only
0080      *
0081      * BIST register: implemented as read-only, as "A bridge that
0082      * does not support BIST must implement this register as a
0083      * read-only register that returns 0 when read"
0084      */
0085     [PCI_CACHE_LINE_SIZE / 4] = { .ro = ~0 },
0086
0087     /*
0088      * Base Address registers not used must be implemented as
0089      * read-only registers that return 0 when read.
0090      */
0091     [PCI_BASE_ADDRESS_0 / 4] = { .ro = ~0 },
0092     [PCI_BASE_ADDRESS_1 / 4] = { .ro = ~0 },
0093
0094     [PCI_PRIMARY_BUS / 4] = {
0095         /* Primary, secondary and subordinate bus are RW */
0096         .rw = GENMASK(24, 0),
0097         /* Secondary latency is read-only */
0098         .ro = GENMASK(31, 24),
0099     },
0100
0101     [PCI_IO_BASE / 4] = {
0102         /* The high four bits of I/O base/limit are RW */
0103         .rw = (GENMASK(15, 12) | GENMASK(7, 4)),
0104
0105         /* The low four bits of I/O base/limit are RO */
0106         .ro = (((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
0107              PCI_STATUS_DEVSEL_MASK) << 16) |
0108                GENMASK(11, 8) | GENMASK(3, 0)),
0109
0110         .w1c = PCI_STATUS_ERROR_BITS << 16,
0111     },
0112
0113     [PCI_MEMORY_BASE / 4] = {
0114         /* The high 12-bits of mem base/limit are RW */
0115         .rw = GENMASK(31, 20) | GENMASK(15, 4),
0116
0117         /* The low four bits of mem base/limit are RO */
0118         .ro = GENMASK(19, 16) | GENMASK(3, 0),
0119     },
0120
0121     [PCI_PREF_MEMORY_BASE / 4] = {
0122         /* The high 12-bits of pref mem base/limit are RW */
0123         .rw = GENMASK(31, 20) | GENMASK(15, 4),
0124
0125         /* The low four bits of pref mem base/limit are RO */
0126         .ro = GENMASK(19, 16) | GENMASK(3, 0),
0127     },
0128
0129     [PCI_PREF_BASE_UPPER32 / 4] = {
0130         .rw = ~0,
0131     },
0132
0133     [PCI_PREF_LIMIT_UPPER32 / 4] = {
0134         .rw = ~0,
0135     },
0136
0137     [PCI_IO_BASE_UPPER16 / 4] = {
0138         .rw = ~0,
0139     },
0140
0141     [PCI_CAPABILITY_LIST / 4] = {
0142         .ro = GENMASK(7, 0),
0143     },
0144
0145     /*
0146      * If expansion ROM is unsupported then ROM Base Address register must
0147      * be implemented as read-only register that return 0 when read, same
0148      * as for unused Base Address registers.
0149      */
0150     [PCI_ROM_ADDRESS1 / 4] = {
0151         .ro = ~0,
0152     },
0153
0154     /*
0155      * Interrupt line (bits 7:0) are RW, interrupt pin (bits 15:8)
0156      * are RO, and bridge control (31:16) are a mix of RW, RO,
0157      * reserved and W1C bits
0158      */
0159     [PCI_INTERRUPT_LINE / 4] = {
0160         /* Interrupt line is RW */
0161         .rw = (GENMASK(7, 0) |
0162                ((PCI_BRIDGE_CTL_PARITY |
0163              PCI_BRIDGE_CTL_SERR |
0164              PCI_BRIDGE_CTL_ISA |
0165              PCI_BRIDGE_CTL_VGA |
0166              PCI_BRIDGE_CTL_MASTER_ABORT |
0167              PCI_BRIDGE_CTL_BUS_RESET |
0168              BIT(8) | BIT(9) | BIT(11)) << 16)),
0169
0170         /* Interrupt pin is RO */
0171         .ro = (GENMASK(15, 8) | ((PCI_BRIDGE_CTL_FAST_BACK) << 16)),
0172
0173         .w1c = BIT(10) << 16,
0174     },
0175 };
0176
0177 static const
0178 struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] = {
0179     [PCI_CAP_LIST_ID / 4] = {
0180         /*
0181          * Capability ID, Next Capability Pointer and
0182          * bits [14:0] of Capabilities register are all read-only.
0183          * Bit 15 of Capabilities register is reserved.
0184          */
0185         .ro = GENMASK(30, 0),
0186     },
0187
0188     [PCI_EXP_DEVCAP / 4] = {
0189         /*
0190          * Bits [31:29] and [17:16] are reserved.
0191          * Bits [27:18] are reserved for non-upstream ports.
0192          * Bits 28 and [14:6] are reserved for non-endpoint devices.
0193          * Other bits are read-only.
0194          */
0195         .ro = BIT(15) | GENMASK(5, 0),
0196     },
0197
0198     [PCI_EXP_DEVCTL / 4] = {
0199         /*
0200          * Device control register is RW, except bit 15 which is
0201          * reserved for non-endpoints or non-PCIe-to-PCI/X bridges.
0202          */
0203         .rw = GENMASK(14, 0),
0204
0205         /*
0206          * Device status register has bits 6 and [3:0] W1C, [5:4] RO,
0207          * the rest is reserved. Also bit 6 is reserved for non-upstream
0208          * ports.
0209          */
0210         .w1c = GENMASK(3, 0) << 16,
0211         .ro = GENMASK(5, 4) << 16,
0212     },
0213
0214     [PCI_EXP_LNKCAP / 4] = {
0215         /*
0216          * All bits are RO, except bit 23 which is reserved and
0217          * bit 18 which is reserved for non-upstream ports.
0218          */
0219         .ro = lower_32_bits(~(BIT(23) | PCI_EXP_LNKCAP_CLKPM)),
0220     },
0221
0222     [PCI_EXP_LNKCTL / 4] = {
0223         /*
0224          * Link control has bits [15:14], [11:3] and [1:0] RW, the
0225          * rest is reserved. Bit 8 is reserved for non-upstream ports.
0226          *
0227          * Link status has bits [13:0] RO, and bits [15:14]
0228          * W1C.
0229          */
0230         .rw = GENMASK(15, 14) | GENMASK(11, 9) | GENMASK(7, 3) | GENMASK(1, 0),
0231         .ro = GENMASK(13, 0) << 16,
0232         .w1c = GENMASK(15, 14) << 16,
0233     },
0234
0235     [PCI_EXP_SLTCAP / 4] = {
0236         .ro = ~0,
0237     },
0238
0239     [PCI_EXP_SLTCTL / 4] = {
0240         /*
0241          * Slot control has bits [14:0] RW, the rest is
0242          * reserved.
0243          *
0244          * Slot status has bits 8 and [4:0] W1C, bits [7:5] RO, the
0245          * rest is reserved.
0246          */
0247         .rw = GENMASK(14, 0),
0248         .w1c = (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
0249             PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
0250             PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC) << 16,
0251         .ro = (PCI_EXP_SLTSTA_MRLSS | PCI_EXP_SLTSTA_PDS |
0252                PCI_EXP_SLTSTA_EIS) << 16,
0253     },
0254
0255     [PCI_EXP_RTCTL / 4] = {
0256         /*
0257          * Root control has bits [4:0] RW, the rest is
0258          * reserved.
0259          *
0260          * Root capabilities has bit 0 RO, the rest is reserved.
0261          */
0262         .rw = (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
0263                PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE |
0264                PCI_EXP_RTCTL_CRSSVE),
0265         .ro = PCI_EXP_RTCAP_CRSVIS << 16,
0266     },
0267
0268     [PCI_EXP_RTSTA / 4] = {
0269         /*
0270          * Root status has bits 17 and [15:0] RO, bit 16 W1C, the rest
0271          * is reserved.
0272          */
0273         .ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
0274         .w1c = PCI_EXP_RTSTA_PME,
0275     },
0276
0277     [PCI_EXP_DEVCAP2 / 4] = {
0278         /*
0279          * Device capabilities 2 register has reserved bits [30:27].
0280          * Also bits [26:24] are reserved for non-upstream ports.
0281          */
0282         .ro = BIT(31) | GENMASK(23, 0),
0283     },
0284
0285     [PCI_EXP_DEVCTL2 / 4] = {
0286         /*
0287          * Device control 2 register is RW. Bit 11 is reserved for
0288          * non-upstream ports.
0289          *
0290          * Device status 2 register is reserved.
0291          */
0292         .rw = GENMASK(15, 12) | GENMASK(10, 0),
0293     },
0294
0295     [PCI_EXP_LNKCAP2 / 4] = {
0296         /* Link capabilities 2 register has reserved bits [30:25] and 0. */
0297         .ro = BIT(31) | GENMASK(24, 1),
0298     },
0299
0300     [PCI_EXP_LNKCTL2 / 4] = {
0301         /*
0302          * Link control 2 register is RW.
0303          *
0304          * Link status 2 register has bits 5, 15 W1C;
0305          * bits 10, 11 reserved and others are RO.
0306          */
0307         .rw = GENMASK(15, 0),
0308         .w1c = (BIT(15) | BIT(5)) << 16,
0309         .ro = (GENMASK(14, 12) | GENMASK(9, 6) | GENMASK(4, 0)) << 16,
0310     },
0311
0312     [PCI_EXP_SLTCAP2 / 4] = {
0313         /* Slot capabilities 2 register is reserved. */
0314     },
0315
0316     [PCI_EXP_SLTCTL2 / 4] = {
0317         /* Both Slot control 2 and Slot status 2 registers are reserved. */
0318     },
0319 };
0320
0321 static pci_bridge_emul_read_status_t
0322 pci_bridge_emul_read_ssid(struct pci_bridge_emul *bridge, int reg, u32 *value)
0323 {
0324     switch (reg) {
0325     case PCI_CAP_LIST_ID:
0326         *value = PCI_CAP_ID_SSVID |
0327             (bridge->has_pcie ? (PCI_CAP_PCIE_START << 8) : 0);
0328         return PCI_BRIDGE_EMUL_HANDLED;
0329
0330     case PCI_SSVID_VENDOR_ID:
0331         *value = bridge->subsystem_vendor_id |
0332             (bridge->subsystem_id << 16);
0333         return PCI_BRIDGE_EMUL_HANDLED;
0334
0335     default:
0336         return PCI_BRIDGE_EMUL_NOT_HANDLED;
0337     }
0338 }
0339
0340 /*
0341  * Initialize a pci_bridge_emul structure to represent a fake PCI
0342  * bridge configuration space. The caller needs to have initialized
0343  * the PCI configuration space with whatever values make sense
0344  * (typically at least vendor, device, revision), the ->ops pointer,
0345  * and optionally ->data and ->has_pcie.
0346  */
0347 int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
0348              unsigned int flags)
0349 {
0350     BUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END);
0351
0352     /*
0353      * class_revision: Class is high 24 bits and revision is low 8 bit
0354      * of this member, while class for PCI Bridge Normal Decode has the
0355      * 24-bit value: PCI_CLASS_BRIDGE_PCI_NORMAL
0356      */
0357     bridge->conf.class_revision |=
0358         cpu_to_le32(PCI_CLASS_BRIDGE_PCI_NORMAL << 8);
0359     bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
0360     bridge->conf.cache_line_size = 0x10;
0361     bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST);
0362     bridge->pci_regs_behavior = kmemdup(pci_regs_behavior,
0363                         sizeof(pci_regs_behavior),
0364                         GFP_KERNEL);
0365     if (!bridge->pci_regs_behavior)
0366         return -ENOMEM;
0367
0368     if (bridge->subsystem_vendor_id)
0369         bridge->conf.capabilities_pointer = PCI_CAP_SSID_START;
0370     else if (bridge->has_pcie)
0371         bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START;
0372     else
0373         bridge->conf.capabilities_pointer = 0;
0374
0375     if (bridge->conf.capabilities_pointer)
0376         bridge->conf.status |= cpu_to_le16(PCI_STATUS_CAP_LIST);
0377
0378     if (bridge->has_pcie) {
0379         bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP;
0380         bridge->pcie_conf.cap |= cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4);
0381         bridge->pcie_cap_regs_behavior =
0382             kmemdup(pcie_cap_regs_behavior,
0383                 sizeof(pcie_cap_regs_behavior),
0384                 GFP_KERNEL);
0385         if (!bridge->pcie_cap_regs_behavior) {
0386             kfree(bridge->pci_regs_behavior);
0387             return -ENOMEM;
0388         }
0389         /* These bits are applicable only for PCI and reserved on PCIe */
0390         bridge->pci_regs_behavior[PCI_CACHE_LINE_SIZE / 4].ro &=
0391             ~GENMASK(15, 8);
0392         bridge->pci_regs_behavior[PCI_COMMAND / 4].ro &=
0393             ~((PCI_COMMAND_SPECIAL | PCI_COMMAND_INVALIDATE |
0394                PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_WAIT |
0395                PCI_COMMAND_FAST_BACK) |
0396               (PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
0397                PCI_STATUS_DEVSEL_MASK) << 16);
0398         bridge->pci_regs_behavior[PCI_PRIMARY_BUS / 4].ro &=
0399             ~GENMASK(31, 24);
0400         bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro &=
0401             ~((PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK |
0402                PCI_STATUS_DEVSEL_MASK) << 16);
0403         bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &=
0404             ~((PCI_BRIDGE_CTL_MASTER_ABORT |
0405                BIT(8) | BIT(9) | BIT(11)) << 16);
0406         bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].ro &=
0407             ~((PCI_BRIDGE_CTL_FAST_BACK) << 16);
0408         bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].w1c &=
0409             ~(BIT(10) << 16);
0410     }
0411
0412     if (flags & PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD) {
0413         bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0;
0414         bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0;
0415     }
0416
0417     if (flags & PCI_BRIDGE_EMUL_NO_IO_FORWARD) {
0418         bridge->pci_regs_behavior[PCI_COMMAND / 4].ro |= PCI_COMMAND_IO;
0419         bridge->pci_regs_behavior[PCI_COMMAND / 4].rw &= ~PCI_COMMAND_IO;
0420         bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro |= GENMASK(15, 0);
0421         bridge->pci_regs_behavior[PCI_IO_BASE / 4].rw &= ~GENMASK(15, 0);
0422         bridge->pci_regs_behavior[PCI_IO_BASE_UPPER16 / 4].ro = ~0;
0423         bridge->pci_regs_behavior[PCI_IO_BASE_UPPER16 / 4].rw = 0;
0424     }
0425
0426     return 0;
0427 }
0428 EXPORT_SYMBOL_GPL(pci_bridge_emul_init);
0429
0430 /*
0431  * Cleanup a pci_bridge_emul structure that was previously initialized
0432  * using pci_bridge_emul_init().
0433  */
0434 void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge)
0435 {
0436     if (bridge->has_pcie)
0437         kfree(bridge->pcie_cap_regs_behavior);
0438     kfree(bridge->pci_regs_behavior);
0439 }
0440 EXPORT_SYMBOL_GPL(pci_bridge_emul_cleanup);
0441
0442 /*
0443  * Should be called by the PCI controller driver when reading the PCI
0444  * configuration space of the fake bridge. It will call back the
0445  * ->ops->read_base or ->ops->read_pcie operations.
0446  */
0447 int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
0448                   int size, u32 *value)
0449 {
0450     int ret;
0451     int reg = where & ~3;
0452     pci_bridge_emul_read_status_t (*read_op)(struct pci_bridge_emul *bridge,
0453                          int reg, u32 *value);
0454     __le32 *cfgspace;
0455     const struct pci_bridge_reg_behavior *behavior;
0456
0457     if (reg < PCI_BRIDGE_CONF_END) {
0458         /* Emulated PCI space */
0459         read_op = bridge->ops->read_base;
0460         cfgspace = (__le32 *) &bridge->conf;
0461         behavior = bridge->pci_regs_behavior;
0462     } else if (reg >= PCI_CAP_SSID_START && reg < PCI_CAP_SSID_END && bridge->subsystem_vendor_id) {
0463         /* Emulated PCI Bridge Subsystem Vendor ID capability */
0464         reg -= PCI_CAP_SSID_START;
0465         read_op = pci_bridge_emul_read_ssid;
0466         cfgspace = NULL;
0467         behavior = NULL;
0468     } else if (reg >= PCI_CAP_PCIE_START && reg < PCI_CAP_PCIE_END && bridge->has_pcie) {
0469         /* Our emulated PCIe capability */
0470         reg -= PCI_CAP_PCIE_START;
0471         read_op = bridge->ops->read_pcie;
0472         cfgspace = (__le32 *) &bridge->pcie_conf;
0473         behavior = bridge->pcie_cap_regs_behavior;
0474     } else if (reg >= PCI_CFG_SPACE_SIZE && bridge->has_pcie) {
0475         /* PCIe extended capability space */
0476         reg -= PCI_CFG_SPACE_SIZE;
0477         read_op = bridge->ops->read_ext;
0478         cfgspace = NULL;
0479         behavior = NULL;
0480     } else {
0481         /* Not implemented */
0482         *value = 0;
0483         return PCIBIOS_SUCCESSFUL;
0484     }
0485
0486     if (read_op)
0487         ret = read_op(bridge, reg, value);
0488     else
0489         ret = PCI_BRIDGE_EMUL_NOT_HANDLED;
0490
0491     if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED) {
0492         if (cfgspace)
0493             *value = le32_to_cpu(cfgspace[reg / 4]);
0494         else
0495             *value = 0;
0496     }
0497
0498     /*
0499      * Make sure we never return any reserved bit with a value
0500      * different from 0.
0501      */
0502     if (behavior)
0503         *value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
0504               behavior[reg / 4].w1c;
0505
0506     if (size == 1)
0507         *value = (*value >> (8 * (where & 3))) & 0xff;
0508     else if (size == 2)
0509         *value = (*value >> (8 * (where & 3))) & 0xffff;
0510     else if (size != 4)
0511         return PCIBIOS_BAD_REGISTER_NUMBER;
0512
0513     return PCIBIOS_SUCCESSFUL;
0514 }
0515 EXPORT_SYMBOL_GPL(pci_bridge_emul_conf_read);
0516
0517 /*
0518  * Should be called by the PCI controller driver when writing the PCI
0519  * configuration space of the fake bridge. It will call back the
0520  * ->ops->write_base or ->ops->write_pcie operations.
0521  */
0522 int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
0523                    int size, u32 value)
0524 {
0525     int reg = where & ~3;
0526     int mask, ret, old, new, shift;
0527     void (*write_op)(struct pci_bridge_emul *bridge, int reg,
0528              u32 old, u32 new, u32 mask);
0529     __le32 *cfgspace;
0530     const struct pci_bridge_reg_behavior *behavior;
0531
0532     ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old);
0533     if (ret != PCIBIOS_SUCCESSFUL)
0534         return ret;
0535
0536     if (reg < PCI_BRIDGE_CONF_END) {
0537         /* Emulated PCI space */
0538         write_op = bridge->ops->write_base;
0539         cfgspace = (__le32 *) &bridge->conf;
0540         behavior = bridge->pci_regs_behavior;
0541     } else if (reg >= PCI_CAP_PCIE_START && reg < PCI_CAP_PCIE_END && bridge->has_pcie) {
0542         /* Our emulated PCIe capability */
0543         reg -= PCI_CAP_PCIE_START;
0544         write_op = bridge->ops->write_pcie;
0545         cfgspace = (__le32 *) &bridge->pcie_conf;
0546         behavior = bridge->pcie_cap_regs_behavior;
0547     } else if (reg >= PCI_CFG_SPACE_SIZE && bridge->has_pcie) {
0548         /* PCIe extended capability space */
0549         reg -= PCI_CFG_SPACE_SIZE;
0550         write_op = bridge->ops->write_ext;
0551         cfgspace = NULL;
0552         behavior = NULL;
0553     } else {
0554         /* Not implemented */
0555         return PCIBIOS_SUCCESSFUL;
0556     }
0557
0558     shift = (where & 0x3) * 8;
0559
0560     if (size == 4)
0561         mask = 0xffffffff;
0562     else if (size == 2)
0563         mask = 0xffff << shift;
0564     else if (size == 1)
0565         mask = 0xff << shift;
0566     else
0567         return PCIBIOS_BAD_REGISTER_NUMBER;
0568
0569     if (behavior) {
0570         /* Keep all bits, except the RW bits */
0571         new = old & (~mask | ~behavior[reg / 4].rw);
0572
0573         /* Update the value of the RW bits */
0574         new |= (value << shift) & (behavior[reg / 4].rw & mask);
0575
0576         /* Clear the W1C bits */
0577         new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
0578     } else {
0579         new = old & ~mask;
0580         new |= (value << shift) & mask;
0581     }
0582
0583     if (cfgspace) {
0584         /* Save the new value with the cleared W1C bits into the cfgspace */
0585         cfgspace[reg / 4] = cpu_to_le32(new);
0586     }
0587
0588     if (behavior) {
0589         /*
0590          * Clear the W1C bits not specified by the write mask, so that the
0591          * write_op() does not clear them.
0592          */
0593         new &= ~(behavior[reg / 4].w1c & ~mask);
0594
0595         /*
0596          * Set the W1C bits specified by the write mask, so that write_op()
0597          * knows about that they are to be cleared.
0598          */
0599         new |= (value << shift) & (behavior[reg / 4].w1c & mask);
0600     }
0601
0602     if (write_op)
0603         write_op(bridge, reg, old, new, mask);
0604
0605     return PCIBIOS_SUCCESSFUL;
0606 }
0607 EXPORT_SYMBOL_GPL(pci_bridge_emul_conf_write);