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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * PCI support in ACPI
0004  *
0005  * Copyright (C) 2005 David Shaohua Li <shaohua.li@intel.com>
0006  * Copyright (C) 2004 Tom Long Nguyen <tom.l.nguyen@intel.com>
0007  * Copyright (C) 2004 Intel Corp.
0008  */
0009 
0010 #include <linux/delay.h>
0011 #include <linux/init.h>
0012 #include <linux/irqdomain.h>
0013 #include <linux/pci.h>
0014 #include <linux/msi.h>
0015 #include <linux/pci_hotplug.h>
0016 #include <linux/module.h>
0017 #include <linux/pci-acpi.h>
0018 #include <linux/pm_runtime.h>
0019 #include <linux/pm_qos.h>
0020 #include <linux/rwsem.h>
0021 #include "pci.h"
0022 
0023 /*
0024  * The GUID is defined in the PCI Firmware Specification available
0025  * here to PCI-SIG members:
0026  * https://members.pcisig.com/wg/PCI-SIG/document/15350
0027  */
0028 const guid_t pci_acpi_dsm_guid =
0029     GUID_INIT(0xe5c937d0, 0x3553, 0x4d7a,
0030           0x91, 0x17, 0xea, 0x4d, 0x19, 0xc3, 0x43, 0x4d);
0031 
0032 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
0033 static int acpi_get_rc_addr(struct acpi_device *adev, struct resource *res)
0034 {
0035     struct device *dev = &adev->dev;
0036     struct resource_entry *entry;
0037     struct list_head list;
0038     unsigned long flags;
0039     int ret;
0040 
0041     INIT_LIST_HEAD(&list);
0042     flags = IORESOURCE_MEM;
0043     ret = acpi_dev_get_resources(adev, &list,
0044                      acpi_dev_filter_resource_type_cb,
0045                      (void *) flags);
0046     if (ret < 0) {
0047         dev_err(dev, "failed to parse _CRS method, error code %d\n",
0048             ret);
0049         return ret;
0050     }
0051 
0052     if (ret == 0) {
0053         dev_err(dev, "no IO and memory resources present in _CRS\n");
0054         return -EINVAL;
0055     }
0056 
0057     entry = list_first_entry(&list, struct resource_entry, node);
0058     *res = *entry->res;
0059     acpi_dev_free_resource_list(&list);
0060     return 0;
0061 }
0062 
0063 static acpi_status acpi_match_rc(acpi_handle handle, u32 lvl, void *context,
0064                  void **retval)
0065 {
0066     u16 *segment = context;
0067     unsigned long long uid;
0068     acpi_status status;
0069 
0070     status = acpi_evaluate_integer(handle, "_UID", NULL, &uid);
0071     if (ACPI_FAILURE(status) || uid != *segment)
0072         return AE_CTRL_DEPTH;
0073 
0074     *(acpi_handle *)retval = handle;
0075     return AE_CTRL_TERMINATE;
0076 }
0077 
0078 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
0079               struct resource *res)
0080 {
0081     struct acpi_device *adev;
0082     acpi_status status;
0083     acpi_handle handle;
0084     int ret;
0085 
0086     status = acpi_get_devices(hid, acpi_match_rc, &segment, &handle);
0087     if (ACPI_FAILURE(status)) {
0088         dev_err(dev, "can't find _HID %s device to locate resources\n",
0089             hid);
0090         return -ENODEV;
0091     }
0092 
0093     adev = acpi_fetch_acpi_dev(handle);
0094     if (!adev)
0095         return -ENODEV;
0096 
0097     ret = acpi_get_rc_addr(adev, res);
0098     if (ret) {
0099         dev_err(dev, "can't get resource from %s\n",
0100             dev_name(&adev->dev));
0101         return ret;
0102     }
0103 
0104     return 0;
0105 }
0106 #endif
0107 
0108 phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle)
0109 {
0110     acpi_status status = AE_NOT_EXIST;
0111     unsigned long long mcfg_addr;
0112 
0113     if (handle)
0114         status = acpi_evaluate_integer(handle, METHOD_NAME__CBA,
0115                            NULL, &mcfg_addr);
0116     if (ACPI_FAILURE(status))
0117         return 0;
0118 
0119     return (phys_addr_t)mcfg_addr;
0120 }
0121 
0122 /* _HPX PCI Setting Record (Type 0); same as _HPP */
0123 struct hpx_type0 {
0124     u32 revision;       /* Not present in _HPP */
0125     u8  cache_line_size;    /* Not applicable to PCIe */
0126     u8  latency_timer;  /* Not applicable to PCIe */
0127     u8  enable_serr;
0128     u8  enable_perr;
0129 };
0130 
0131 static struct hpx_type0 pci_default_type0 = {
0132     .revision = 1,
0133     .cache_line_size = 8,
0134     .latency_timer = 0x40,
0135     .enable_serr = 0,
0136     .enable_perr = 0,
0137 };
0138 
0139 static void program_hpx_type0(struct pci_dev *dev, struct hpx_type0 *hpx)
0140 {
0141     u16 pci_cmd, pci_bctl;
0142 
0143     if (!hpx)
0144         hpx = &pci_default_type0;
0145 
0146     if (hpx->revision > 1) {
0147         pci_warn(dev, "PCI settings rev %d not supported; using defaults\n",
0148              hpx->revision);
0149         hpx = &pci_default_type0;
0150     }
0151 
0152     pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpx->cache_line_size);
0153     pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpx->latency_timer);
0154     pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
0155     if (hpx->enable_serr)
0156         pci_cmd |= PCI_COMMAND_SERR;
0157     if (hpx->enable_perr)
0158         pci_cmd |= PCI_COMMAND_PARITY;
0159     pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
0160 
0161     /* Program bridge control value */
0162     if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
0163         pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
0164                       hpx->latency_timer);
0165         pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
0166         if (hpx->enable_perr)
0167             pci_bctl |= PCI_BRIDGE_CTL_PARITY;
0168         pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
0169     }
0170 }
0171 
0172 static acpi_status decode_type0_hpx_record(union acpi_object *record,
0173                        struct hpx_type0 *hpx0)
0174 {
0175     int i;
0176     union acpi_object *fields = record->package.elements;
0177     u32 revision = fields[1].integer.value;
0178 
0179     switch (revision) {
0180     case 1:
0181         if (record->package.count != 6)
0182             return AE_ERROR;
0183         for (i = 2; i < 6; i++)
0184             if (fields[i].type != ACPI_TYPE_INTEGER)
0185                 return AE_ERROR;
0186         hpx0->revision        = revision;
0187         hpx0->cache_line_size = fields[2].integer.value;
0188         hpx0->latency_timer   = fields[3].integer.value;
0189         hpx0->enable_serr     = fields[4].integer.value;
0190         hpx0->enable_perr     = fields[5].integer.value;
0191         break;
0192     default:
0193         pr_warn("%s: Type 0 Revision %d record not supported\n",
0194                __func__, revision);
0195         return AE_ERROR;
0196     }
0197     return AE_OK;
0198 }
0199 
0200 /* _HPX PCI-X Setting Record (Type 1) */
0201 struct hpx_type1 {
0202     u32 revision;
0203     u8  max_mem_read;
0204     u8  avg_max_split;
0205     u16 tot_max_split;
0206 };
0207 
0208 static void program_hpx_type1(struct pci_dev *dev, struct hpx_type1 *hpx)
0209 {
0210     int pos;
0211 
0212     if (!hpx)
0213         return;
0214 
0215     pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
0216     if (!pos)
0217         return;
0218 
0219     pci_warn(dev, "PCI-X settings not supported\n");
0220 }
0221 
0222 static acpi_status decode_type1_hpx_record(union acpi_object *record,
0223                        struct hpx_type1 *hpx1)
0224 {
0225     int i;
0226     union acpi_object *fields = record->package.elements;
0227     u32 revision = fields[1].integer.value;
0228 
0229     switch (revision) {
0230     case 1:
0231         if (record->package.count != 5)
0232             return AE_ERROR;
0233         for (i = 2; i < 5; i++)
0234             if (fields[i].type != ACPI_TYPE_INTEGER)
0235                 return AE_ERROR;
0236         hpx1->revision      = revision;
0237         hpx1->max_mem_read  = fields[2].integer.value;
0238         hpx1->avg_max_split = fields[3].integer.value;
0239         hpx1->tot_max_split = fields[4].integer.value;
0240         break;
0241     default:
0242         pr_warn("%s: Type 1 Revision %d record not supported\n",
0243                __func__, revision);
0244         return AE_ERROR;
0245     }
0246     return AE_OK;
0247 }
0248 
0249 static bool pcie_root_rcb_set(struct pci_dev *dev)
0250 {
0251     struct pci_dev *rp = pcie_find_root_port(dev);
0252     u16 lnkctl;
0253 
0254     if (!rp)
0255         return false;
0256 
0257     pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
0258     if (lnkctl & PCI_EXP_LNKCTL_RCB)
0259         return true;
0260 
0261     return false;
0262 }
0263 
0264 /* _HPX PCI Express Setting Record (Type 2) */
0265 struct hpx_type2 {
0266     u32 revision;
0267     u32 unc_err_mask_and;
0268     u32 unc_err_mask_or;
0269     u32 unc_err_sever_and;
0270     u32 unc_err_sever_or;
0271     u32 cor_err_mask_and;
0272     u32 cor_err_mask_or;
0273     u32 adv_err_cap_and;
0274     u32 adv_err_cap_or;
0275     u16 pci_exp_devctl_and;
0276     u16 pci_exp_devctl_or;
0277     u16 pci_exp_lnkctl_and;
0278     u16 pci_exp_lnkctl_or;
0279     u32 sec_unc_err_sever_and;
0280     u32 sec_unc_err_sever_or;
0281     u32 sec_unc_err_mask_and;
0282     u32 sec_unc_err_mask_or;
0283 };
0284 
0285 static void program_hpx_type2(struct pci_dev *dev, struct hpx_type2 *hpx)
0286 {
0287     int pos;
0288     u32 reg32;
0289 
0290     if (!hpx)
0291         return;
0292 
0293     if (!pci_is_pcie(dev))
0294         return;
0295 
0296     if (hpx->revision > 1) {
0297         pci_warn(dev, "PCIe settings rev %d not supported\n",
0298              hpx->revision);
0299         return;
0300     }
0301 
0302     /*
0303      * Don't allow _HPX to change MPS or MRRS settings.  We manage
0304      * those to make sure they're consistent with the rest of the
0305      * platform.
0306      */
0307     hpx->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
0308                     PCI_EXP_DEVCTL_READRQ;
0309     hpx->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
0310                     PCI_EXP_DEVCTL_READRQ);
0311 
0312     /* Initialize Device Control Register */
0313     pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
0314             ~hpx->pci_exp_devctl_and, hpx->pci_exp_devctl_or);
0315 
0316     /* Initialize Link Control Register */
0317     if (pcie_cap_has_lnkctl(dev)) {
0318 
0319         /*
0320          * If the Root Port supports Read Completion Boundary of
0321          * 128, set RCB to 128.  Otherwise, clear it.
0322          */
0323         hpx->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
0324         hpx->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
0325         if (pcie_root_rcb_set(dev))
0326             hpx->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
0327 
0328         pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
0329             ~hpx->pci_exp_lnkctl_and, hpx->pci_exp_lnkctl_or);
0330     }
0331 
0332     /* Find Advanced Error Reporting Enhanced Capability */
0333     pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
0334     if (!pos)
0335         return;
0336 
0337     /* Initialize Uncorrectable Error Mask Register */
0338     pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32);
0339     reg32 = (reg32 & hpx->unc_err_mask_and) | hpx->unc_err_mask_or;
0340     pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
0341 
0342     /* Initialize Uncorrectable Error Severity Register */
0343     pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32);
0344     reg32 = (reg32 & hpx->unc_err_sever_and) | hpx->unc_err_sever_or;
0345     pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
0346 
0347     /* Initialize Correctable Error Mask Register */
0348     pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32);
0349     reg32 = (reg32 & hpx->cor_err_mask_and) | hpx->cor_err_mask_or;
0350     pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
0351 
0352     /* Initialize Advanced Error Capabilities and Control Register */
0353     pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
0354     reg32 = (reg32 & hpx->adv_err_cap_and) | hpx->adv_err_cap_or;
0355 
0356     /* Don't enable ECRC generation or checking if unsupported */
0357     if (!(reg32 & PCI_ERR_CAP_ECRC_GENC))
0358         reg32 &= ~PCI_ERR_CAP_ECRC_GENE;
0359     if (!(reg32 & PCI_ERR_CAP_ECRC_CHKC))
0360         reg32 &= ~PCI_ERR_CAP_ECRC_CHKE;
0361     pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
0362 
0363     /*
0364      * FIXME: The following two registers are not supported yet.
0365      *
0366      *   o Secondary Uncorrectable Error Severity Register
0367      *   o Secondary Uncorrectable Error Mask Register
0368      */
0369 }
0370 
0371 static acpi_status decode_type2_hpx_record(union acpi_object *record,
0372                        struct hpx_type2 *hpx2)
0373 {
0374     int i;
0375     union acpi_object *fields = record->package.elements;
0376     u32 revision = fields[1].integer.value;
0377 
0378     switch (revision) {
0379     case 1:
0380         if (record->package.count != 18)
0381             return AE_ERROR;
0382         for (i = 2; i < 18; i++)
0383             if (fields[i].type != ACPI_TYPE_INTEGER)
0384                 return AE_ERROR;
0385         hpx2->revision      = revision;
0386         hpx2->unc_err_mask_and      = fields[2].integer.value;
0387         hpx2->unc_err_mask_or       = fields[3].integer.value;
0388         hpx2->unc_err_sever_and     = fields[4].integer.value;
0389         hpx2->unc_err_sever_or      = fields[5].integer.value;
0390         hpx2->cor_err_mask_and      = fields[6].integer.value;
0391         hpx2->cor_err_mask_or       = fields[7].integer.value;
0392         hpx2->adv_err_cap_and       = fields[8].integer.value;
0393         hpx2->adv_err_cap_or        = fields[9].integer.value;
0394         hpx2->pci_exp_devctl_and    = fields[10].integer.value;
0395         hpx2->pci_exp_devctl_or     = fields[11].integer.value;
0396         hpx2->pci_exp_lnkctl_and    = fields[12].integer.value;
0397         hpx2->pci_exp_lnkctl_or     = fields[13].integer.value;
0398         hpx2->sec_unc_err_sever_and = fields[14].integer.value;
0399         hpx2->sec_unc_err_sever_or  = fields[15].integer.value;
0400         hpx2->sec_unc_err_mask_and  = fields[16].integer.value;
0401         hpx2->sec_unc_err_mask_or   = fields[17].integer.value;
0402         break;
0403     default:
0404         pr_warn("%s: Type 2 Revision %d record not supported\n",
0405                __func__, revision);
0406         return AE_ERROR;
0407     }
0408     return AE_OK;
0409 }
0410 
0411 /* _HPX PCI Express Setting Record (Type 3) */
0412 struct hpx_type3 {
0413     u16 device_type;
0414     u16 function_type;
0415     u16 config_space_location;
0416     u16 pci_exp_cap_id;
0417     u16 pci_exp_cap_ver;
0418     u16 pci_exp_vendor_id;
0419     u16 dvsec_id;
0420     u16 dvsec_rev;
0421     u16 match_offset;
0422     u32 match_mask_and;
0423     u32 match_value;
0424     u16 reg_offset;
0425     u32 reg_mask_and;
0426     u32 reg_mask_or;
0427 };
0428 
0429 enum hpx_type3_dev_type {
0430     HPX_TYPE_ENDPOINT   = BIT(0),
0431     HPX_TYPE_LEG_END    = BIT(1),
0432     HPX_TYPE_RC_END     = BIT(2),
0433     HPX_TYPE_RC_EC      = BIT(3),
0434     HPX_TYPE_ROOT_PORT  = BIT(4),
0435     HPX_TYPE_UPSTREAM   = BIT(5),
0436     HPX_TYPE_DOWNSTREAM = BIT(6),
0437     HPX_TYPE_PCI_BRIDGE = BIT(7),
0438     HPX_TYPE_PCIE_BRIDGE    = BIT(8),
0439 };
0440 
0441 static u16 hpx3_device_type(struct pci_dev *dev)
0442 {
0443     u16 pcie_type = pci_pcie_type(dev);
0444     static const int pcie_to_hpx3_type[] = {
0445         [PCI_EXP_TYPE_ENDPOINT]    = HPX_TYPE_ENDPOINT,
0446         [PCI_EXP_TYPE_LEG_END]     = HPX_TYPE_LEG_END,
0447         [PCI_EXP_TYPE_RC_END]      = HPX_TYPE_RC_END,
0448         [PCI_EXP_TYPE_RC_EC]       = HPX_TYPE_RC_EC,
0449         [PCI_EXP_TYPE_ROOT_PORT]   = HPX_TYPE_ROOT_PORT,
0450         [PCI_EXP_TYPE_UPSTREAM]    = HPX_TYPE_UPSTREAM,
0451         [PCI_EXP_TYPE_DOWNSTREAM]  = HPX_TYPE_DOWNSTREAM,
0452         [PCI_EXP_TYPE_PCI_BRIDGE]  = HPX_TYPE_PCI_BRIDGE,
0453         [PCI_EXP_TYPE_PCIE_BRIDGE] = HPX_TYPE_PCIE_BRIDGE,
0454     };
0455 
0456     if (pcie_type >= ARRAY_SIZE(pcie_to_hpx3_type))
0457         return 0;
0458 
0459     return pcie_to_hpx3_type[pcie_type];
0460 }
0461 
0462 enum hpx_type3_fn_type {
0463     HPX_FN_NORMAL       = BIT(0),
0464     HPX_FN_SRIOV_PHYS   = BIT(1),
0465     HPX_FN_SRIOV_VIRT   = BIT(2),
0466 };
0467 
0468 static u8 hpx3_function_type(struct pci_dev *dev)
0469 {
0470     if (dev->is_virtfn)
0471         return HPX_FN_SRIOV_VIRT;
0472     else if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV) > 0)
0473         return HPX_FN_SRIOV_PHYS;
0474     else
0475         return HPX_FN_NORMAL;
0476 }
0477 
0478 static bool hpx3_cap_ver_matches(u8 pcie_cap_id, u8 hpx3_cap_id)
0479 {
0480     u8 cap_ver = hpx3_cap_id & 0xf;
0481 
0482     if ((hpx3_cap_id & BIT(4)) && cap_ver >= pcie_cap_id)
0483         return true;
0484     else if (cap_ver == pcie_cap_id)
0485         return true;
0486 
0487     return false;
0488 }
0489 
0490 enum hpx_type3_cfg_loc {
0491     HPX_CFG_PCICFG      = 0,
0492     HPX_CFG_PCIE_CAP    = 1,
0493     HPX_CFG_PCIE_CAP_EXT    = 2,
0494     HPX_CFG_VEND_CAP    = 3,
0495     HPX_CFG_DVSEC       = 4,
0496     HPX_CFG_MAX,
0497 };
0498 
0499 static void program_hpx_type3_register(struct pci_dev *dev,
0500                        const struct hpx_type3 *reg)
0501 {
0502     u32 match_reg, write_reg, header, orig_value;
0503     u16 pos;
0504 
0505     if (!(hpx3_device_type(dev) & reg->device_type))
0506         return;
0507 
0508     if (!(hpx3_function_type(dev) & reg->function_type))
0509         return;
0510 
0511     switch (reg->config_space_location) {
0512     case HPX_CFG_PCICFG:
0513         pos = 0;
0514         break;
0515     case HPX_CFG_PCIE_CAP:
0516         pos = pci_find_capability(dev, reg->pci_exp_cap_id);
0517         if (pos == 0)
0518             return;
0519 
0520         break;
0521     case HPX_CFG_PCIE_CAP_EXT:
0522         pos = pci_find_ext_capability(dev, reg->pci_exp_cap_id);
0523         if (pos == 0)
0524             return;
0525 
0526         pci_read_config_dword(dev, pos, &header);
0527         if (!hpx3_cap_ver_matches(PCI_EXT_CAP_VER(header),
0528                       reg->pci_exp_cap_ver))
0529             return;
0530 
0531         break;
0532     case HPX_CFG_VEND_CAP:
0533     case HPX_CFG_DVSEC:
0534     default:
0535         pci_warn(dev, "Encountered _HPX type 3 with unsupported config space location");
0536         return;
0537     }
0538 
0539     pci_read_config_dword(dev, pos + reg->match_offset, &match_reg);
0540 
0541     if ((match_reg & reg->match_mask_and) != reg->match_value)
0542         return;
0543 
0544     pci_read_config_dword(dev, pos + reg->reg_offset, &write_reg);
0545     orig_value = write_reg;
0546     write_reg &= reg->reg_mask_and;
0547     write_reg |= reg->reg_mask_or;
0548 
0549     if (orig_value == write_reg)
0550         return;
0551 
0552     pci_write_config_dword(dev, pos + reg->reg_offset, write_reg);
0553 
0554     pci_dbg(dev, "Applied _HPX3 at [0x%x]: 0x%08x -> 0x%08x",
0555         pos, orig_value, write_reg);
0556 }
0557 
0558 static void program_hpx_type3(struct pci_dev *dev, struct hpx_type3 *hpx)
0559 {
0560     if (!hpx)
0561         return;
0562 
0563     if (!pci_is_pcie(dev))
0564         return;
0565 
0566     program_hpx_type3_register(dev, hpx);
0567 }
0568 
0569 static void parse_hpx3_register(struct hpx_type3 *hpx3_reg,
0570                 union acpi_object *reg_fields)
0571 {
0572     hpx3_reg->device_type            = reg_fields[0].integer.value;
0573     hpx3_reg->function_type          = reg_fields[1].integer.value;
0574     hpx3_reg->config_space_location  = reg_fields[2].integer.value;
0575     hpx3_reg->pci_exp_cap_id         = reg_fields[3].integer.value;
0576     hpx3_reg->pci_exp_cap_ver        = reg_fields[4].integer.value;
0577     hpx3_reg->pci_exp_vendor_id      = reg_fields[5].integer.value;
0578     hpx3_reg->dvsec_id               = reg_fields[6].integer.value;
0579     hpx3_reg->dvsec_rev              = reg_fields[7].integer.value;
0580     hpx3_reg->match_offset           = reg_fields[8].integer.value;
0581     hpx3_reg->match_mask_and         = reg_fields[9].integer.value;
0582     hpx3_reg->match_value            = reg_fields[10].integer.value;
0583     hpx3_reg->reg_offset             = reg_fields[11].integer.value;
0584     hpx3_reg->reg_mask_and           = reg_fields[12].integer.value;
0585     hpx3_reg->reg_mask_or            = reg_fields[13].integer.value;
0586 }
0587 
0588 static acpi_status program_type3_hpx_record(struct pci_dev *dev,
0589                        union acpi_object *record)
0590 {
0591     union acpi_object *fields = record->package.elements;
0592     u32 desc_count, expected_length, revision;
0593     union acpi_object *reg_fields;
0594     struct hpx_type3 hpx3;
0595     int i;
0596 
0597     revision = fields[1].integer.value;
0598     switch (revision) {
0599     case 1:
0600         desc_count = fields[2].integer.value;
0601         expected_length = 3 + desc_count * 14;
0602 
0603         if (record->package.count != expected_length)
0604             return AE_ERROR;
0605 
0606         for (i = 2; i < expected_length; i++)
0607             if (fields[i].type != ACPI_TYPE_INTEGER)
0608                 return AE_ERROR;
0609 
0610         for (i = 0; i < desc_count; i++) {
0611             reg_fields = fields + 3 + i * 14;
0612             parse_hpx3_register(&hpx3, reg_fields);
0613             program_hpx_type3(dev, &hpx3);
0614         }
0615 
0616         break;
0617     default:
0618         printk(KERN_WARNING
0619             "%s: Type 3 Revision %d record not supported\n",
0620             __func__, revision);
0621         return AE_ERROR;
0622     }
0623     return AE_OK;
0624 }
0625 
0626 static acpi_status acpi_run_hpx(struct pci_dev *dev, acpi_handle handle)
0627 {
0628     acpi_status status;
0629     struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
0630     union acpi_object *package, *record, *fields;
0631     struct hpx_type0 hpx0;
0632     struct hpx_type1 hpx1;
0633     struct hpx_type2 hpx2;
0634     u32 type;
0635     int i;
0636 
0637     status = acpi_evaluate_object(handle, "_HPX", NULL, &buffer);
0638     if (ACPI_FAILURE(status))
0639         return status;
0640 
0641     package = (union acpi_object *)buffer.pointer;
0642     if (package->type != ACPI_TYPE_PACKAGE) {
0643         status = AE_ERROR;
0644         goto exit;
0645     }
0646 
0647     for (i = 0; i < package->package.count; i++) {
0648         record = &package->package.elements[i];
0649         if (record->type != ACPI_TYPE_PACKAGE) {
0650             status = AE_ERROR;
0651             goto exit;
0652         }
0653 
0654         fields = record->package.elements;
0655         if (fields[0].type != ACPI_TYPE_INTEGER ||
0656             fields[1].type != ACPI_TYPE_INTEGER) {
0657             status = AE_ERROR;
0658             goto exit;
0659         }
0660 
0661         type = fields[0].integer.value;
0662         switch (type) {
0663         case 0:
0664             memset(&hpx0, 0, sizeof(hpx0));
0665             status = decode_type0_hpx_record(record, &hpx0);
0666             if (ACPI_FAILURE(status))
0667                 goto exit;
0668             program_hpx_type0(dev, &hpx0);
0669             break;
0670         case 1:
0671             memset(&hpx1, 0, sizeof(hpx1));
0672             status = decode_type1_hpx_record(record, &hpx1);
0673             if (ACPI_FAILURE(status))
0674                 goto exit;
0675             program_hpx_type1(dev, &hpx1);
0676             break;
0677         case 2:
0678             memset(&hpx2, 0, sizeof(hpx2));
0679             status = decode_type2_hpx_record(record, &hpx2);
0680             if (ACPI_FAILURE(status))
0681                 goto exit;
0682             program_hpx_type2(dev, &hpx2);
0683             break;
0684         case 3:
0685             status = program_type3_hpx_record(dev, record);
0686             if (ACPI_FAILURE(status))
0687                 goto exit;
0688             break;
0689         default:
0690             pr_err("%s: Type %d record not supported\n",
0691                    __func__, type);
0692             status = AE_ERROR;
0693             goto exit;
0694         }
0695     }
0696  exit:
0697     kfree(buffer.pointer);
0698     return status;
0699 }
0700 
0701 static acpi_status acpi_run_hpp(struct pci_dev *dev, acpi_handle handle)
0702 {
0703     acpi_status status;
0704     struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
0705     union acpi_object *package, *fields;
0706     struct hpx_type0 hpx0;
0707     int i;
0708 
0709     memset(&hpx0, 0, sizeof(hpx0));
0710 
0711     status = acpi_evaluate_object(handle, "_HPP", NULL, &buffer);
0712     if (ACPI_FAILURE(status))
0713         return status;
0714 
0715     package = (union acpi_object *) buffer.pointer;
0716     if (package->type != ACPI_TYPE_PACKAGE ||
0717         package->package.count != 4) {
0718         status = AE_ERROR;
0719         goto exit;
0720     }
0721 
0722     fields = package->package.elements;
0723     for (i = 0; i < 4; i++) {
0724         if (fields[i].type != ACPI_TYPE_INTEGER) {
0725             status = AE_ERROR;
0726             goto exit;
0727         }
0728     }
0729 
0730     hpx0.revision        = 1;
0731     hpx0.cache_line_size = fields[0].integer.value;
0732     hpx0.latency_timer   = fields[1].integer.value;
0733     hpx0.enable_serr     = fields[2].integer.value;
0734     hpx0.enable_perr     = fields[3].integer.value;
0735 
0736     program_hpx_type0(dev, &hpx0);
0737 
0738 exit:
0739     kfree(buffer.pointer);
0740     return status;
0741 }
0742 
0743 /* pci_acpi_program_hp_params
0744  *
0745  * @dev - the pci_dev for which we want parameters
0746  */
0747 int pci_acpi_program_hp_params(struct pci_dev *dev)
0748 {
0749     acpi_status status;
0750     acpi_handle handle, phandle;
0751     struct pci_bus *pbus;
0752 
0753     if (acpi_pci_disabled)
0754         return -ENODEV;
0755 
0756     handle = NULL;
0757     for (pbus = dev->bus; pbus; pbus = pbus->parent) {
0758         handle = acpi_pci_get_bridge_handle(pbus);
0759         if (handle)
0760             break;
0761     }
0762 
0763     /*
0764      * _HPP settings apply to all child buses, until another _HPP is
0765      * encountered. If we don't find an _HPP for the input pci dev,
0766      * look for it in the parent device scope since that would apply to
0767      * this pci dev.
0768      */
0769     while (handle) {
0770         status = acpi_run_hpx(dev, handle);
0771         if (ACPI_SUCCESS(status))
0772             return 0;
0773         status = acpi_run_hpp(dev, handle);
0774         if (ACPI_SUCCESS(status))
0775             return 0;
0776         if (acpi_is_root_bridge(handle))
0777             break;
0778         status = acpi_get_parent(handle, &phandle);
0779         if (ACPI_FAILURE(status))
0780             break;
0781         handle = phandle;
0782     }
0783     return -ENODEV;
0784 }
0785 
0786 /**
0787  * pciehp_is_native - Check whether a hotplug port is handled by the OS
0788  * @bridge: Hotplug port to check
0789  *
0790  * Returns true if the given @bridge is handled by the native PCIe hotplug
0791  * driver.
0792  */
0793 bool pciehp_is_native(struct pci_dev *bridge)
0794 {
0795     const struct pci_host_bridge *host;
0796     u32 slot_cap;
0797 
0798     if (!IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
0799         return false;
0800 
0801     pcie_capability_read_dword(bridge, PCI_EXP_SLTCAP, &slot_cap);
0802     if (!(slot_cap & PCI_EXP_SLTCAP_HPC))
0803         return false;
0804 
0805     if (pcie_ports_native)
0806         return true;
0807 
0808     host = pci_find_host_bridge(bridge->bus);
0809     return host->native_pcie_hotplug;
0810 }
0811 
0812 /**
0813  * shpchp_is_native - Check whether a hotplug port is handled by the OS
0814  * @bridge: Hotplug port to check
0815  *
0816  * Returns true if the given @bridge is handled by the native SHPC hotplug
0817  * driver.
0818  */
0819 bool shpchp_is_native(struct pci_dev *bridge)
0820 {
0821     return bridge->shpc_managed;
0822 }
0823 
0824 /**
0825  * pci_acpi_wake_bus - Root bus wakeup notification fork function.
0826  * @context: Device wakeup context.
0827  */
0828 static void pci_acpi_wake_bus(struct acpi_device_wakeup_context *context)
0829 {
0830     struct acpi_device *adev;
0831     struct acpi_pci_root *root;
0832 
0833     adev = container_of(context, struct acpi_device, wakeup.context);
0834     root = acpi_driver_data(adev);
0835     pci_pme_wakeup_bus(root->bus);
0836 }
0837 
0838 /**
0839  * pci_acpi_wake_dev - PCI device wakeup notification work function.
0840  * @context: Device wakeup context.
0841  */
0842 static void pci_acpi_wake_dev(struct acpi_device_wakeup_context *context)
0843 {
0844     struct pci_dev *pci_dev;
0845 
0846     pci_dev = to_pci_dev(context->dev);
0847 
0848     if (pci_dev->pme_poll)
0849         pci_dev->pme_poll = false;
0850 
0851     if (pci_dev->current_state == PCI_D3cold) {
0852         pci_wakeup_event(pci_dev);
0853         pm_request_resume(&pci_dev->dev);
0854         return;
0855     }
0856 
0857     /* Clear PME Status if set. */
0858     if (pci_dev->pme_support)
0859         pci_check_pme_status(pci_dev);
0860 
0861     pci_wakeup_event(pci_dev);
0862     pm_request_resume(&pci_dev->dev);
0863 
0864     pci_pme_wakeup_bus(pci_dev->subordinate);
0865 }
0866 
0867 /**
0868  * pci_acpi_add_bus_pm_notifier - Register PM notifier for root PCI bus.
0869  * @dev: PCI root bridge ACPI device.
0870  */
0871 acpi_status pci_acpi_add_bus_pm_notifier(struct acpi_device *dev)
0872 {
0873     return acpi_add_pm_notifier(dev, NULL, pci_acpi_wake_bus);
0874 }
0875 
0876 /**
0877  * pci_acpi_add_pm_notifier - Register PM notifier for given PCI device.
0878  * @dev: ACPI device to add the notifier for.
0879  * @pci_dev: PCI device to check for the PME status if an event is signaled.
0880  */
0881 acpi_status pci_acpi_add_pm_notifier(struct acpi_device *dev,
0882                      struct pci_dev *pci_dev)
0883 {
0884     return acpi_add_pm_notifier(dev, &pci_dev->dev, pci_acpi_wake_dev);
0885 }
0886 
0887 /*
0888  * _SxD returns the D-state with the highest power
0889  * (lowest D-state number) supported in the S-state "x".
0890  *
0891  * If the devices does not have a _PRW
0892  * (Power Resources for Wake) supporting system wakeup from "x"
0893  * then the OS is free to choose a lower power (higher number
0894  * D-state) than the return value from _SxD.
0895  *
0896  * But if _PRW is enabled at S-state "x", the OS
0897  * must not choose a power lower than _SxD --
0898  * unless the device has an _SxW method specifying
0899  * the lowest power (highest D-state number) the device
0900  * may enter while still able to wake the system.
0901  *
0902  * ie. depending on global OS policy:
0903  *
0904  * if (_PRW at S-state x)
0905  *  choose from highest power _SxD to lowest power _SxW
0906  * else // no _PRW at S-state x
0907  *  choose highest power _SxD or any lower power
0908  */
0909 
0910 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
0911 {
0912     int acpi_state, d_max;
0913 
0914     if (pdev->no_d3cold)
0915         d_max = ACPI_STATE_D3_HOT;
0916     else
0917         d_max = ACPI_STATE_D3_COLD;
0918     acpi_state = acpi_pm_device_sleep_state(&pdev->dev, NULL, d_max);
0919     if (acpi_state < 0)
0920         return PCI_POWER_ERROR;
0921 
0922     switch (acpi_state) {
0923     case ACPI_STATE_D0:
0924         return PCI_D0;
0925     case ACPI_STATE_D1:
0926         return PCI_D1;
0927     case ACPI_STATE_D2:
0928         return PCI_D2;
0929     case ACPI_STATE_D3_HOT:
0930         return PCI_D3hot;
0931     case ACPI_STATE_D3_COLD:
0932         return PCI_D3cold;
0933     }
0934     return PCI_POWER_ERROR;
0935 }
0936 
0937 static struct acpi_device *acpi_pci_find_companion(struct device *dev);
0938 
0939 void pci_set_acpi_fwnode(struct pci_dev *dev)
0940 {
0941     if (!dev_fwnode(&dev->dev) && !pci_dev_is_added(dev))
0942         ACPI_COMPANION_SET(&dev->dev,
0943                    acpi_pci_find_companion(&dev->dev));
0944 }
0945 
0946 /**
0947  * pci_dev_acpi_reset - do a function level reset using _RST method
0948  * @dev: device to reset
0949  * @probe: if true, return 0 if device supports _RST
0950  */
0951 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
0952 {
0953     acpi_handle handle = ACPI_HANDLE(&dev->dev);
0954 
0955     if (!handle || !acpi_has_method(handle, "_RST"))
0956         return -ENOTTY;
0957 
0958     if (probe)
0959         return 0;
0960 
0961     if (ACPI_FAILURE(acpi_evaluate_object(handle, "_RST", NULL, NULL))) {
0962         pci_warn(dev, "ACPI _RST failed\n");
0963         return -ENOTTY;
0964     }
0965 
0966     return 0;
0967 }
0968 
0969 bool acpi_pci_power_manageable(struct pci_dev *dev)
0970 {
0971     struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
0972 
0973     return adev && acpi_device_power_manageable(adev);
0974 }
0975 
0976 bool acpi_pci_bridge_d3(struct pci_dev *dev)
0977 {
0978     struct pci_dev *rpdev;
0979     struct acpi_device *adev;
0980     acpi_status status;
0981     unsigned long long state;
0982     const union acpi_object *obj;
0983 
0984     if (acpi_pci_disabled || !dev->is_hotplug_bridge)
0985         return false;
0986 
0987     /* Assume D3 support if the bridge is power-manageable by ACPI. */
0988     if (acpi_pci_power_manageable(dev))
0989         return true;
0990 
0991     rpdev = pcie_find_root_port(dev);
0992     if (!rpdev)
0993         return false;
0994 
0995     adev = ACPI_COMPANION(&rpdev->dev);
0996     if (!adev)
0997         return false;
0998 
0999     /*
1000      * If the Root Port cannot signal wakeup signals at all, i.e., it
1001      * doesn't supply a wakeup GPE via _PRW, it cannot signal hotplug
1002      * events from low-power states including D3hot and D3cold.
1003      */
1004     if (!adev->wakeup.flags.valid)
1005         return false;
1006 
1007     /*
1008      * If the Root Port cannot wake itself from D3hot or D3cold, we
1009      * can't use D3.
1010      */
1011     status = acpi_evaluate_integer(adev->handle, "_S0W", NULL, &state);
1012     if (ACPI_SUCCESS(status) && state < ACPI_STATE_D3_HOT)
1013         return false;
1014 
1015     /*
1016      * The "HotPlugSupportInD3" property in a Root Port _DSD indicates
1017      * the Port can signal hotplug events while in D3.  We assume any
1018      * bridges *below* that Root Port can also signal hotplug events
1019      * while in D3.
1020      */
1021     if (!acpi_dev_get_property(adev, "HotPlugSupportInD3",
1022                    ACPI_TYPE_INTEGER, &obj) &&
1023         obj->integer.value == 1)
1024         return true;
1025 
1026     return false;
1027 }
1028 
1029 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1030 {
1031     struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
1032     static const u8 state_conv[] = {
1033         [PCI_D0] = ACPI_STATE_D0,
1034         [PCI_D1] = ACPI_STATE_D1,
1035         [PCI_D2] = ACPI_STATE_D2,
1036         [PCI_D3hot] = ACPI_STATE_D3_HOT,
1037         [PCI_D3cold] = ACPI_STATE_D3_COLD,
1038     };
1039     int error = -EINVAL;
1040 
1041     /* If the ACPI device has _EJ0, ignore the device */
1042     if (!adev || acpi_has_method(adev->handle, "_EJ0"))
1043         return -ENODEV;
1044 
1045     switch (state) {
1046     case PCI_D3cold:
1047         if (dev_pm_qos_flags(&dev->dev, PM_QOS_FLAG_NO_POWER_OFF) ==
1048                 PM_QOS_FLAGS_ALL) {
1049             error = -EBUSY;
1050             break;
1051         }
1052         fallthrough;
1053     case PCI_D0:
1054     case PCI_D1:
1055     case PCI_D2:
1056     case PCI_D3hot:
1057         error = acpi_device_set_power(adev, state_conv[state]);
1058     }
1059 
1060     if (!error)
1061         pci_dbg(dev, "power state changed by ACPI to %s\n",
1062                 acpi_power_state_string(adev->power.state));
1063 
1064     return error;
1065 }
1066 
1067 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
1068 {
1069     struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
1070     static const pci_power_t state_conv[] = {
1071         [ACPI_STATE_D0]      = PCI_D0,
1072         [ACPI_STATE_D1]      = PCI_D1,
1073         [ACPI_STATE_D2]      = PCI_D2,
1074         [ACPI_STATE_D3_HOT]  = PCI_D3hot,
1075         [ACPI_STATE_D3_COLD] = PCI_D3cold,
1076     };
1077     int state;
1078 
1079     if (!adev || !acpi_device_power_manageable(adev))
1080         return PCI_UNKNOWN;
1081 
1082     state = adev->power.state;
1083     if (state == ACPI_STATE_UNKNOWN)
1084         return PCI_UNKNOWN;
1085 
1086     return state_conv[state];
1087 }
1088 
1089 void acpi_pci_refresh_power_state(struct pci_dev *dev)
1090 {
1091     struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
1092 
1093     if (adev && acpi_device_power_manageable(adev))
1094         acpi_device_update_power(adev, NULL);
1095 }
1096 
1097 static int acpi_pci_propagate_wakeup(struct pci_bus *bus, bool enable)
1098 {
1099     while (bus->parent) {
1100         if (acpi_pm_device_can_wakeup(&bus->self->dev))
1101             return acpi_pm_set_device_wakeup(&bus->self->dev, enable);
1102 
1103         bus = bus->parent;
1104     }
1105 
1106     /* We have reached the root bus. */
1107     if (bus->bridge) {
1108         if (acpi_pm_device_can_wakeup(bus->bridge))
1109             return acpi_pm_set_device_wakeup(bus->bridge, enable);
1110     }
1111     return 0;
1112 }
1113 
1114 int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
1115 {
1116     if (acpi_pci_disabled)
1117         return 0;
1118 
1119     if (acpi_pm_device_can_wakeup(&dev->dev))
1120         return acpi_pm_set_device_wakeup(&dev->dev, enable);
1121 
1122     return acpi_pci_propagate_wakeup(dev->bus, enable);
1123 }
1124 
1125 bool acpi_pci_need_resume(struct pci_dev *dev)
1126 {
1127     struct acpi_device *adev;
1128 
1129     if (acpi_pci_disabled)
1130         return false;
1131 
1132     /*
1133      * In some cases (eg. Samsung 305V4A) leaving a bridge in suspend over
1134      * system-wide suspend/resume confuses the platform firmware, so avoid
1135      * doing that.  According to Section 16.1.6 of ACPI 6.2, endpoint
1136      * devices are expected to be in D3 before invoking the S3 entry path
1137      * from the firmware, so they should not be affected by this issue.
1138      */
1139     if (pci_is_bridge(dev) && acpi_target_system_state() != ACPI_STATE_S0)
1140         return true;
1141 
1142     adev = ACPI_COMPANION(&dev->dev);
1143     if (!adev || !acpi_device_power_manageable(adev))
1144         return false;
1145 
1146     if (adev->wakeup.flags.valid &&
1147         device_may_wakeup(&dev->dev) != !!adev->wakeup.prepare_count)
1148         return true;
1149 
1150     if (acpi_target_system_state() == ACPI_STATE_S0)
1151         return false;
1152 
1153     return !!adev->power.flags.dsw_present;
1154 }
1155 
1156 void acpi_pci_add_bus(struct pci_bus *bus)
1157 {
1158     union acpi_object *obj;
1159     struct pci_host_bridge *bridge;
1160 
1161     if (acpi_pci_disabled || !bus->bridge || !ACPI_HANDLE(bus->bridge))
1162         return;
1163 
1164     acpi_pci_slot_enumerate(bus);
1165     acpiphp_enumerate_slots(bus);
1166 
1167     /*
1168      * For a host bridge, check its _DSM for function 8 and if
1169      * that is available, mark it in pci_host_bridge.
1170      */
1171     if (!pci_is_root_bus(bus))
1172         return;
1173 
1174     obj = acpi_evaluate_dsm(ACPI_HANDLE(bus->bridge), &pci_acpi_dsm_guid, 3,
1175                 DSM_PCI_POWER_ON_RESET_DELAY, NULL);
1176     if (!obj)
1177         return;
1178 
1179     if (obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 1) {
1180         bridge = pci_find_host_bridge(bus);
1181         bridge->ignore_reset_delay = 1;
1182     }
1183     ACPI_FREE(obj);
1184 }
1185 
1186 void acpi_pci_remove_bus(struct pci_bus *bus)
1187 {
1188     if (acpi_pci_disabled || !bus->bridge)
1189         return;
1190 
1191     acpiphp_remove_slots(bus);
1192     acpi_pci_slot_remove(bus);
1193 }
1194 
1195 /* ACPI bus type */
1196 
1197 
1198 static DECLARE_RWSEM(pci_acpi_companion_lookup_sem);
1199 static struct acpi_device *(*pci_acpi_find_companion_hook)(struct pci_dev *);
1200 
1201 /**
1202  * pci_acpi_set_companion_lookup_hook - Set ACPI companion lookup callback.
1203  * @func: ACPI companion lookup callback pointer or NULL.
1204  *
1205  * Set a special ACPI companion lookup callback for PCI devices whose companion
1206  * objects in the ACPI namespace have _ADR with non-standard bus-device-function
1207  * encodings.
1208  *
1209  * Return 0 on success or a negative error code on failure (in which case no
1210  * changes are made).
1211  *
1212  * The caller is responsible for the appropriate ordering of the invocations of
1213  * this function with respect to the enumeration of the PCI devices needing the
1214  * callback installed by it.
1215  */
1216 int pci_acpi_set_companion_lookup_hook(struct acpi_device *(*func)(struct pci_dev *))
1217 {
1218     int ret;
1219 
1220     if (!func)
1221         return -EINVAL;
1222 
1223     down_write(&pci_acpi_companion_lookup_sem);
1224 
1225     if (pci_acpi_find_companion_hook) {
1226         ret = -EBUSY;
1227     } else {
1228         pci_acpi_find_companion_hook = func;
1229         ret = 0;
1230     }
1231 
1232     up_write(&pci_acpi_companion_lookup_sem);
1233 
1234     return ret;
1235 }
1236 EXPORT_SYMBOL_GPL(pci_acpi_set_companion_lookup_hook);
1237 
1238 /**
1239  * pci_acpi_clear_companion_lookup_hook - Clear ACPI companion lookup callback.
1240  *
1241  * Clear the special ACPI companion lookup callback previously set by
1242  * pci_acpi_set_companion_lookup_hook().  Block until the last running instance
1243  * of the callback returns before clearing it.
1244  *
1245  * The caller is responsible for the appropriate ordering of the invocations of
1246  * this function with respect to the enumeration of the PCI devices needing the
1247  * callback cleared by it.
1248  */
1249 void pci_acpi_clear_companion_lookup_hook(void)
1250 {
1251     down_write(&pci_acpi_companion_lookup_sem);
1252 
1253     pci_acpi_find_companion_hook = NULL;
1254 
1255     up_write(&pci_acpi_companion_lookup_sem);
1256 }
1257 EXPORT_SYMBOL_GPL(pci_acpi_clear_companion_lookup_hook);
1258 
1259 static struct acpi_device *acpi_pci_find_companion(struct device *dev)
1260 {
1261     struct pci_dev *pci_dev = to_pci_dev(dev);
1262     struct acpi_device *adev;
1263     bool check_children;
1264     u64 addr;
1265 
1266     if (!dev->parent)
1267         return NULL;
1268 
1269     down_read(&pci_acpi_companion_lookup_sem);
1270 
1271     adev = pci_acpi_find_companion_hook ?
1272         pci_acpi_find_companion_hook(pci_dev) : NULL;
1273 
1274     up_read(&pci_acpi_companion_lookup_sem);
1275 
1276     if (adev)
1277         return adev;
1278 
1279     check_children = pci_is_bridge(pci_dev);
1280     /* Please ref to ACPI spec for the syntax of _ADR */
1281     addr = (PCI_SLOT(pci_dev->devfn) << 16) | PCI_FUNC(pci_dev->devfn);
1282     adev = acpi_find_child_device(ACPI_COMPANION(dev->parent), addr,
1283                       check_children);
1284 
1285     /*
1286      * There may be ACPI device objects in the ACPI namespace that are
1287      * children of the device object representing the host bridge, but don't
1288      * represent PCI devices.  Both _HID and _ADR may be present for them,
1289      * even though that is against the specification (for example, see
1290      * Section 6.1 of ACPI 6.3), but in many cases the _ADR returns 0 which
1291      * appears to indicate that they should not be taken into consideration
1292      * as potential companions of PCI devices on the root bus.
1293      *
1294      * To catch this special case, disregard the returned device object if
1295      * it has a valid _HID, addr is 0 and the PCI device at hand is on the
1296      * root bus.
1297      */
1298     if (adev && adev->pnp.type.platform_id && !addr &&
1299         pci_is_root_bus(pci_dev->bus))
1300         return NULL;
1301 
1302     return adev;
1303 }
1304 
1305 /**
1306  * pci_acpi_optimize_delay - optimize PCI D3 and D3cold delay from ACPI
1307  * @pdev: the PCI device whose delay is to be updated
1308  * @handle: ACPI handle of this device
1309  *
1310  * Update the d3hot_delay and d3cold_delay of a PCI device from the ACPI _DSM
1311  * control method of either the device itself or the PCI host bridge.
1312  *
1313  * Function 8, "Reset Delay," applies to the entire hierarchy below a PCI
1314  * host bridge.  If it returns one, the OS may assume that all devices in
1315  * the hierarchy have already completed power-on reset delays.
1316  *
1317  * Function 9, "Device Readiness Durations," applies only to the object
1318  * where it is located.  It returns delay durations required after various
1319  * events if the device requires less time than the spec requires.  Delays
1320  * from this function take precedence over the Reset Delay function.
1321  *
1322  * These _DSM functions are defined by the draft ECN of January 28, 2014,
1323  * titled "ACPI additions for FW latency optimizations."
1324  */
1325 static void pci_acpi_optimize_delay(struct pci_dev *pdev,
1326                     acpi_handle handle)
1327 {
1328     struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
1329     int value;
1330     union acpi_object *obj, *elements;
1331 
1332     if (bridge->ignore_reset_delay)
1333         pdev->d3cold_delay = 0;
1334 
1335     obj = acpi_evaluate_dsm(handle, &pci_acpi_dsm_guid, 3,
1336                 DSM_PCI_DEVICE_READINESS_DURATIONS, NULL);
1337     if (!obj)
1338         return;
1339 
1340     if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 5) {
1341         elements = obj->package.elements;
1342         if (elements[0].type == ACPI_TYPE_INTEGER) {
1343             value = (int)elements[0].integer.value / 1000;
1344             if (value < PCI_PM_D3COLD_WAIT)
1345                 pdev->d3cold_delay = value;
1346         }
1347         if (elements[3].type == ACPI_TYPE_INTEGER) {
1348             value = (int)elements[3].integer.value / 1000;
1349             if (value < PCI_PM_D3HOT_WAIT)
1350                 pdev->d3hot_delay = value;
1351         }
1352     }
1353     ACPI_FREE(obj);
1354 }
1355 
1356 static void pci_acpi_set_external_facing(struct pci_dev *dev)
1357 {
1358     u8 val;
1359 
1360     if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1361         return;
1362     if (device_property_read_u8(&dev->dev, "ExternalFacingPort", &val))
1363         return;
1364 
1365     /*
1366      * These root ports expose PCIe (including DMA) outside of the
1367      * system.  Everything downstream from them is external.
1368      */
1369     if (val)
1370         dev->external_facing = 1;
1371 }
1372 
1373 void pci_acpi_setup(struct device *dev, struct acpi_device *adev)
1374 {
1375     struct pci_dev *pci_dev = to_pci_dev(dev);
1376 
1377     pci_acpi_optimize_delay(pci_dev, adev->handle);
1378     pci_acpi_set_external_facing(pci_dev);
1379     pci_acpi_add_edr_notifier(pci_dev);
1380 
1381     pci_acpi_add_pm_notifier(adev, pci_dev);
1382     if (!adev->wakeup.flags.valid)
1383         return;
1384 
1385     device_set_wakeup_capable(dev, true);
1386     /*
1387      * For bridges that can do D3 we enable wake automatically (as
1388      * we do for the power management itself in that case). The
1389      * reason is that the bridge may have additional methods such as
1390      * _DSW that need to be called.
1391      */
1392     if (pci_dev->bridge_d3)
1393         device_wakeup_enable(dev);
1394 
1395     acpi_pci_wakeup(pci_dev, false);
1396     acpi_device_power_add_dependent(adev, dev);
1397 
1398     if (pci_is_bridge(pci_dev))
1399         acpi_dev_power_up_children_with_adr(adev);
1400 }
1401 
1402 void pci_acpi_cleanup(struct device *dev, struct acpi_device *adev)
1403 {
1404     struct pci_dev *pci_dev = to_pci_dev(dev);
1405 
1406     pci_acpi_remove_edr_notifier(pci_dev);
1407     pci_acpi_remove_pm_notifier(adev);
1408     if (adev->wakeup.flags.valid) {
1409         acpi_device_power_remove_dependent(adev, dev);
1410         if (pci_dev->bridge_d3)
1411             device_wakeup_disable(dev);
1412 
1413         device_set_wakeup_capable(dev, false);
1414     }
1415 }
1416 
1417 static struct fwnode_handle *(*pci_msi_get_fwnode_cb)(struct device *dev);
1418 
1419 /**
1420  * pci_msi_register_fwnode_provider - Register callback to retrieve fwnode
1421  * @fn:       Callback matching a device to a fwnode that identifies a PCI
1422  *            MSI domain.
1423  *
1424  * This should be called by irqchip driver, which is the parent of
1425  * the MSI domain to provide callback interface to query fwnode.
1426  */
1427 void
1428 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *))
1429 {
1430     pci_msi_get_fwnode_cb = fn;
1431 }
1432 
1433 /**
1434  * pci_host_bridge_acpi_msi_domain - Retrieve MSI domain of a PCI host bridge
1435  * @bus:      The PCI host bridge bus.
1436  *
1437  * This function uses the callback function registered by
1438  * pci_msi_register_fwnode_provider() to retrieve the irq_domain with
1439  * type DOMAIN_BUS_PCI_MSI of the specified host bridge bus.
1440  * This returns NULL on error or when the domain is not found.
1441  */
1442 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus)
1443 {
1444     struct fwnode_handle *fwnode;
1445 
1446     if (!pci_msi_get_fwnode_cb)
1447         return NULL;
1448 
1449     fwnode = pci_msi_get_fwnode_cb(&bus->dev);
1450     if (!fwnode)
1451         return NULL;
1452 
1453     return irq_find_matching_fwnode(fwnode, DOMAIN_BUS_PCI_MSI);
1454 }
1455 
1456 static int __init acpi_pci_init(void)
1457 {
1458     if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_MSI) {
1459         pr_info("ACPI FADT declares the system doesn't support MSI, so disable it\n");
1460         pci_no_msi();
1461     }
1462 
1463     if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) {
1464         pr_info("ACPI FADT declares the system doesn't support PCIe ASPM, so disable it\n");
1465         pcie_no_aspm();
1466     }
1467 
1468     if (acpi_pci_disabled)
1469         return 0;
1470 
1471     acpi_pci_slot_init();
1472     acpiphp_init();
1473 
1474     return 0;
1475 }
1476 arch_initcall(acpi_pci_init);
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