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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Standard PCI Hot Plug Driver
0004  *
0005  * Copyright (C) 1995,2001 Compaq Computer Corporation
0006  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
0007  * Copyright (C) 2001 IBM Corp.
0008  * Copyright (C) 2003-2004 Intel Corporation
0009  *
0010  * All rights reserved.
0011  *
0012  * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
0013  *
0014  */
0015 
0016 #include <linux/kernel.h>
0017 #include <linux/module.h>
0018 #include <linux/types.h>
0019 #include <linux/pci.h>
0020 #include <linux/interrupt.h>
0021 
0022 #include "shpchp.h"
0023 
0024 /* Slot Available Register I field definition */
0025 #define SLOT_33MHZ      0x0000001f
0026 #define SLOT_66MHZ_PCIX     0x00001f00
0027 #define SLOT_100MHZ_PCIX    0x001f0000
0028 #define SLOT_133MHZ_PCIX    0x1f000000
0029 
0030 /* Slot Available Register II field definition */
0031 #define SLOT_66MHZ      0x0000001f
0032 #define SLOT_66MHZ_PCIX_266 0x00000f00
0033 #define SLOT_100MHZ_PCIX_266    0x0000f000
0034 #define SLOT_133MHZ_PCIX_266    0x000f0000
0035 #define SLOT_66MHZ_PCIX_533 0x00f00000
0036 #define SLOT_100MHZ_PCIX_533    0x0f000000
0037 #define SLOT_133MHZ_PCIX_533    0xf0000000
0038 
0039 /* Slot Configuration */
0040 #define SLOT_NUM        0x0000001F
0041 #define FIRST_DEV_NUM       0x00001F00
0042 #define PSN         0x07FF0000
0043 #define UPDOWN          0x20000000
0044 #define MRLSENSOR       0x40000000
0045 #define ATTN_BUTTON     0x80000000
0046 
0047 /*
0048  * Interrupt Locator Register definitions
0049  */
0050 #define CMD_INTR_PENDING    (1 << 0)
0051 #define SLOT_INTR_PENDING(i)    (1 << (i + 1))
0052 
0053 /*
0054  * Controller SERR-INT Register
0055  */
0056 #define GLOBAL_INTR_MASK    (1 << 0)
0057 #define GLOBAL_SERR_MASK    (1 << 1)
0058 #define COMMAND_INTR_MASK   (1 << 2)
0059 #define ARBITER_SERR_MASK   (1 << 3)
0060 #define COMMAND_DETECTED    (1 << 16)
0061 #define ARBITER_DETECTED    (1 << 17)
0062 #define SERR_INTR_RSVDZ_MASK    0xfffc0000
0063 
0064 /*
0065  * Logical Slot Register definitions
0066  */
0067 #define SLOT_REG(i)     (SLOT1 + (4 * i))
0068 
0069 #define SLOT_STATE_SHIFT    (0)
0070 #define SLOT_STATE_MASK     (3 << 0)
0071 #define SLOT_STATE_PWRONLY  (1)
0072 #define SLOT_STATE_ENABLED  (2)
0073 #define SLOT_STATE_DISABLED (3)
0074 #define PWR_LED_STATE_SHIFT (2)
0075 #define PWR_LED_STATE_MASK  (3 << 2)
0076 #define ATN_LED_STATE_SHIFT (4)
0077 #define ATN_LED_STATE_MASK  (3 << 4)
0078 #define ATN_LED_STATE_ON    (1)
0079 #define ATN_LED_STATE_BLINK (2)
0080 #define ATN_LED_STATE_OFF   (3)
0081 #define POWER_FAULT     (1 << 6)
0082 #define ATN_BUTTON      (1 << 7)
0083 #define MRL_SENSOR      (1 << 8)
0084 #define MHZ66_CAP       (1 << 9)
0085 #define PRSNT_SHIFT     (10)
0086 #define PRSNT_MASK      (3 << 10)
0087 #define PCIX_CAP_SHIFT      (12)
0088 #define PCIX_CAP_MASK_PI1   (3 << 12)
0089 #define PCIX_CAP_MASK_PI2   (7 << 12)
0090 #define PRSNT_CHANGE_DETECTED   (1 << 16)
0091 #define ISO_PFAULT_DETECTED (1 << 17)
0092 #define BUTTON_PRESS_DETECTED   (1 << 18)
0093 #define MRL_CHANGE_DETECTED (1 << 19)
0094 #define CON_PFAULT_DETECTED (1 << 20)
0095 #define PRSNT_CHANGE_INTR_MASK  (1 << 24)
0096 #define ISO_PFAULT_INTR_MASK    (1 << 25)
0097 #define BUTTON_PRESS_INTR_MASK  (1 << 26)
0098 #define MRL_CHANGE_INTR_MASK    (1 << 27)
0099 #define CON_PFAULT_INTR_MASK    (1 << 28)
0100 #define MRL_CHANGE_SERR_MASK    (1 << 29)
0101 #define CON_PFAULT_SERR_MASK    (1 << 30)
0102 #define SLOT_REG_RSVDZ_MASK ((1 << 15) | (7 << 21))
0103 
0104 /*
0105  * SHPC Command Code definitions
0106  *
0107  *     Slot Operation               00h - 3Fh
0108  *     Set Bus Segment Speed/Mode A     40h - 47h
0109  *     Power-Only All Slots         48h
0110  *     Enable All Slots             49h
0111  *     Set Bus Segment Speed/Mode B (PI=2)  50h - 5Fh
0112  *     Reserved Command Codes           60h - BFh
0113  *     Vendor Specific Commands         C0h - FFh
0114  */
0115 #define SET_SLOT_PWR        0x01    /* Slot Operation */
0116 #define SET_SLOT_ENABLE     0x02
0117 #define SET_SLOT_DISABLE    0x03
0118 #define SET_PWR_ON      0x04
0119 #define SET_PWR_BLINK       0x08
0120 #define SET_PWR_OFF     0x0c
0121 #define SET_ATTN_ON     0x10
0122 #define SET_ATTN_BLINK      0x20
0123 #define SET_ATTN_OFF        0x30
0124 #define SETA_PCI_33MHZ      0x40    /* Set Bus Segment Speed/Mode A */
0125 #define SETA_PCI_66MHZ      0x41
0126 #define SETA_PCIX_66MHZ     0x42
0127 #define SETA_PCIX_100MHZ    0x43
0128 #define SETA_PCIX_133MHZ    0x44
0129 #define SETA_RESERVED1      0x45
0130 #define SETA_RESERVED2      0x46
0131 #define SETA_RESERVED3      0x47
0132 #define SET_PWR_ONLY_ALL    0x48    /* Power-Only All Slots */
0133 #define SET_ENABLE_ALL      0x49    /* Enable All Slots */
0134 #define SETB_PCI_33MHZ      0x50    /* Set Bus Segment Speed/Mode B */
0135 #define SETB_PCI_66MHZ      0x51
0136 #define SETB_PCIX_66MHZ_PM  0x52
0137 #define SETB_PCIX_100MHZ_PM 0x53
0138 #define SETB_PCIX_133MHZ_PM 0x54
0139 #define SETB_PCIX_66MHZ_EM  0x55
0140 #define SETB_PCIX_100MHZ_EM 0x56
0141 #define SETB_PCIX_133MHZ_EM 0x57
0142 #define SETB_PCIX_66MHZ_266 0x58
0143 #define SETB_PCIX_100MHZ_266    0x59
0144 #define SETB_PCIX_133MHZ_266    0x5a
0145 #define SETB_PCIX_66MHZ_533 0x5b
0146 #define SETB_PCIX_100MHZ_533    0x5c
0147 #define SETB_PCIX_133MHZ_533    0x5d
0148 #define SETB_RESERVED1      0x5e
0149 #define SETB_RESERVED2      0x5f
0150 
0151 /*
0152  * SHPC controller command error code
0153  */
0154 #define SWITCH_OPEN     0x1
0155 #define INVALID_CMD     0x2
0156 #define INVALID_SPEED_MODE  0x4
0157 
0158 /*
0159  * For accessing SHPC Working Register Set via PCI Configuration Space
0160  */
0161 #define DWORD_SELECT        0x2
0162 #define DWORD_DATA      0x4
0163 
0164 /* Field Offset in Logical Slot Register - byte boundary */
0165 #define SLOT_EVENT_LATCH    0x2
0166 #define SLOT_SERR_INT_MASK  0x3
0167 
0168 static irqreturn_t shpc_isr(int irq, void *dev_id);
0169 static void start_int_poll_timer(struct controller *ctrl, int sec);
0170 static int hpc_check_cmd_status(struct controller *ctrl);
0171 
0172 static inline u8 shpc_readb(struct controller *ctrl, int reg)
0173 {
0174     return readb(ctrl->creg + reg);
0175 }
0176 
0177 static inline u16 shpc_readw(struct controller *ctrl, int reg)
0178 {
0179     return readw(ctrl->creg + reg);
0180 }
0181 
0182 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)
0183 {
0184     writew(val, ctrl->creg + reg);
0185 }
0186 
0187 static inline u32 shpc_readl(struct controller *ctrl, int reg)
0188 {
0189     return readl(ctrl->creg + reg);
0190 }
0191 
0192 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)
0193 {
0194     writel(val, ctrl->creg + reg);
0195 }
0196 
0197 static inline int shpc_indirect_read(struct controller *ctrl, int index,
0198                      u32 *value)
0199 {
0200     int rc;
0201     u32 cap_offset = ctrl->cap_offset;
0202     struct pci_dev *pdev = ctrl->pci_dev;
0203 
0204     rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index);
0205     if (rc)
0206         return rc;
0207     return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
0208 }
0209 
0210 /*
0211  * This is the interrupt polling timeout function.
0212  */
0213 static void int_poll_timeout(struct timer_list *t)
0214 {
0215     struct controller *ctrl = from_timer(ctrl, t, poll_timer);
0216 
0217     /* Poll for interrupt events.  regs == NULL => polling */
0218     shpc_isr(0, ctrl);
0219 
0220     if (!shpchp_poll_time)
0221         shpchp_poll_time = 2; /* default polling interval is 2 sec */
0222 
0223     start_int_poll_timer(ctrl, shpchp_poll_time);
0224 }
0225 
0226 /*
0227  * This function starts the interrupt polling timer.
0228  */
0229 static void start_int_poll_timer(struct controller *ctrl, int sec)
0230 {
0231     /* Clamp to sane value */
0232     if ((sec <= 0) || (sec > 60))
0233         sec = 2;
0234 
0235     ctrl->poll_timer.expires = jiffies + sec * HZ;
0236     add_timer(&ctrl->poll_timer);
0237 }
0238 
0239 static inline int is_ctrl_busy(struct controller *ctrl)
0240 {
0241     u16 cmd_status = shpc_readw(ctrl, CMD_STATUS);
0242     return cmd_status & 0x1;
0243 }
0244 
0245 /*
0246  * Returns 1 if SHPC finishes executing a command within 1 sec,
0247  * otherwise returns 0.
0248  */
0249 static inline int shpc_poll_ctrl_busy(struct controller *ctrl)
0250 {
0251     int i;
0252 
0253     if (!is_ctrl_busy(ctrl))
0254         return 1;
0255 
0256     /* Check every 0.1 sec for a total of 1 sec */
0257     for (i = 0; i < 10; i++) {
0258         msleep(100);
0259         if (!is_ctrl_busy(ctrl))
0260             return 1;
0261     }
0262 
0263     return 0;
0264 }
0265 
0266 static inline int shpc_wait_cmd(struct controller *ctrl)
0267 {
0268     int retval = 0;
0269     unsigned long timeout = msecs_to_jiffies(1000);
0270     int rc;
0271 
0272     if (shpchp_poll_mode)
0273         rc = shpc_poll_ctrl_busy(ctrl);
0274     else
0275         rc = wait_event_interruptible_timeout(ctrl->queue,
0276                         !is_ctrl_busy(ctrl), timeout);
0277     if (!rc && is_ctrl_busy(ctrl)) {
0278         retval = -EIO;
0279         ctrl_err(ctrl, "Command not completed in 1000 msec\n");
0280     } else if (rc < 0) {
0281         retval = -EINTR;
0282         ctrl_info(ctrl, "Command was interrupted by a signal\n");
0283     }
0284 
0285     return retval;
0286 }
0287 
0288 static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
0289 {
0290     struct controller *ctrl = slot->ctrl;
0291     u16 cmd_status;
0292     int retval = 0;
0293     u16 temp_word;
0294 
0295     mutex_lock(&slot->ctrl->cmd_lock);
0296 
0297     if (!shpc_poll_ctrl_busy(ctrl)) {
0298         /* After 1 sec and the controller is still busy */
0299         ctrl_err(ctrl, "Controller is still busy after 1 sec\n");
0300         retval = -EBUSY;
0301         goto out;
0302     }
0303 
0304     ++t_slot;
0305     temp_word =  (t_slot << 8) | (cmd & 0xFF);
0306     ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd);
0307 
0308     /* To make sure the Controller Busy bit is 0 before we send out the
0309      * command.
0310      */
0311     shpc_writew(ctrl, CMD, temp_word);
0312 
0313     /*
0314      * Wait for command completion.
0315      */
0316     retval = shpc_wait_cmd(slot->ctrl);
0317     if (retval)
0318         goto out;
0319 
0320     cmd_status = hpc_check_cmd_status(slot->ctrl);
0321     if (cmd_status) {
0322         ctrl_err(ctrl, "Failed to issued command 0x%x (error code = %d)\n",
0323              cmd, cmd_status);
0324         retval = -EIO;
0325     }
0326  out:
0327     mutex_unlock(&slot->ctrl->cmd_lock);
0328     return retval;
0329 }
0330 
0331 static int hpc_check_cmd_status(struct controller *ctrl)
0332 {
0333     int retval = 0;
0334     u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
0335 
0336     switch (cmd_status >> 1) {
0337     case 0:
0338         retval = 0;
0339         break;
0340     case 1:
0341         retval = SWITCH_OPEN;
0342         ctrl_err(ctrl, "Switch opened!\n");
0343         break;
0344     case 2:
0345         retval = INVALID_CMD;
0346         ctrl_err(ctrl, "Invalid HPC command!\n");
0347         break;
0348     case 4:
0349         retval = INVALID_SPEED_MODE;
0350         ctrl_err(ctrl, "Invalid bus speed/mode!\n");
0351         break;
0352     default:
0353         retval = cmd_status;
0354     }
0355 
0356     return retval;
0357 }
0358 
0359 
0360 static int hpc_get_attention_status(struct slot *slot, u8 *status)
0361 {
0362     struct controller *ctrl = slot->ctrl;
0363     u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
0364     u8 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;
0365 
0366     switch (state) {
0367     case ATN_LED_STATE_ON:
0368         *status = 1;    /* On */
0369         break;
0370     case ATN_LED_STATE_BLINK:
0371         *status = 2;    /* Blink */
0372         break;
0373     case ATN_LED_STATE_OFF:
0374         *status = 0;    /* Off */
0375         break;
0376     default:
0377         *status = 0xFF; /* Reserved */
0378         break;
0379     }
0380 
0381     return 0;
0382 }
0383 
0384 static int hpc_get_power_status(struct slot *slot, u8 *status)
0385 {
0386     struct controller *ctrl = slot->ctrl;
0387     u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
0388     u8 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;
0389 
0390     switch (state) {
0391     case SLOT_STATE_PWRONLY:
0392         *status = 2;    /* Powered only */
0393         break;
0394     case SLOT_STATE_ENABLED:
0395         *status = 1;    /* Enabled */
0396         break;
0397     case SLOT_STATE_DISABLED:
0398         *status = 0;    /* Disabled */
0399         break;
0400     default:
0401         *status = 0xFF; /* Reserved */
0402         break;
0403     }
0404 
0405     return 0;
0406 }
0407 
0408 
0409 static int hpc_get_latch_status(struct slot *slot, u8 *status)
0410 {
0411     struct controller *ctrl = slot->ctrl;
0412     u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
0413 
0414     *status = !!(slot_reg & MRL_SENSOR);    /* 0 -> close; 1 -> open */
0415 
0416     return 0;
0417 }
0418 
0419 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
0420 {
0421     struct controller *ctrl = slot->ctrl;
0422     u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
0423     u8 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;
0424 
0425     *status = (state != 0x3) ? 1 : 0;
0426 
0427     return 0;
0428 }
0429 
0430 static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
0431 {
0432     struct controller *ctrl = slot->ctrl;
0433 
0434     *prog_int = shpc_readb(ctrl, PROG_INTERFACE);
0435 
0436     return 0;
0437 }
0438 
0439 static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
0440 {
0441     int retval = 0;
0442     struct controller *ctrl = slot->ctrl;
0443     u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
0444     u8 m66_cap  = !!(slot_reg & MHZ66_CAP);
0445     u8 pi, pcix_cap;
0446 
0447     retval = hpc_get_prog_int(slot, &pi);
0448     if (retval)
0449         return retval;
0450 
0451     switch (pi) {
0452     case 1:
0453         pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT;
0454         break;
0455     case 2:
0456         pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT;
0457         break;
0458     default:
0459         return -ENODEV;
0460     }
0461 
0462     ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
0463          __func__, slot_reg, pcix_cap, m66_cap);
0464 
0465     switch (pcix_cap) {
0466     case 0x0:
0467         *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
0468         break;
0469     case 0x1:
0470         *value = PCI_SPEED_66MHz_PCIX;
0471         break;
0472     case 0x3:
0473         *value = PCI_SPEED_133MHz_PCIX;
0474         break;
0475     case 0x4:
0476         *value = PCI_SPEED_133MHz_PCIX_266;
0477         break;
0478     case 0x5:
0479         *value = PCI_SPEED_133MHz_PCIX_533;
0480         break;
0481     case 0x2:
0482     default:
0483         *value = PCI_SPEED_UNKNOWN;
0484         retval = -ENODEV;
0485         break;
0486     }
0487 
0488     ctrl_dbg(ctrl, "Adapter speed = %d\n", *value);
0489     return retval;
0490 }
0491 
0492 static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
0493 {
0494     int retval = 0;
0495     struct controller *ctrl = slot->ctrl;
0496     u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
0497     u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
0498 
0499     if (pi == 2) {
0500         *mode = (sec_bus_status & 0x0100) >> 8;
0501     } else {
0502         retval = -1;
0503     }
0504 
0505     ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode);
0506     return retval;
0507 }
0508 
0509 static int hpc_query_power_fault(struct slot *slot)
0510 {
0511     struct controller *ctrl = slot->ctrl;
0512     u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
0513 
0514     /* Note: Logic 0 => fault */
0515     return !(slot_reg & POWER_FAULT);
0516 }
0517 
0518 static int hpc_set_attention_status(struct slot *slot, u8 value)
0519 {
0520     u8 slot_cmd = 0;
0521 
0522     switch (value) {
0523         case 0:
0524             slot_cmd = SET_ATTN_OFF;    /* OFF */
0525             break;
0526         case 1:
0527             slot_cmd = SET_ATTN_ON;     /* ON */
0528             break;
0529         case 2:
0530             slot_cmd = SET_ATTN_BLINK;  /* BLINK */
0531             break;
0532         default:
0533             return -1;
0534     }
0535 
0536     return shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
0537 }
0538 
0539 
0540 static void hpc_set_green_led_on(struct slot *slot)
0541 {
0542     shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON);
0543 }
0544 
0545 static void hpc_set_green_led_off(struct slot *slot)
0546 {
0547     shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF);
0548 }
0549 
0550 static void hpc_set_green_led_blink(struct slot *slot)
0551 {
0552     shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK);
0553 }
0554 
0555 static void hpc_release_ctlr(struct controller *ctrl)
0556 {
0557     int i;
0558     u32 slot_reg, serr_int;
0559 
0560     /*
0561      * Mask event interrupts and SERRs of all slots
0562      */
0563     for (i = 0; i < ctrl->num_slots; i++) {
0564         slot_reg = shpc_readl(ctrl, SLOT_REG(i));
0565         slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
0566                  BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
0567                  CON_PFAULT_INTR_MASK   | MRL_CHANGE_SERR_MASK |
0568                  CON_PFAULT_SERR_MASK);
0569         slot_reg &= ~SLOT_REG_RSVDZ_MASK;
0570         shpc_writel(ctrl, SLOT_REG(i), slot_reg);
0571     }
0572 
0573     cleanup_slots(ctrl);
0574 
0575     /*
0576      * Mask SERR and System Interrupt generation
0577      */
0578     serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
0579     serr_int |= (GLOBAL_INTR_MASK  | GLOBAL_SERR_MASK |
0580              COMMAND_INTR_MASK | ARBITER_SERR_MASK);
0581     serr_int &= ~SERR_INTR_RSVDZ_MASK;
0582     shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
0583 
0584     if (shpchp_poll_mode)
0585         del_timer(&ctrl->poll_timer);
0586     else {
0587         free_irq(ctrl->pci_dev->irq, ctrl);
0588         pci_disable_msi(ctrl->pci_dev);
0589     }
0590 
0591     iounmap(ctrl->creg);
0592     release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
0593 }
0594 
0595 static int hpc_power_on_slot(struct slot *slot)
0596 {
0597     int retval;
0598 
0599     retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR);
0600     if (retval)
0601         ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
0602 
0603     return retval;
0604 }
0605 
0606 static int hpc_slot_enable(struct slot *slot)
0607 {
0608     int retval;
0609 
0610     /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
0611     retval = shpc_write_cmd(slot, slot->hp_slot,
0612             SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF);
0613     if (retval)
0614         ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
0615 
0616     return retval;
0617 }
0618 
0619 static int hpc_slot_disable(struct slot *slot)
0620 {
0621     int retval;
0622 
0623     /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */
0624     retval = shpc_write_cmd(slot, slot->hp_slot,
0625             SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON);
0626     if (retval)
0627         ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
0628 
0629     return retval;
0630 }
0631 
0632 static int shpc_get_cur_bus_speed(struct controller *ctrl)
0633 {
0634     int retval = 0;
0635     struct pci_bus *bus = ctrl->pci_dev->subordinate;
0636     enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
0637     u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);
0638     u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
0639     u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);
0640 
0641     if ((pi == 1) && (speed_mode > 4)) {
0642         retval = -ENODEV;
0643         goto out;
0644     }
0645 
0646     switch (speed_mode) {
0647     case 0x0:
0648         bus_speed = PCI_SPEED_33MHz;
0649         break;
0650     case 0x1:
0651         bus_speed = PCI_SPEED_66MHz;
0652         break;
0653     case 0x2:
0654         bus_speed = PCI_SPEED_66MHz_PCIX;
0655         break;
0656     case 0x3:
0657         bus_speed = PCI_SPEED_100MHz_PCIX;
0658         break;
0659     case 0x4:
0660         bus_speed = PCI_SPEED_133MHz_PCIX;
0661         break;
0662     case 0x5:
0663         bus_speed = PCI_SPEED_66MHz_PCIX_ECC;
0664         break;
0665     case 0x6:
0666         bus_speed = PCI_SPEED_100MHz_PCIX_ECC;
0667         break;
0668     case 0x7:
0669         bus_speed = PCI_SPEED_133MHz_PCIX_ECC;
0670         break;
0671     case 0x8:
0672         bus_speed = PCI_SPEED_66MHz_PCIX_266;
0673         break;
0674     case 0x9:
0675         bus_speed = PCI_SPEED_100MHz_PCIX_266;
0676         break;
0677     case 0xa:
0678         bus_speed = PCI_SPEED_133MHz_PCIX_266;
0679         break;
0680     case 0xb:
0681         bus_speed = PCI_SPEED_66MHz_PCIX_533;
0682         break;
0683     case 0xc:
0684         bus_speed = PCI_SPEED_100MHz_PCIX_533;
0685         break;
0686     case 0xd:
0687         bus_speed = PCI_SPEED_133MHz_PCIX_533;
0688         break;
0689     default:
0690         retval = -ENODEV;
0691         break;
0692     }
0693 
0694  out:
0695     bus->cur_bus_speed = bus_speed;
0696     dbg("Current bus speed = %d\n", bus_speed);
0697     return retval;
0698 }
0699 
0700 
0701 static int hpc_set_bus_speed_mode(struct slot *slot, enum pci_bus_speed value)
0702 {
0703     int retval;
0704     struct controller *ctrl = slot->ctrl;
0705     u8 pi, cmd;
0706 
0707     pi = shpc_readb(ctrl, PROG_INTERFACE);
0708     if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))
0709         return -EINVAL;
0710 
0711     switch (value) {
0712     case PCI_SPEED_33MHz:
0713         cmd = SETA_PCI_33MHZ;
0714         break;
0715     case PCI_SPEED_66MHz:
0716         cmd = SETA_PCI_66MHZ;
0717         break;
0718     case PCI_SPEED_66MHz_PCIX:
0719         cmd = SETA_PCIX_66MHZ;
0720         break;
0721     case PCI_SPEED_100MHz_PCIX:
0722         cmd = SETA_PCIX_100MHZ;
0723         break;
0724     case PCI_SPEED_133MHz_PCIX:
0725         cmd = SETA_PCIX_133MHZ;
0726         break;
0727     case PCI_SPEED_66MHz_PCIX_ECC:
0728         cmd = SETB_PCIX_66MHZ_EM;
0729         break;
0730     case PCI_SPEED_100MHz_PCIX_ECC:
0731         cmd = SETB_PCIX_100MHZ_EM;
0732         break;
0733     case PCI_SPEED_133MHz_PCIX_ECC:
0734         cmd = SETB_PCIX_133MHZ_EM;
0735         break;
0736     case PCI_SPEED_66MHz_PCIX_266:
0737         cmd = SETB_PCIX_66MHZ_266;
0738         break;
0739     case PCI_SPEED_100MHz_PCIX_266:
0740         cmd = SETB_PCIX_100MHZ_266;
0741         break;
0742     case PCI_SPEED_133MHz_PCIX_266:
0743         cmd = SETB_PCIX_133MHZ_266;
0744         break;
0745     case PCI_SPEED_66MHz_PCIX_533:
0746         cmd = SETB_PCIX_66MHZ_533;
0747         break;
0748     case PCI_SPEED_100MHz_PCIX_533:
0749         cmd = SETB_PCIX_100MHZ_533;
0750         break;
0751     case PCI_SPEED_133MHz_PCIX_533:
0752         cmd = SETB_PCIX_133MHZ_533;
0753         break;
0754     default:
0755         return -EINVAL;
0756     }
0757 
0758     retval = shpc_write_cmd(slot, 0, cmd);
0759     if (retval)
0760         ctrl_err(ctrl, "%s: Write command failed!\n", __func__);
0761     else
0762         shpc_get_cur_bus_speed(ctrl);
0763 
0764     return retval;
0765 }
0766 
0767 static irqreturn_t shpc_isr(int irq, void *dev_id)
0768 {
0769     struct controller *ctrl = (struct controller *)dev_id;
0770     u32 serr_int, slot_reg, intr_loc, intr_loc2;
0771     int hp_slot;
0772 
0773     /* Check to see if it was our interrupt */
0774     intr_loc = shpc_readl(ctrl, INTR_LOC);
0775     if (!intr_loc)
0776         return IRQ_NONE;
0777 
0778     ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc);
0779 
0780     if (!shpchp_poll_mode) {
0781         /*
0782          * Mask Global Interrupt Mask - see implementation
0783          * note on p. 139 of SHPC spec rev 1.0
0784          */
0785         serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
0786         serr_int |= GLOBAL_INTR_MASK;
0787         serr_int &= ~SERR_INTR_RSVDZ_MASK;
0788         shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
0789 
0790         intr_loc2 = shpc_readl(ctrl, INTR_LOC);
0791         ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2);
0792     }
0793 
0794     if (intr_loc & CMD_INTR_PENDING) {
0795         /*
0796          * Command Complete Interrupt Pending
0797          * RO only - clear by writing 1 to the Command Completion
0798          * Detect bit in Controller SERR-INT register
0799          */
0800         serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
0801         serr_int &= ~SERR_INTR_RSVDZ_MASK;
0802         shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
0803 
0804         wake_up_interruptible(&ctrl->queue);
0805     }
0806 
0807     if (!(intr_loc & ~CMD_INTR_PENDING))
0808         goto out;
0809 
0810     for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
0811         /* To find out which slot has interrupt pending */
0812         if (!(intr_loc & SLOT_INTR_PENDING(hp_slot)))
0813             continue;
0814 
0815         slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
0816         ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n",
0817              hp_slot, slot_reg);
0818 
0819         if (slot_reg & MRL_CHANGE_DETECTED)
0820             shpchp_handle_switch_change(hp_slot, ctrl);
0821 
0822         if (slot_reg & BUTTON_PRESS_DETECTED)
0823             shpchp_handle_attention_button(hp_slot, ctrl);
0824 
0825         if (slot_reg & PRSNT_CHANGE_DETECTED)
0826             shpchp_handle_presence_change(hp_slot, ctrl);
0827 
0828         if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED))
0829             shpchp_handle_power_fault(hp_slot, ctrl);
0830 
0831         /* Clear all slot events */
0832         slot_reg &= ~SLOT_REG_RSVDZ_MASK;
0833         shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
0834     }
0835  out:
0836     if (!shpchp_poll_mode) {
0837         /* Unmask Global Interrupt Mask */
0838         serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
0839         serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK);
0840         shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
0841     }
0842 
0843     return IRQ_HANDLED;
0844 }
0845 
0846 static int shpc_get_max_bus_speed(struct controller *ctrl)
0847 {
0848     int retval = 0;
0849     struct pci_bus *bus = ctrl->pci_dev->subordinate;
0850     enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
0851     u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
0852     u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
0853     u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
0854 
0855     if (pi == 2) {
0856         if (slot_avail2 & SLOT_133MHZ_PCIX_533)
0857             bus_speed = PCI_SPEED_133MHz_PCIX_533;
0858         else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
0859             bus_speed = PCI_SPEED_100MHz_PCIX_533;
0860         else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
0861             bus_speed = PCI_SPEED_66MHz_PCIX_533;
0862         else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
0863             bus_speed = PCI_SPEED_133MHz_PCIX_266;
0864         else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
0865             bus_speed = PCI_SPEED_100MHz_PCIX_266;
0866         else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
0867             bus_speed = PCI_SPEED_66MHz_PCIX_266;
0868     }
0869 
0870     if (bus_speed == PCI_SPEED_UNKNOWN) {
0871         if (slot_avail1 & SLOT_133MHZ_PCIX)
0872             bus_speed = PCI_SPEED_133MHz_PCIX;
0873         else if (slot_avail1 & SLOT_100MHZ_PCIX)
0874             bus_speed = PCI_SPEED_100MHz_PCIX;
0875         else if (slot_avail1 & SLOT_66MHZ_PCIX)
0876             bus_speed = PCI_SPEED_66MHz_PCIX;
0877         else if (slot_avail2 & SLOT_66MHZ)
0878             bus_speed = PCI_SPEED_66MHz;
0879         else if (slot_avail1 & SLOT_33MHZ)
0880             bus_speed = PCI_SPEED_33MHz;
0881         else
0882             retval = -ENODEV;
0883     }
0884 
0885     bus->max_bus_speed = bus_speed;
0886     ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed);
0887 
0888     return retval;
0889 }
0890 
0891 static const struct hpc_ops shpchp_hpc_ops = {
0892     .power_on_slot          = hpc_power_on_slot,
0893     .slot_enable            = hpc_slot_enable,
0894     .slot_disable           = hpc_slot_disable,
0895     .set_bus_speed_mode     = hpc_set_bus_speed_mode,
0896     .set_attention_status   = hpc_set_attention_status,
0897     .get_power_status       = hpc_get_power_status,
0898     .get_attention_status   = hpc_get_attention_status,
0899     .get_latch_status       = hpc_get_latch_status,
0900     .get_adapter_status     = hpc_get_adapter_status,
0901 
0902     .get_adapter_speed      = hpc_get_adapter_speed,
0903     .get_mode1_ECC_cap      = hpc_get_mode1_ECC_cap,
0904     .get_prog_int           = hpc_get_prog_int,
0905 
0906     .query_power_fault      = hpc_query_power_fault,
0907     .green_led_on           = hpc_set_green_led_on,
0908     .green_led_off          = hpc_set_green_led_off,
0909     .green_led_blink        = hpc_set_green_led_blink,
0910 
0911     .release_ctlr           = hpc_release_ctlr,
0912 };
0913 
0914 int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
0915 {
0916     int rc = -1, num_slots = 0;
0917     u8 hp_slot;
0918     u32 shpc_base_offset;
0919     u32 tempdword, slot_reg, slot_config;
0920     u8 i;
0921 
0922     ctrl->pci_dev = pdev;  /* pci_dev of the P2P bridge */
0923     ctrl_dbg(ctrl, "Hotplug Controller:\n");
0924 
0925     if (pdev->vendor == PCI_VENDOR_ID_AMD &&
0926         pdev->device == PCI_DEVICE_ID_AMD_GOLAM_7450) {
0927         /* amd shpc driver doesn't use Base Offset; assume 0 */
0928         ctrl->mmio_base = pci_resource_start(pdev, 0);
0929         ctrl->mmio_size = pci_resource_len(pdev, 0);
0930     } else {
0931         ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
0932         if (!ctrl->cap_offset) {
0933             ctrl_err(ctrl, "Cannot find PCI capability\n");
0934             goto abort;
0935         }
0936         ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset);
0937 
0938         rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
0939         if (rc) {
0940             ctrl_err(ctrl, "Cannot read base_offset\n");
0941             goto abort;
0942         }
0943 
0944         rc = shpc_indirect_read(ctrl, 3, &tempdword);
0945         if (rc) {
0946             ctrl_err(ctrl, "Cannot read slot config\n");
0947             goto abort;
0948         }
0949         num_slots = tempdword & SLOT_NUM;
0950         ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots);
0951 
0952         for (i = 0; i < 9 + num_slots; i++) {
0953             rc = shpc_indirect_read(ctrl, i, &tempdword);
0954             if (rc) {
0955                 ctrl_err(ctrl, "Cannot read creg (index = %d)\n",
0956                      i);
0957                 goto abort;
0958             }
0959             ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword);
0960         }
0961 
0962         ctrl->mmio_base =
0963             pci_resource_start(pdev, 0) + shpc_base_offset;
0964         ctrl->mmio_size = 0x24 + 0x4 * num_slots;
0965     }
0966 
0967     ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
0968           pdev->vendor, pdev->device, pdev->subsystem_vendor,
0969           pdev->subsystem_device);
0970 
0971     rc = pci_enable_device(pdev);
0972     if (rc) {
0973         ctrl_err(ctrl, "pci_enable_device failed\n");
0974         goto abort;
0975     }
0976 
0977     if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
0978         ctrl_err(ctrl, "Cannot reserve MMIO region\n");
0979         rc = -1;
0980         goto abort;
0981     }
0982 
0983     ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
0984     if (!ctrl->creg) {
0985         ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n",
0986              ctrl->mmio_size, ctrl->mmio_base);
0987         release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
0988         rc = -1;
0989         goto abort;
0990     }
0991     ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg);
0992 
0993     mutex_init(&ctrl->crit_sect);
0994     mutex_init(&ctrl->cmd_lock);
0995 
0996     /* Setup wait queue */
0997     init_waitqueue_head(&ctrl->queue);
0998 
0999     ctrl->hpc_ops = &shpchp_hpc_ops;
1000 
1001     /* Return PCI Controller Info */
1002     slot_config = shpc_readl(ctrl, SLOT_CONFIG);
1003     ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;
1004     ctrl->num_slots = slot_config & SLOT_NUM;
1005     ctrl->first_slot = (slot_config & PSN) >> 16;
1006     ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1;
1007 
1008     /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
1009     tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1010     ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1011     tempdword |= (GLOBAL_INTR_MASK  | GLOBAL_SERR_MASK |
1012               COMMAND_INTR_MASK | ARBITER_SERR_MASK);
1013     tempdword &= ~SERR_INTR_RSVDZ_MASK;
1014     shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1015     tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1016     ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1017 
1018     /* Mask the MRL sensor SERR Mask of individual slot in
1019      * Slot SERR-INT Mask & clear all the existing event if any
1020      */
1021     for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1022         slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1023         ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
1024              hp_slot, slot_reg);
1025         slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1026                  BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1027                  CON_PFAULT_INTR_MASK   | MRL_CHANGE_SERR_MASK |
1028                  CON_PFAULT_SERR_MASK);
1029         slot_reg &= ~SLOT_REG_RSVDZ_MASK;
1030         shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1031     }
1032 
1033     if (shpchp_poll_mode) {
1034         /* Install interrupt polling timer. Start with 10 sec delay */
1035         timer_setup(&ctrl->poll_timer, int_poll_timeout, 0);
1036         start_int_poll_timer(ctrl, 10);
1037     } else {
1038         /* Installs the interrupt handler */
1039         rc = pci_enable_msi(pdev);
1040         if (rc) {
1041             ctrl_info(ctrl, "Can't get msi for the hotplug controller\n");
1042             ctrl_info(ctrl, "Use INTx for the hotplug controller\n");
1043         } else {
1044             pci_set_master(pdev);
1045         }
1046 
1047         rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED,
1048                  MY_NAME, (void *)ctrl);
1049         ctrl_dbg(ctrl, "request_irq %d (returns %d)\n",
1050              ctrl->pci_dev->irq, rc);
1051         if (rc) {
1052             ctrl_err(ctrl, "Can't get irq %d for the hotplug controller\n",
1053                  ctrl->pci_dev->irq);
1054             goto abort_iounmap;
1055         }
1056     }
1057     ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq);
1058 
1059     shpc_get_max_bus_speed(ctrl);
1060     shpc_get_cur_bus_speed(ctrl);
1061 
1062     /*
1063      * Unmask all event interrupts of all slots
1064      */
1065     for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1066         slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1067         ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
1068              hp_slot, slot_reg);
1069         slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1070                   BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1071                   CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK);
1072         shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1073     }
1074     if (!shpchp_poll_mode) {
1075         /* Unmask all general input interrupts and SERR */
1076         tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1077         tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK |
1078                    SERR_INTR_RSVDZ_MASK);
1079         shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1080         tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1081         ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1082     }
1083 
1084     return 0;
1085 
1086     /* We end up here for the many possible ways to fail this API.  */
1087 abort_iounmap:
1088     iounmap(ctrl->creg);
1089 abort:
1090     return rc;
1091 }
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